1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include "amdgpu_vm.h" 24 #include "amdgpu_vm_internal.h" 25 #include "amdgpu.h" 26 #include "amdgpu_reset.h" 27 #include "amdgpu_object.h" 28 #include "amdgpu_trace.h" 29 30 /** 31 * amdgpu_vm_cpu_map_table - make sure new PDs/PTs are kmapped 32 * 33 * @table: newly allocated or validated PD/PT 34 */ 35 static int amdgpu_vm_cpu_map_table(struct amdgpu_bo_vm *table) 36 { 37 table->bo.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 38 return amdgpu_bo_kmap(&table->bo, NULL); 39 } 40 41 /** 42 * amdgpu_vm_cpu_prepare - prepare page table update with the CPU 43 * 44 * @p: see amdgpu_vm_update_params definition 45 * @sync: sync obj with fences to wait on 46 * @k_job_id: the id for tracing/debug purposes 47 * 48 * Returns: 49 * Negativ errno, 0 for success. 50 */ 51 static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p, 52 struct amdgpu_sync *sync, 53 u64 k_job_id) 54 { 55 if (!sync) 56 return 0; 57 58 return amdgpu_sync_wait(sync, true); 59 } 60 61 /** 62 * amdgpu_vm_cpu_update - helper to update page tables via CPU 63 * 64 * @p: see amdgpu_vm_update_params definition 65 * @vmbo: PD/PT to update 66 * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB 67 * @addr: dst addr to write into pe 68 * @count: number of page entries to update 69 * @incr: increase next addr by incr bytes 70 * @flags: hw access flags 71 * 72 * Write count number of PT/PD entries directly. 73 */ 74 static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p, 75 struct amdgpu_bo_vm *vmbo, uint64_t pe, 76 uint64_t addr, unsigned count, uint32_t incr, 77 uint64_t flags) 78 { 79 unsigned int i; 80 uint64_t value; 81 long r; 82 83 r = dma_resv_wait_timeout(vmbo->bo.tbo.base.resv, DMA_RESV_USAGE_KERNEL, 84 true, MAX_SCHEDULE_TIMEOUT); 85 if (r < 0) 86 return r; 87 88 pe += (unsigned long)amdgpu_bo_kptr(&vmbo->bo); 89 90 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate); 91 92 if (!p->pages_addr && p->override_pte) 93 amdgpu_gmc_override_vm_pte_flags(p->adev, p->vm, addr, &flags); 94 95 for (i = 0; i < count; i++) { 96 u64 oflags = flags; 97 98 value = p->pages_addr ? 99 amdgpu_vm_map_gart(p->pages_addr, addr) : 100 addr; 101 102 if (p->pages_addr && p->override_pte) 103 amdgpu_gmc_override_vm_pte_flags(p->adev, p->vm, value, &oflags); 104 105 amdgpu_gmc_set_pte_pde(p->adev, (void *)(uintptr_t)pe, 106 i, value, oflags); 107 addr += incr; 108 } 109 return 0; 110 } 111 112 /** 113 * amdgpu_vm_cpu_commit - commit page table update to the HW 114 * 115 * @p: see amdgpu_vm_update_params definition 116 * @fence: unused 117 * 118 * Make sure that the hardware sees the page table updates. 119 */ 120 static int amdgpu_vm_cpu_commit(struct amdgpu_vm_update_params *p, 121 struct dma_fence **fence) 122 { 123 struct amdgpu_device *adev = p->adev; 124 125 if (p->needs_flush) 126 atomic64_inc(&p->vm->tlb_seq); 127 128 mb(); 129 /* A reset flushed the HDP anyway, so that here can be skipped when a reset is ongoing */ 130 if (!down_read_trylock(&adev->reset_domain->sem)) 131 return 0; 132 133 amdgpu_device_flush_hdp(adev, NULL); 134 up_read(&adev->reset_domain->sem); 135 136 return 0; 137 } 138 139 const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs = { 140 .map_table = amdgpu_vm_cpu_map_table, 141 .prepare = amdgpu_vm_cpu_prepare, 142 .update = amdgpu_vm_cpu_update, 143 .commit = amdgpu_vm_cpu_commit 144 }; 145