1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 #include <drm/ttm/ttm_bo.h> 33 #include <linux/sched/mm.h> 34 35 #include "amdgpu_sync.h" 36 #include "amdgpu_ring.h" 37 #include "amdgpu_ids.h" 38 39 struct drm_exec; 40 41 struct amdgpu_bo_va; 42 struct amdgpu_job; 43 struct amdgpu_bo_list_entry; 44 struct amdgpu_bo_vm; 45 struct amdgpu_mem_stats; 46 47 /* 48 * GPUVM handling 49 */ 50 51 /* Maximum number of PTEs the hardware can write with one command */ 52 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 53 54 /* number of entries in page table */ 55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 56 57 #define AMDGPU_PTE_VALID (1ULL << 0) 58 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 59 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 60 61 /* RV+ */ 62 #define AMDGPU_PTE_TMZ (1ULL << 3) 63 64 /* VI only */ 65 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 66 67 #define AMDGPU_PTE_READABLE (1ULL << 5) 68 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 69 70 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 71 72 /* TILED for VEGA10, reserved for older ASICs */ 73 #define AMDGPU_PTE_PRT (1ULL << 51) 74 75 /* PDE is handled as PTE for VEGA10 */ 76 #define AMDGPU_PDE_PTE (1ULL << 54) 77 78 #define AMDGPU_PTE_LOG (1ULL << 55) 79 80 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 81 #define AMDGPU_PTE_TF (1ULL << 56) 82 83 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */ 84 #define AMDGPU_PTE_NOALLOC (1ULL << 58) 85 86 /* PDE Block Fragment Size for VEGA10 */ 87 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 88 89 /* Flag combination to set no-retry with TF disabled */ 90 #define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \ 91 AMDGPU_PTE_TF) 92 93 /* Flag combination to set no-retry with TF enabled */ 94 #define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \ 95 AMDGPU_PTE_PRT) 96 /* For GFX9 */ 97 #define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57) 98 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL) 99 100 #define AMDGPU_MTYPE_NC 0 101 #define AMDGPU_MTYPE_CC 2 102 103 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 104 | AMDGPU_PTE_SNOOPED \ 105 | AMDGPU_PTE_EXECUTABLE \ 106 | AMDGPU_PTE_READABLE \ 107 | AMDGPU_PTE_WRITEABLE \ 108 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) 109 110 /* gfx10 */ 111 #define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48) 112 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL) 113 114 /* gfx12 */ 115 #define AMDGPU_PTE_PRT_GFX12 (1ULL << 56) 116 #define AMDGPU_PTE_PRT_FLAG(adev) \ 117 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT) 118 119 #define AMDGPU_PTE_MTYPE_GFX12(a) ((uint64_t)(a) << 54) 120 #define AMDGPU_PTE_MTYPE_GFX12_MASK AMDGPU_PTE_MTYPE_GFX12(3ULL) 121 122 #define AMDGPU_PTE_IS_PTE (1ULL << 63) 123 124 /* PDE Block Fragment Size for gfx v12 */ 125 #define AMDGPU_PDE_BFS_GFX12(a) ((uint64_t)((a) & 0x1fULL) << 58) 126 #define AMDGPU_PDE_BFS_FLAG(adev, a) \ 127 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGPU_PDE_BFS(a)) 128 /* PDE is handled as PTE for gfx v12 */ 129 #define AMDGPU_PDE_PTE_GFX12 (1ULL << 63) 130 #define AMDGPU_PDE_PTE_FLAG(adev) \ 131 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_PDE_PTE) 132 133 /* How to program VM fault handling */ 134 #define AMDGPU_VM_FAULT_STOP_NEVER 0 135 #define AMDGPU_VM_FAULT_STOP_FIRST 1 136 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 137 138 /* How much VRAM be reserved for page tables */ 139 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) 140 141 /* 142 * max number of VMHUB 143 * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1 144 */ 145 #define AMDGPU_MAX_VMHUBS 13 146 #define AMDGPU_GFXHUB_START 0 147 #define AMDGPU_MMHUB0_START 8 148 #define AMDGPU_MMHUB1_START 12 149 #define AMDGPU_GFXHUB(x) (AMDGPU_GFXHUB_START + (x)) 150 #define AMDGPU_MMHUB0(x) (AMDGPU_MMHUB0_START + (x)) 151 #define AMDGPU_MMHUB1(x) (AMDGPU_MMHUB1_START + (x)) 152 153 #define AMDGPU_IS_GFXHUB(x) ((x) >= AMDGPU_GFXHUB_START && (x) < AMDGPU_MMHUB0_START) 154 #define AMDGPU_IS_MMHUB0(x) ((x) >= AMDGPU_MMHUB0_START && (x) < AMDGPU_MMHUB1_START) 155 #define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS) 156 157 /* Reserve space at top/bottom of address space for kernel use */ 158 #define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20) 159 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \ 160 << AMDGPU_GPU_PAGE_SHIFT) \ 161 - AMDGPU_VA_RESERVED_CSA_SIZE) 162 #define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20) 163 #define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \ 164 - AMDGPU_VA_RESERVED_SEQ64_SIZE) 165 #define AMDGPU_VA_RESERVED_TRAP_SIZE (2ULL << 12) 166 #define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \ 167 - AMDGPU_VA_RESERVED_TRAP_SIZE) 168 #define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16) 169 #define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_TRAP_SIZE + \ 170 AMDGPU_VA_RESERVED_SEQ64_SIZE + \ 171 AMDGPU_VA_RESERVED_CSA_SIZE) 172 173 /* See vm_update_mode */ 174 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 175 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 176 177 /* VMPT level enumerate, and the hiberachy is: 178 * PDB2->PDB1->PDB0->PTB 179 */ 180 enum amdgpu_vm_level { 181 AMDGPU_VM_PDB2, 182 AMDGPU_VM_PDB1, 183 AMDGPU_VM_PDB0, 184 AMDGPU_VM_PTB 185 }; 186 187 /* base structure for tracking BO usage in a VM */ 188 struct amdgpu_vm_bo_base { 189 /* constant after initialization */ 190 struct amdgpu_vm *vm; 191 struct amdgpu_bo *bo; 192 193 /* protected by bo being reserved */ 194 struct amdgpu_vm_bo_base *next; 195 196 /* protected by spinlock */ 197 struct list_head vm_status; 198 199 /* protected by the BO being reserved */ 200 bool moved; 201 }; 202 203 /* provided by hw blocks that can write ptes, e.g., sdma */ 204 struct amdgpu_vm_pte_funcs { 205 /* number of dw to reserve per operation */ 206 unsigned copy_pte_num_dw; 207 208 /* copy pte entries from GART */ 209 void (*copy_pte)(struct amdgpu_ib *ib, 210 uint64_t pe, uint64_t src, 211 unsigned count); 212 213 /* write pte one entry at a time with addr mapping */ 214 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 215 uint64_t value, unsigned count, 216 uint32_t incr); 217 /* for linear pte/pde updates without addr mapping */ 218 void (*set_pte_pde)(struct amdgpu_ib *ib, 219 uint64_t pe, 220 uint64_t addr, unsigned count, 221 uint32_t incr, uint64_t flags); 222 }; 223 224 struct amdgpu_task_info { 225 char process_name[TASK_COMM_LEN]; 226 char task_name[TASK_COMM_LEN]; 227 pid_t pid; 228 pid_t tgid; 229 struct kref refcount; 230 }; 231 232 /** 233 * struct amdgpu_vm_update_params 234 * 235 * Encapsulate some VM table update parameters to reduce 236 * the number of function parameters 237 * 238 */ 239 struct amdgpu_vm_update_params { 240 241 /** 242 * @adev: amdgpu device we do this update for 243 */ 244 struct amdgpu_device *adev; 245 246 /** 247 * @vm: optional amdgpu_vm we do this update for 248 */ 249 struct amdgpu_vm *vm; 250 251 /** 252 * @immediate: if changes should be made immediately 253 */ 254 bool immediate; 255 256 /** 257 * @unlocked: true if the root BO is not locked 258 */ 259 bool unlocked; 260 261 /** 262 * @pages_addr: 263 * 264 * DMA addresses to use for mapping 265 */ 266 dma_addr_t *pages_addr; 267 268 /** 269 * @job: job to used for hw submission 270 */ 271 struct amdgpu_job *job; 272 273 /** 274 * @num_dw_left: number of dw left for the IB 275 */ 276 unsigned int num_dw_left; 277 278 /** 279 * @needs_flush: true whenever we need to invalidate the TLB 280 */ 281 bool needs_flush; 282 283 /** 284 * @allow_override: true for memory that is not uncached: allows MTYPE 285 * to be overridden for NUMA local memory. 286 */ 287 bool allow_override; 288 289 /** 290 * @tlb_flush_waitlist: temporary storage for BOs until tlb_flush 291 */ 292 struct list_head tlb_flush_waitlist; 293 }; 294 295 struct amdgpu_vm_update_funcs { 296 int (*map_table)(struct amdgpu_bo_vm *bo); 297 int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv, 298 enum amdgpu_sync_mode sync_mode); 299 int (*update)(struct amdgpu_vm_update_params *p, 300 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, 301 unsigned count, uint32_t incr, uint64_t flags); 302 int (*commit)(struct amdgpu_vm_update_params *p, 303 struct dma_fence **fence); 304 }; 305 306 struct amdgpu_vm_fault_info { 307 /* fault address */ 308 uint64_t addr; 309 /* fault status register */ 310 uint32_t status; 311 /* which vmhub? gfxhub, mmhub, etc. */ 312 unsigned int vmhub; 313 }; 314 315 struct amdgpu_vm { 316 /* tree of virtual addresses mapped */ 317 struct rb_root_cached va; 318 319 /* Lock to prevent eviction while we are updating page tables 320 * use vm_eviction_lock/unlock(vm) 321 */ 322 struct mutex eviction_lock; 323 bool evicting; 324 unsigned int saved_flags; 325 326 /* Lock to protect vm_bo add/del/move on all lists of vm */ 327 spinlock_t status_lock; 328 329 /* Per-VM and PT BOs who needs a validation */ 330 struct list_head evicted; 331 332 /* BOs for user mode queues that need a validation */ 333 struct list_head evicted_user; 334 335 /* PT BOs which relocated and their parent need an update */ 336 struct list_head relocated; 337 338 /* per VM BOs moved, but not yet updated in the PT */ 339 struct list_head moved; 340 341 /* All BOs of this VM not currently in the state machine */ 342 struct list_head idle; 343 344 /* regular invalidated BOs, but not yet updated in the PT */ 345 struct list_head invalidated; 346 347 /* BO mappings freed, but not yet updated in the PT */ 348 struct list_head freed; 349 350 /* BOs which are invalidated, has been updated in the PTs */ 351 struct list_head done; 352 353 /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */ 354 struct list_head pt_freed; 355 struct work_struct pt_free_work; 356 357 /* contains the page directory */ 358 struct amdgpu_vm_bo_base root; 359 struct dma_fence *last_update; 360 361 /* Scheduler entities for page table updates */ 362 struct drm_sched_entity immediate; 363 struct drm_sched_entity delayed; 364 365 /* Last finished delayed update */ 366 atomic64_t tlb_seq; 367 struct dma_fence *last_tlb_flush; 368 atomic64_t kfd_last_flushed_seq; 369 uint64_t tlb_fence_context; 370 371 /* How many times we had to re-generate the page tables */ 372 uint64_t generation; 373 374 /* Last unlocked submission to the scheduler entities */ 375 struct dma_fence *last_unlocked; 376 377 unsigned int pasid; 378 bool reserved_vmid[AMDGPU_MAX_VMHUBS]; 379 380 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 381 bool use_cpu_for_update; 382 383 /* Functions to use for VM table updates */ 384 const struct amdgpu_vm_update_funcs *update_funcs; 385 386 /* Up to 128 pending retry page faults */ 387 DECLARE_KFIFO(faults, u64, 128); 388 389 /* Points to the KFD process VM info */ 390 struct amdkfd_process_info *process_info; 391 392 /* List node in amdkfd_process_info.vm_list_head */ 393 struct list_head vm_list_node; 394 395 /* Valid while the PD is reserved or fenced */ 396 uint64_t pd_phys_addr; 397 398 /* Some basic info about the task */ 399 struct amdgpu_task_info *task_info; 400 401 /* Store positions of group of BOs */ 402 struct ttm_lru_bulk_move lru_bulk_move; 403 /* Flag to indicate if VM is used for compute */ 404 bool is_compute_context; 405 406 /* Memory partition number, -1 means any partition */ 407 int8_t mem_id; 408 409 /* cached fault info */ 410 struct amdgpu_vm_fault_info fault_info; 411 }; 412 413 struct amdgpu_vm_manager { 414 /* Handling of VMIDs */ 415 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 416 unsigned int first_kfd_vmid; 417 bool concurrent_flush; 418 419 /* Handling of VM fences */ 420 u64 fence_context; 421 unsigned seqno[AMDGPU_MAX_RINGS]; 422 423 uint64_t max_pfn; 424 uint32_t num_level; 425 uint32_t block_size; 426 uint32_t fragment_size; 427 enum amdgpu_vm_level root_level; 428 /* vram base address for page table entry */ 429 u64 vram_base_offset; 430 /* vm pte handling */ 431 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 432 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; 433 unsigned vm_pte_num_scheds; 434 struct amdgpu_ring *page_fault; 435 436 /* partial resident texture handling */ 437 spinlock_t prt_lock; 438 atomic_t num_prt_users; 439 440 /* controls how VM page tables are updated for Graphics and Compute. 441 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 442 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 443 */ 444 int vm_update_mode; 445 446 /* PASID to VM mapping, will be used in interrupt context to 447 * look up VM of a page fault 448 */ 449 struct xarray pasids; 450 /* Global registration of recent page fault information */ 451 struct amdgpu_vm_fault_info fault_info; 452 }; 453 454 struct amdgpu_bo_va_mapping; 455 456 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 457 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 458 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 459 460 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; 461 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; 462 463 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 464 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 465 466 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, 467 u32 pasid); 468 469 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 470 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id); 471 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 472 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 473 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 474 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, 475 unsigned int num_fences); 476 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 477 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm); 478 int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, 479 struct ww_acquire_ctx *ticket, 480 int (*callback)(void *p, struct amdgpu_bo *bo), 481 void *param); 482 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 483 int amdgpu_vm_update_pdes(struct amdgpu_device *adev, 484 struct amdgpu_vm *vm, bool immediate); 485 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 486 struct amdgpu_vm *vm, 487 struct dma_fence **fence); 488 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 489 struct amdgpu_vm *vm, 490 struct ww_acquire_ctx *ticket); 491 int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev, 492 struct amdgpu_vm *vm, 493 uint32_t flush_type, 494 uint32_t xcc_mask); 495 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, 496 struct amdgpu_vm *vm, struct amdgpu_bo *bo); 497 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, 498 bool immediate, bool unlocked, bool flush_tlb, bool allow_override, 499 struct dma_resv *resv, uint64_t start, uint64_t last, 500 uint64_t flags, uint64_t offset, uint64_t vram_base, 501 struct ttm_resource *res, dma_addr_t *pages_addr, 502 struct dma_fence **fence); 503 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 504 struct amdgpu_bo_va *bo_va, 505 bool clear); 506 bool amdgpu_vm_evictable(struct amdgpu_bo *bo); 507 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 508 struct amdgpu_bo *bo, bool evicted); 509 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 510 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 511 struct amdgpu_bo *bo); 512 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 513 struct amdgpu_vm *vm, 514 struct amdgpu_bo *bo); 515 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 516 struct amdgpu_bo_va *bo_va, 517 uint64_t addr, uint64_t offset, 518 uint64_t size, uint64_t flags); 519 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 520 struct amdgpu_bo_va *bo_va, 521 uint64_t addr, uint64_t offset, 522 uint64_t size, uint64_t flags); 523 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 524 struct amdgpu_bo_va *bo_va, 525 uint64_t addr); 526 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 527 struct amdgpu_vm *vm, 528 uint64_t saddr, uint64_t size); 529 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 530 uint64_t addr); 531 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 532 void amdgpu_vm_bo_del(struct amdgpu_device *adev, 533 struct amdgpu_bo_va *bo_va); 534 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 535 uint32_t fragment_size_default, unsigned max_level, 536 unsigned max_bits); 537 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 538 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 539 struct amdgpu_job *job); 540 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 541 542 struct amdgpu_task_info * 543 amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid); 544 545 struct amdgpu_task_info * 546 amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm); 547 548 void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info); 549 550 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 551 u32 vmid, u32 node_id, uint64_t addr, 552 bool write_fault); 553 554 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 555 556 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 557 struct amdgpu_vm *vm); 558 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, 559 struct amdgpu_mem_stats *stats); 560 561 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, 562 struct amdgpu_bo_vm *vmbo, bool immediate); 563 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, 564 int level, bool immediate, struct amdgpu_bo_vm **vmbo, 565 int32_t xcp_id); 566 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm); 567 568 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params, 569 struct amdgpu_vm_bo_base *entry); 570 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, 571 uint64_t start, uint64_t end, 572 uint64_t dst, uint64_t flags); 573 void amdgpu_vm_pt_free_work(struct work_struct *work); 574 void amdgpu_vm_pt_free_list(struct amdgpu_device *adev, 575 struct amdgpu_vm_update_params *params); 576 577 #if defined(CONFIG_DEBUG_FS) 578 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); 579 #endif 580 581 int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm); 582 583 /** 584 * amdgpu_vm_tlb_seq - return tlb flush sequence number 585 * @vm: the amdgpu_vm structure to query 586 * 587 * Returns the tlb flush sequence number which indicates that the VM TLBs needs 588 * to be invalidated whenever the sequence number change. 589 */ 590 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm) 591 { 592 unsigned long flags; 593 spinlock_t *lock; 594 595 /* 596 * Workaround to stop racing between the fence signaling and handling 597 * the cb. The lock is static after initially setting it up, just make 598 * sure that the dma_fence structure isn't freed up. 599 */ 600 rcu_read_lock(); 601 lock = vm->last_tlb_flush->lock; 602 rcu_read_unlock(); 603 604 spin_lock_irqsave(lock, flags); 605 spin_unlock_irqrestore(lock, flags); 606 607 return atomic64_read(&vm->tlb_seq); 608 } 609 610 /* 611 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS 612 * happens while holding this lock anywhere to prevent deadlocks when 613 * an MMU notifier runs in reclaim-FS context. 614 */ 615 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm) 616 { 617 mutex_lock(&vm->eviction_lock); 618 vm->saved_flags = memalloc_noreclaim_save(); 619 } 620 621 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) 622 { 623 if (mutex_trylock(&vm->eviction_lock)) { 624 vm->saved_flags = memalloc_noreclaim_save(); 625 return true; 626 } 627 return false; 628 } 629 630 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) 631 { 632 memalloc_noreclaim_restore(vm->saved_flags); 633 mutex_unlock(&vm->eviction_lock); 634 } 635 636 void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, 637 unsigned int pasid, 638 uint64_t addr, 639 uint32_t status, 640 unsigned int vmhub); 641 void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, 642 struct amdgpu_vm *vm, 643 struct dma_fence **fence); 644 645 #endif 646