1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 #include <drm/ttm/ttm_bo.h> 33 #include <linux/sched/mm.h> 34 35 #include "amdgpu_sync.h" 36 #include "amdgpu_ring.h" 37 #include "amdgpu_ids.h" 38 39 struct drm_exec; 40 41 struct amdgpu_bo_va; 42 struct amdgpu_job; 43 struct amdgpu_bo_list_entry; 44 struct amdgpu_bo_vm; 45 struct amdgpu_mem_stats; 46 47 /* 48 * GPUVM handling 49 */ 50 51 /* Maximum number of PTEs the hardware can write with one command */ 52 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 53 54 /* number of entries in page table */ 55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 56 57 #define AMDGPU_PTE_VALID (1ULL << 0) 58 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 59 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 60 61 /* RV+ */ 62 #define AMDGPU_PTE_TMZ (1ULL << 3) 63 64 /* VI only */ 65 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 66 67 #define AMDGPU_PTE_READABLE (1ULL << 5) 68 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 69 70 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 71 72 /* TILED for VEGA10, reserved for older ASICs */ 73 #define AMDGPU_PTE_PRT (1ULL << 51) 74 75 /* PDE is handled as PTE for VEGA10 */ 76 #define AMDGPU_PDE_PTE (1ULL << 54) 77 78 #define AMDGPU_PTE_LOG (1ULL << 55) 79 80 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 81 #define AMDGPU_PTE_TF (1ULL << 56) 82 83 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */ 84 #define AMDGPU_PTE_NOALLOC (1ULL << 58) 85 86 /* PDE Block Fragment Size for VEGA10 */ 87 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 88 89 /* Flag combination to set no-retry with TF disabled */ 90 #define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \ 91 AMDGPU_PTE_TF) 92 93 /* Flag combination to set no-retry with TF enabled */ 94 #define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \ 95 AMDGPU_PTE_PRT) 96 /* For GFX9 */ 97 #define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57) 98 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL) 99 100 #define AMDGPU_MTYPE_NC 0 101 #define AMDGPU_MTYPE_CC 2 102 103 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 104 | AMDGPU_PTE_SNOOPED \ 105 | AMDGPU_PTE_EXECUTABLE \ 106 | AMDGPU_PTE_READABLE \ 107 | AMDGPU_PTE_WRITEABLE \ 108 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) 109 110 /* gfx10 */ 111 #define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48) 112 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL) 113 114 /* How to program VM fault handling */ 115 #define AMDGPU_VM_FAULT_STOP_NEVER 0 116 #define AMDGPU_VM_FAULT_STOP_FIRST 1 117 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 118 119 /* How much VRAM be reserved for page tables */ 120 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) 121 122 /* 123 * max number of VMHUB 124 * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1 125 */ 126 #define AMDGPU_MAX_VMHUBS 13 127 #define AMDGPU_GFXHUB_START 0 128 #define AMDGPU_MMHUB0_START 8 129 #define AMDGPU_MMHUB1_START 12 130 #define AMDGPU_GFXHUB(x) (AMDGPU_GFXHUB_START + (x)) 131 #define AMDGPU_MMHUB0(x) (AMDGPU_MMHUB0_START + (x)) 132 #define AMDGPU_MMHUB1(x) (AMDGPU_MMHUB1_START + (x)) 133 134 #define AMDGPU_IS_GFXHUB(x) ((x) >= AMDGPU_GFXHUB_START && (x) < AMDGPU_MMHUB0_START) 135 #define AMDGPU_IS_MMHUB0(x) ((x) >= AMDGPU_MMHUB0_START && (x) < AMDGPU_MMHUB1_START) 136 #define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS) 137 138 /* Reserve space at top/bottom of address space for kernel use */ 139 #define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20) 140 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \ 141 << AMDGPU_GPU_PAGE_SHIFT) \ 142 - AMDGPU_VA_RESERVED_CSA_SIZE) 143 #define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20) 144 #define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \ 145 - AMDGPU_VA_RESERVED_SEQ64_SIZE) 146 #define AMDGPU_VA_RESERVED_TRAP_SIZE (2ULL << 12) 147 #define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \ 148 - AMDGPU_VA_RESERVED_TRAP_SIZE) 149 #define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16) 150 #define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_TRAP_SIZE + \ 151 AMDGPU_VA_RESERVED_SEQ64_SIZE + \ 152 AMDGPU_VA_RESERVED_CSA_SIZE) 153 154 /* See vm_update_mode */ 155 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 156 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 157 158 /* VMPT level enumerate, and the hiberachy is: 159 * PDB2->PDB1->PDB0->PTB 160 */ 161 enum amdgpu_vm_level { 162 AMDGPU_VM_PDB2, 163 AMDGPU_VM_PDB1, 164 AMDGPU_VM_PDB0, 165 AMDGPU_VM_PTB 166 }; 167 168 /* base structure for tracking BO usage in a VM */ 169 struct amdgpu_vm_bo_base { 170 /* constant after initialization */ 171 struct amdgpu_vm *vm; 172 struct amdgpu_bo *bo; 173 174 /* protected by bo being reserved */ 175 struct amdgpu_vm_bo_base *next; 176 177 /* protected by spinlock */ 178 struct list_head vm_status; 179 180 /* protected by the BO being reserved */ 181 bool moved; 182 }; 183 184 /* provided by hw blocks that can write ptes, e.g., sdma */ 185 struct amdgpu_vm_pte_funcs { 186 /* number of dw to reserve per operation */ 187 unsigned copy_pte_num_dw; 188 189 /* copy pte entries from GART */ 190 void (*copy_pte)(struct amdgpu_ib *ib, 191 uint64_t pe, uint64_t src, 192 unsigned count); 193 194 /* write pte one entry at a time with addr mapping */ 195 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 196 uint64_t value, unsigned count, 197 uint32_t incr); 198 /* for linear pte/pde updates without addr mapping */ 199 void (*set_pte_pde)(struct amdgpu_ib *ib, 200 uint64_t pe, 201 uint64_t addr, unsigned count, 202 uint32_t incr, uint64_t flags); 203 }; 204 205 struct amdgpu_task_info { 206 char process_name[TASK_COMM_LEN]; 207 char task_name[TASK_COMM_LEN]; 208 pid_t pid; 209 pid_t tgid; 210 }; 211 212 /** 213 * struct amdgpu_vm_update_params 214 * 215 * Encapsulate some VM table update parameters to reduce 216 * the number of function parameters 217 * 218 */ 219 struct amdgpu_vm_update_params { 220 221 /** 222 * @adev: amdgpu device we do this update for 223 */ 224 struct amdgpu_device *adev; 225 226 /** 227 * @vm: optional amdgpu_vm we do this update for 228 */ 229 struct amdgpu_vm *vm; 230 231 /** 232 * @immediate: if changes should be made immediately 233 */ 234 bool immediate; 235 236 /** 237 * @unlocked: true if the root BO is not locked 238 */ 239 bool unlocked; 240 241 /** 242 * @pages_addr: 243 * 244 * DMA addresses to use for mapping 245 */ 246 dma_addr_t *pages_addr; 247 248 /** 249 * @job: job to used for hw submission 250 */ 251 struct amdgpu_job *job; 252 253 /** 254 * @num_dw_left: number of dw left for the IB 255 */ 256 unsigned int num_dw_left; 257 258 /** 259 * @table_freed: return true if page table is freed when updating 260 */ 261 bool table_freed; 262 263 /** 264 * @allow_override: true for memory that is not uncached: allows MTYPE 265 * to be overridden for NUMA local memory. 266 */ 267 bool allow_override; 268 }; 269 270 struct amdgpu_vm_update_funcs { 271 int (*map_table)(struct amdgpu_bo_vm *bo); 272 int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv, 273 enum amdgpu_sync_mode sync_mode); 274 int (*update)(struct amdgpu_vm_update_params *p, 275 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, 276 unsigned count, uint32_t incr, uint64_t flags); 277 int (*commit)(struct amdgpu_vm_update_params *p, 278 struct dma_fence **fence); 279 }; 280 281 struct amdgpu_vm_fault_info { 282 /* fault address */ 283 uint64_t addr; 284 /* fault status register */ 285 uint32_t status; 286 /* which vmhub? gfxhub, mmhub, etc. */ 287 unsigned int vmhub; 288 }; 289 290 struct amdgpu_vm { 291 /* tree of virtual addresses mapped */ 292 struct rb_root_cached va; 293 294 /* Lock to prevent eviction while we are updating page tables 295 * use vm_eviction_lock/unlock(vm) 296 */ 297 struct mutex eviction_lock; 298 bool evicting; 299 unsigned int saved_flags; 300 301 /* Lock to protect vm_bo add/del/move on all lists of vm */ 302 spinlock_t status_lock; 303 304 /* Per-VM and PT BOs who needs a validation */ 305 struct list_head evicted; 306 307 /* BOs for user mode queues that need a validation */ 308 struct list_head evicted_user; 309 310 /* PT BOs which relocated and their parent need an update */ 311 struct list_head relocated; 312 313 /* per VM BOs moved, but not yet updated in the PT */ 314 struct list_head moved; 315 316 /* All BOs of this VM not currently in the state machine */ 317 struct list_head idle; 318 319 /* regular invalidated BOs, but not yet updated in the PT */ 320 struct list_head invalidated; 321 322 /* BO mappings freed, but not yet updated in the PT */ 323 struct list_head freed; 324 325 /* BOs which are invalidated, has been updated in the PTs */ 326 struct list_head done; 327 328 /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */ 329 struct list_head pt_freed; 330 struct work_struct pt_free_work; 331 332 /* contains the page directory */ 333 struct amdgpu_vm_bo_base root; 334 struct dma_fence *last_update; 335 336 /* Scheduler entities for page table updates */ 337 struct drm_sched_entity immediate; 338 struct drm_sched_entity delayed; 339 340 /* Last finished delayed update */ 341 atomic64_t tlb_seq; 342 struct dma_fence *last_tlb_flush; 343 atomic64_t kfd_last_flushed_seq; 344 345 /* How many times we had to re-generate the page tables */ 346 uint64_t generation; 347 348 /* Last unlocked submission to the scheduler entities */ 349 struct dma_fence *last_unlocked; 350 351 unsigned int pasid; 352 bool reserved_vmid[AMDGPU_MAX_VMHUBS]; 353 354 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 355 bool use_cpu_for_update; 356 357 /* Functions to use for VM table updates */ 358 const struct amdgpu_vm_update_funcs *update_funcs; 359 360 /* Flag to indicate ATS support from PTE for GFX9 */ 361 bool pte_support_ats; 362 363 /* Up to 128 pending retry page faults */ 364 DECLARE_KFIFO(faults, u64, 128); 365 366 /* Points to the KFD process VM info */ 367 struct amdkfd_process_info *process_info; 368 369 /* List node in amdkfd_process_info.vm_list_head */ 370 struct list_head vm_list_node; 371 372 /* Valid while the PD is reserved or fenced */ 373 uint64_t pd_phys_addr; 374 375 /* Some basic info about the task */ 376 struct amdgpu_task_info task_info; 377 378 /* Store positions of group of BOs */ 379 struct ttm_lru_bulk_move lru_bulk_move; 380 /* Flag to indicate if VM is used for compute */ 381 bool is_compute_context; 382 383 /* Memory partition number, -1 means any partition */ 384 int8_t mem_id; 385 386 /* cached fault info */ 387 struct amdgpu_vm_fault_info fault_info; 388 }; 389 390 struct amdgpu_vm_manager { 391 /* Handling of VMIDs */ 392 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 393 unsigned int first_kfd_vmid; 394 bool concurrent_flush; 395 396 /* Handling of VM fences */ 397 u64 fence_context; 398 unsigned seqno[AMDGPU_MAX_RINGS]; 399 400 uint64_t max_pfn; 401 uint32_t num_level; 402 uint32_t block_size; 403 uint32_t fragment_size; 404 enum amdgpu_vm_level root_level; 405 /* vram base address for page table entry */ 406 u64 vram_base_offset; 407 /* vm pte handling */ 408 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 409 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; 410 unsigned vm_pte_num_scheds; 411 struct amdgpu_ring *page_fault; 412 413 /* partial resident texture handling */ 414 spinlock_t prt_lock; 415 atomic_t num_prt_users; 416 417 /* controls how VM page tables are updated for Graphics and Compute. 418 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 419 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 420 */ 421 int vm_update_mode; 422 423 /* PASID to VM mapping, will be used in interrupt context to 424 * look up VM of a page fault 425 */ 426 struct xarray pasids; 427 }; 428 429 struct amdgpu_bo_va_mapping; 430 431 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 432 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 433 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 434 435 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; 436 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; 437 438 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 439 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 440 441 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, 442 u32 pasid); 443 444 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 445 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id); 446 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 447 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 448 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 449 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, 450 unsigned int num_fences); 451 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 452 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm); 453 int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, 454 struct ww_acquire_ctx *ticket, 455 int (*callback)(void *p, struct amdgpu_bo *bo), 456 void *param); 457 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 458 int amdgpu_vm_update_pdes(struct amdgpu_device *adev, 459 struct amdgpu_vm *vm, bool immediate); 460 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 461 struct amdgpu_vm *vm, 462 struct dma_fence **fence); 463 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 464 struct amdgpu_vm *vm, 465 struct ww_acquire_ctx *ticket); 466 int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev, 467 struct amdgpu_vm *vm, 468 uint32_t flush_type, 469 uint32_t xcc_mask); 470 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, 471 struct amdgpu_vm *vm, struct amdgpu_bo *bo); 472 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, 473 bool immediate, bool unlocked, bool flush_tlb, bool allow_override, 474 struct dma_resv *resv, uint64_t start, uint64_t last, 475 uint64_t flags, uint64_t offset, uint64_t vram_base, 476 struct ttm_resource *res, dma_addr_t *pages_addr, 477 struct dma_fence **fence); 478 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 479 struct amdgpu_bo_va *bo_va, 480 bool clear); 481 bool amdgpu_vm_evictable(struct amdgpu_bo *bo); 482 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 483 struct amdgpu_bo *bo, bool evicted); 484 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 485 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 486 struct amdgpu_bo *bo); 487 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 488 struct amdgpu_vm *vm, 489 struct amdgpu_bo *bo); 490 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 491 struct amdgpu_bo_va *bo_va, 492 uint64_t addr, uint64_t offset, 493 uint64_t size, uint64_t flags); 494 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 495 struct amdgpu_bo_va *bo_va, 496 uint64_t addr, uint64_t offset, 497 uint64_t size, uint64_t flags); 498 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 499 struct amdgpu_bo_va *bo_va, 500 uint64_t addr); 501 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 502 struct amdgpu_vm *vm, 503 uint64_t saddr, uint64_t size); 504 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 505 uint64_t addr); 506 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 507 void amdgpu_vm_bo_del(struct amdgpu_device *adev, 508 struct amdgpu_bo_va *bo_va); 509 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 510 uint32_t fragment_size_default, unsigned max_level, 511 unsigned max_bits); 512 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 513 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 514 struct amdgpu_job *job); 515 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 516 517 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid, 518 struct amdgpu_task_info *task_info); 519 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 520 u32 vmid, u32 node_id, uint64_t addr, 521 bool write_fault); 522 523 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 524 525 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 526 struct amdgpu_vm *vm); 527 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, 528 struct amdgpu_mem_stats *stats); 529 530 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, 531 struct amdgpu_bo_vm *vmbo, bool immediate); 532 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, 533 int level, bool immediate, struct amdgpu_bo_vm **vmbo, 534 int32_t xcp_id); 535 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm); 536 bool amdgpu_vm_pt_is_root_clean(struct amdgpu_device *adev, 537 struct amdgpu_vm *vm); 538 539 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params, 540 struct amdgpu_vm_bo_base *entry); 541 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, 542 uint64_t start, uint64_t end, 543 uint64_t dst, uint64_t flags); 544 void amdgpu_vm_pt_free_work(struct work_struct *work); 545 546 #if defined(CONFIG_DEBUG_FS) 547 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); 548 #endif 549 550 int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm); 551 552 /** 553 * amdgpu_vm_tlb_seq - return tlb flush sequence number 554 * @vm: the amdgpu_vm structure to query 555 * 556 * Returns the tlb flush sequence number which indicates that the VM TLBs needs 557 * to be invalidated whenever the sequence number change. 558 */ 559 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm) 560 { 561 unsigned long flags; 562 spinlock_t *lock; 563 564 /* 565 * Workaround to stop racing between the fence signaling and handling 566 * the cb. The lock is static after initially setting it up, just make 567 * sure that the dma_fence structure isn't freed up. 568 */ 569 rcu_read_lock(); 570 lock = vm->last_tlb_flush->lock; 571 rcu_read_unlock(); 572 573 spin_lock_irqsave(lock, flags); 574 spin_unlock_irqrestore(lock, flags); 575 576 return atomic64_read(&vm->tlb_seq); 577 } 578 579 /* 580 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS 581 * happens while holding this lock anywhere to prevent deadlocks when 582 * an MMU notifier runs in reclaim-FS context. 583 */ 584 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm) 585 { 586 mutex_lock(&vm->eviction_lock); 587 vm->saved_flags = memalloc_noreclaim_save(); 588 } 589 590 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) 591 { 592 if (mutex_trylock(&vm->eviction_lock)) { 593 vm->saved_flags = memalloc_noreclaim_save(); 594 return true; 595 } 596 return false; 597 } 598 599 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) 600 { 601 memalloc_noreclaim_restore(vm->saved_flags); 602 mutex_unlock(&vm->eviction_lock); 603 } 604 605 void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, 606 unsigned int pasid, 607 uint64_t addr, 608 uint32_t status, 609 unsigned int vmhub); 610 611 #endif 612