1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/rbtree.h> 28 #include <linux/idr.h> 29 30 #include "gpu_scheduler.h" 31 #include "amdgpu_sync.h" 32 #include "amdgpu_ring.h" 33 34 struct amdgpu_bo_va; 35 struct amdgpu_job; 36 struct amdgpu_bo_list_entry; 37 38 /* 39 * GPUVM handling 40 */ 41 42 /* maximum number of VMIDs */ 43 #define AMDGPU_NUM_VM 16 44 45 /* Maximum number of PTEs the hardware can write with one command */ 46 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 47 48 /* number of entries in page table */ 49 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 50 51 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 52 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 53 54 #define AMDGPU_PTE_VALID (1ULL << 0) 55 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 56 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 57 58 /* VI only */ 59 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 60 61 #define AMDGPU_PTE_READABLE (1ULL << 5) 62 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 63 64 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 65 66 /* TILED for VEGA10, reserved for older ASICs */ 67 #define AMDGPU_PTE_PRT (1ULL << 51) 68 69 /* PDE is handled as PTE for VEGA10 */ 70 #define AMDGPU_PDE_PTE (1ULL << 54) 71 72 /* VEGA10 only */ 73 #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57) 74 #define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL) 75 76 /* For Raven */ 77 #define AMDGPU_MTYPE_CC 2 78 79 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 80 | AMDGPU_PTE_SNOOPED \ 81 | AMDGPU_PTE_EXECUTABLE \ 82 | AMDGPU_PTE_READABLE \ 83 | AMDGPU_PTE_WRITEABLE \ 84 | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC)) 85 86 /* How to programm VM fault handling */ 87 #define AMDGPU_VM_FAULT_STOP_NEVER 0 88 #define AMDGPU_VM_FAULT_STOP_FIRST 1 89 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 90 91 /* max number of VMHUB */ 92 #define AMDGPU_MAX_VMHUBS 2 93 #define AMDGPU_GFXHUB 0 94 #define AMDGPU_MMHUB 1 95 96 /* hardcode that limit for now */ 97 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 98 /* max vmids dedicated for process */ 99 #define AMDGPU_VM_MAX_RESERVED_VMID 1 100 101 #define AMDGPU_VM_CONTEXT_GFX 0 102 #define AMDGPU_VM_CONTEXT_COMPUTE 1 103 104 /* See vm_update_mode */ 105 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 106 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 107 108 /* base structure for tracking BO usage in a VM */ 109 struct amdgpu_vm_bo_base { 110 /* constant after initialization */ 111 struct amdgpu_vm *vm; 112 struct amdgpu_bo *bo; 113 114 /* protected by bo being reserved */ 115 struct list_head bo_list; 116 117 /* protected by spinlock */ 118 struct list_head vm_status; 119 120 /* protected by the BO being reserved */ 121 bool moved; 122 }; 123 124 struct amdgpu_vm_pt { 125 struct amdgpu_vm_bo_base base; 126 uint64_t addr; 127 128 /* array of page tables, one for each directory entry */ 129 struct amdgpu_vm_pt *entries; 130 unsigned last_entry_used; 131 }; 132 133 #define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr)) 134 #define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48) 135 #define AMDGPU_VM_FAULT_ADDR(fault) ((u64)(fault) & 0xfffffffff000ULL) 136 137 struct amdgpu_vm { 138 /* tree of virtual addresses mapped */ 139 struct rb_root_cached va; 140 141 /* protecting invalidated */ 142 spinlock_t status_lock; 143 144 /* BOs who needs a validation */ 145 struct list_head evicted; 146 147 /* PT BOs which relocated and their parent need an update */ 148 struct list_head relocated; 149 150 /* BOs moved, but not yet updated in the PT */ 151 struct list_head moved; 152 153 /* BO mappings freed, but not yet updated in the PT */ 154 struct list_head freed; 155 156 /* contains the page directory */ 157 struct amdgpu_vm_pt root; 158 struct dma_fence *last_update; 159 160 /* protecting freed */ 161 spinlock_t freed_lock; 162 163 /* Scheduler entity for page table updates */ 164 struct amd_sched_entity entity; 165 166 /* client id and PASID (TODO: replace client_id with PASID) */ 167 u64 client_id; 168 unsigned int pasid; 169 /* dedicated to vm */ 170 struct amdgpu_vm_id *reserved_vmid[AMDGPU_MAX_VMHUBS]; 171 172 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 173 bool use_cpu_for_update; 174 175 /* Flag to indicate ATS support from PTE for GFX9 */ 176 bool pte_support_ats; 177 178 /* Up to 128 pending retry page faults */ 179 DECLARE_KFIFO(faults, u64, 128); 180 181 /* Limit non-retry fault storms */ 182 unsigned int fault_credit; 183 }; 184 185 struct amdgpu_vm_id { 186 struct list_head list; 187 struct amdgpu_sync active; 188 struct dma_fence *last_flush; 189 atomic64_t owner; 190 191 uint64_t pd_gpu_addr; 192 /* last flushed PD/PT update */ 193 struct dma_fence *flushed_updates; 194 195 uint32_t current_gpu_reset_count; 196 197 uint32_t gds_base; 198 uint32_t gds_size; 199 uint32_t gws_base; 200 uint32_t gws_size; 201 uint32_t oa_base; 202 uint32_t oa_size; 203 }; 204 205 struct amdgpu_vm_id_manager { 206 struct mutex lock; 207 unsigned num_ids; 208 struct list_head ids_lru; 209 struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; 210 atomic_t reserved_vmid_num; 211 }; 212 213 struct amdgpu_vm_manager { 214 /* Handling of VMIDs */ 215 struct amdgpu_vm_id_manager id_mgr[AMDGPU_MAX_VMHUBS]; 216 217 /* Handling of VM fences */ 218 u64 fence_context; 219 unsigned seqno[AMDGPU_MAX_RINGS]; 220 221 uint64_t max_pfn; 222 uint32_t num_level; 223 uint64_t vm_size; 224 uint32_t block_size; 225 uint32_t fragment_size; 226 /* vram base address for page table entry */ 227 u64 vram_base_offset; 228 /* vm pte handling */ 229 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 230 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; 231 unsigned vm_pte_num_rings; 232 atomic_t vm_pte_next_ring; 233 /* client id counter */ 234 atomic64_t client_counter; 235 236 /* partial resident texture handling */ 237 spinlock_t prt_lock; 238 atomic_t num_prt_users; 239 240 /* controls how VM page tables are updated for Graphics and Compute. 241 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 242 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 243 */ 244 int vm_update_mode; 245 246 /* PASID to VM mapping, will be used in interrupt context to 247 * look up VM of a page fault 248 */ 249 struct idr pasid_idr; 250 spinlock_t pasid_lock; 251 }; 252 253 int amdgpu_vm_alloc_pasid(unsigned int bits); 254 void amdgpu_vm_free_pasid(unsigned int pasid); 255 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 256 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 257 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, 258 int vm_context, unsigned int pasid); 259 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 260 bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev, 261 unsigned int pasid); 262 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 263 struct list_head *validated, 264 struct amdgpu_bo_list_entry *entry); 265 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 266 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, 267 int (*callback)(void *p, struct amdgpu_bo *bo), 268 void *param); 269 int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, 270 struct amdgpu_vm *vm, 271 uint64_t saddr, uint64_t size); 272 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 273 struct amdgpu_sync *sync, struct dma_fence *fence, 274 struct amdgpu_job *job); 275 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 276 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub, 277 unsigned vmid); 278 void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev); 279 int amdgpu_vm_update_directories(struct amdgpu_device *adev, 280 struct amdgpu_vm *vm); 281 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 282 struct amdgpu_vm *vm, 283 struct dma_fence **fence); 284 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 285 struct amdgpu_vm *vm); 286 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 287 struct amdgpu_bo_va *bo_va, 288 bool clear); 289 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 290 struct amdgpu_bo *bo, bool evicted); 291 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 292 struct amdgpu_bo *bo); 293 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 294 struct amdgpu_vm *vm, 295 struct amdgpu_bo *bo); 296 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 297 struct amdgpu_bo_va *bo_va, 298 uint64_t addr, uint64_t offset, 299 uint64_t size, uint64_t flags); 300 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 301 struct amdgpu_bo_va *bo_va, 302 uint64_t addr, uint64_t offset, 303 uint64_t size, uint64_t flags); 304 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 305 struct amdgpu_bo_va *bo_va, 306 uint64_t addr); 307 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 308 struct amdgpu_vm *vm, 309 uint64_t saddr, uint64_t size); 310 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 311 uint64_t addr); 312 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 313 struct amdgpu_bo_va *bo_va); 314 void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, 315 uint32_t fragment_size_default); 316 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size, 317 uint32_t fragment_size_default); 318 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 319 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 320 struct amdgpu_job *job); 321 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 322 323 #endif 324