1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 #include <drm/ttm/ttm_bo.h> 33 #include <linux/sched/mm.h> 34 35 #include "amdgpu_sync.h" 36 #include "amdgpu_ring.h" 37 #include "amdgpu_ids.h" 38 39 struct drm_exec; 40 41 struct amdgpu_bo_va; 42 struct amdgpu_job; 43 struct amdgpu_bo_list_entry; 44 struct amdgpu_bo_vm; 45 struct amdgpu_mem_stats; 46 47 /* 48 * GPUVM handling 49 */ 50 51 /* Maximum number of PTEs the hardware can write with one command */ 52 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 53 54 /* number of entries in page table */ 55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 56 57 #define AMDGPU_PTE_VALID (1ULL << 0) 58 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 59 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 60 61 /* RV+ */ 62 #define AMDGPU_PTE_TMZ (1ULL << 3) 63 64 /* VI only */ 65 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 66 67 #define AMDGPU_PTE_READABLE (1ULL << 5) 68 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 69 70 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 71 72 /* TILED for VEGA10, reserved for older ASICs */ 73 #define AMDGPU_PTE_PRT (1ULL << 51) 74 75 /* PDE is handled as PTE for VEGA10 */ 76 #define AMDGPU_PDE_PTE (1ULL << 54) 77 78 #define AMDGPU_PTE_LOG (1ULL << 55) 79 80 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 81 #define AMDGPU_PTE_TF (1ULL << 56) 82 83 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */ 84 #define AMDGPU_PTE_NOALLOC (1ULL << 58) 85 86 /* PDE Block Fragment Size for VEGA10 */ 87 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 88 89 /* Flag combination to set no-retry with TF disabled */ 90 #define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \ 91 AMDGPU_PTE_TF) 92 93 /* Flag combination to set no-retry with TF enabled */ 94 #define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \ 95 AMDGPU_PTE_PRT) 96 /* For GFX9 */ 97 #define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57) 98 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL) 99 100 #define AMDGPU_MTYPE_NC 0 101 #define AMDGPU_MTYPE_CC 2 102 103 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 104 | AMDGPU_PTE_SNOOPED \ 105 | AMDGPU_PTE_EXECUTABLE \ 106 | AMDGPU_PTE_READABLE \ 107 | AMDGPU_PTE_WRITEABLE \ 108 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) 109 110 /* gfx10 */ 111 #define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48) 112 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL) 113 114 /* How to program VM fault handling */ 115 #define AMDGPU_VM_FAULT_STOP_NEVER 0 116 #define AMDGPU_VM_FAULT_STOP_FIRST 1 117 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 118 119 /* How much VRAM be reserved for page tables */ 120 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) 121 122 /* 123 * max number of VMHUB 124 * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1 125 */ 126 #define AMDGPU_MAX_VMHUBS 13 127 #define AMDGPU_GFXHUB_START 0 128 #define AMDGPU_MMHUB0_START 8 129 #define AMDGPU_MMHUB1_START 12 130 #define AMDGPU_GFXHUB(x) (AMDGPU_GFXHUB_START + (x)) 131 #define AMDGPU_MMHUB0(x) (AMDGPU_MMHUB0_START + (x)) 132 #define AMDGPU_MMHUB1(x) (AMDGPU_MMHUB1_START + (x)) 133 134 #define AMDGPU_IS_GFXHUB(x) ((x) >= AMDGPU_GFXHUB_START && (x) < AMDGPU_MMHUB0_START) 135 #define AMDGPU_IS_MMHUB0(x) ((x) >= AMDGPU_MMHUB0_START && (x) < AMDGPU_MMHUB1_START) 136 #define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS) 137 138 /* Reserve 2MB at top/bottom of address space for kernel use */ 139 #define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20) 140 #define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20) 141 #define AMDGPU_VA_RESERVED_BOTTOM (2ULL << 20) 142 #define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_SEQ64_SIZE + \ 143 AMDGPU_VA_RESERVED_CSA_SIZE) 144 145 /* See vm_update_mode */ 146 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 147 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 148 149 /* VMPT level enumerate, and the hiberachy is: 150 * PDB2->PDB1->PDB0->PTB 151 */ 152 enum amdgpu_vm_level { 153 AMDGPU_VM_PDB2, 154 AMDGPU_VM_PDB1, 155 AMDGPU_VM_PDB0, 156 AMDGPU_VM_PTB 157 }; 158 159 /* base structure for tracking BO usage in a VM */ 160 struct amdgpu_vm_bo_base { 161 /* constant after initialization */ 162 struct amdgpu_vm *vm; 163 struct amdgpu_bo *bo; 164 165 /* protected by bo being reserved */ 166 struct amdgpu_vm_bo_base *next; 167 168 /* protected by spinlock */ 169 struct list_head vm_status; 170 171 /* protected by the BO being reserved */ 172 bool moved; 173 }; 174 175 /* provided by hw blocks that can write ptes, e.g., sdma */ 176 struct amdgpu_vm_pte_funcs { 177 /* number of dw to reserve per operation */ 178 unsigned copy_pte_num_dw; 179 180 /* copy pte entries from GART */ 181 void (*copy_pte)(struct amdgpu_ib *ib, 182 uint64_t pe, uint64_t src, 183 unsigned count); 184 185 /* write pte one entry at a time with addr mapping */ 186 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 187 uint64_t value, unsigned count, 188 uint32_t incr); 189 /* for linear pte/pde updates without addr mapping */ 190 void (*set_pte_pde)(struct amdgpu_ib *ib, 191 uint64_t pe, 192 uint64_t addr, unsigned count, 193 uint32_t incr, uint64_t flags); 194 }; 195 196 struct amdgpu_task_info { 197 char process_name[TASK_COMM_LEN]; 198 char task_name[TASK_COMM_LEN]; 199 pid_t pid; 200 pid_t tgid; 201 }; 202 203 /** 204 * struct amdgpu_vm_update_params 205 * 206 * Encapsulate some VM table update parameters to reduce 207 * the number of function parameters 208 * 209 */ 210 struct amdgpu_vm_update_params { 211 212 /** 213 * @adev: amdgpu device we do this update for 214 */ 215 struct amdgpu_device *adev; 216 217 /** 218 * @vm: optional amdgpu_vm we do this update for 219 */ 220 struct amdgpu_vm *vm; 221 222 /** 223 * @immediate: if changes should be made immediately 224 */ 225 bool immediate; 226 227 /** 228 * @unlocked: true if the root BO is not locked 229 */ 230 bool unlocked; 231 232 /** 233 * @pages_addr: 234 * 235 * DMA addresses to use for mapping 236 */ 237 dma_addr_t *pages_addr; 238 239 /** 240 * @job: job to used for hw submission 241 */ 242 struct amdgpu_job *job; 243 244 /** 245 * @num_dw_left: number of dw left for the IB 246 */ 247 unsigned int num_dw_left; 248 249 /** 250 * @table_freed: return true if page table is freed when updating 251 */ 252 bool table_freed; 253 254 /** 255 * @allow_override: true for memory that is not uncached: allows MTYPE 256 * to be overridden for NUMA local memory. 257 */ 258 bool allow_override; 259 }; 260 261 struct amdgpu_vm_update_funcs { 262 int (*map_table)(struct amdgpu_bo_vm *bo); 263 int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv, 264 enum amdgpu_sync_mode sync_mode); 265 int (*update)(struct amdgpu_vm_update_params *p, 266 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, 267 unsigned count, uint32_t incr, uint64_t flags); 268 int (*commit)(struct amdgpu_vm_update_params *p, 269 struct dma_fence **fence); 270 }; 271 272 struct amdgpu_vm_fault_info { 273 /* fault address */ 274 uint64_t addr; 275 /* fault status register */ 276 uint32_t status; 277 /* which vmhub? gfxhub, mmhub, etc. */ 278 unsigned int vmhub; 279 }; 280 281 struct amdgpu_vm { 282 /* tree of virtual addresses mapped */ 283 struct rb_root_cached va; 284 285 /* Lock to prevent eviction while we are updating page tables 286 * use vm_eviction_lock/unlock(vm) 287 */ 288 struct mutex eviction_lock; 289 bool evicting; 290 unsigned int saved_flags; 291 292 /* Lock to protect vm_bo add/del/move on all lists of vm */ 293 spinlock_t status_lock; 294 295 /* Per-VM and PT BOs who needs a validation */ 296 struct list_head evicted; 297 298 /* BOs for user mode queues that need a validation */ 299 struct list_head evicted_user; 300 301 /* PT BOs which relocated and their parent need an update */ 302 struct list_head relocated; 303 304 /* per VM BOs moved, but not yet updated in the PT */ 305 struct list_head moved; 306 307 /* All BOs of this VM not currently in the state machine */ 308 struct list_head idle; 309 310 /* regular invalidated BOs, but not yet updated in the PT */ 311 struct list_head invalidated; 312 313 /* BO mappings freed, but not yet updated in the PT */ 314 struct list_head freed; 315 316 /* BOs which are invalidated, has been updated in the PTs */ 317 struct list_head done; 318 319 /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */ 320 struct list_head pt_freed; 321 struct work_struct pt_free_work; 322 323 /* contains the page directory */ 324 struct amdgpu_vm_bo_base root; 325 struct dma_fence *last_update; 326 327 /* Scheduler entities for page table updates */ 328 struct drm_sched_entity immediate; 329 struct drm_sched_entity delayed; 330 331 /* Last finished delayed update */ 332 atomic64_t tlb_seq; 333 struct dma_fence *last_tlb_flush; 334 atomic64_t kfd_last_flushed_seq; 335 336 /* How many times we had to re-generate the page tables */ 337 uint64_t generation; 338 339 /* Last unlocked submission to the scheduler entities */ 340 struct dma_fence *last_unlocked; 341 342 unsigned int pasid; 343 bool reserved_vmid[AMDGPU_MAX_VMHUBS]; 344 345 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 346 bool use_cpu_for_update; 347 348 /* Functions to use for VM table updates */ 349 const struct amdgpu_vm_update_funcs *update_funcs; 350 351 /* Flag to indicate ATS support from PTE for GFX9 */ 352 bool pte_support_ats; 353 354 /* Up to 128 pending retry page faults */ 355 DECLARE_KFIFO(faults, u64, 128); 356 357 /* Points to the KFD process VM info */ 358 struct amdkfd_process_info *process_info; 359 360 /* List node in amdkfd_process_info.vm_list_head */ 361 struct list_head vm_list_node; 362 363 /* Valid while the PD is reserved or fenced */ 364 uint64_t pd_phys_addr; 365 366 /* Some basic info about the task */ 367 struct amdgpu_task_info task_info; 368 369 /* Store positions of group of BOs */ 370 struct ttm_lru_bulk_move lru_bulk_move; 371 /* Flag to indicate if VM is used for compute */ 372 bool is_compute_context; 373 374 /* Memory partition number, -1 means any partition */ 375 int8_t mem_id; 376 377 /* cached fault info */ 378 struct amdgpu_vm_fault_info fault_info; 379 }; 380 381 struct amdgpu_vm_manager { 382 /* Handling of VMIDs */ 383 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 384 unsigned int first_kfd_vmid; 385 bool concurrent_flush; 386 387 /* Handling of VM fences */ 388 u64 fence_context; 389 unsigned seqno[AMDGPU_MAX_RINGS]; 390 391 uint64_t max_pfn; 392 uint32_t num_level; 393 uint32_t block_size; 394 uint32_t fragment_size; 395 enum amdgpu_vm_level root_level; 396 /* vram base address for page table entry */ 397 u64 vram_base_offset; 398 /* vm pte handling */ 399 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 400 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; 401 unsigned vm_pte_num_scheds; 402 struct amdgpu_ring *page_fault; 403 404 /* partial resident texture handling */ 405 spinlock_t prt_lock; 406 atomic_t num_prt_users; 407 408 /* controls how VM page tables are updated for Graphics and Compute. 409 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 410 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 411 */ 412 int vm_update_mode; 413 414 /* PASID to VM mapping, will be used in interrupt context to 415 * look up VM of a page fault 416 */ 417 struct xarray pasids; 418 }; 419 420 struct amdgpu_bo_va_mapping; 421 422 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 423 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 424 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 425 426 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; 427 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; 428 429 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 430 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 431 432 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, 433 u32 pasid); 434 435 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 436 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id); 437 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 438 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 439 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 440 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, 441 unsigned int num_fences); 442 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 443 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm); 444 int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, 445 struct ww_acquire_ctx *ticket, 446 int (*callback)(void *p, struct amdgpu_bo *bo), 447 void *param); 448 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 449 int amdgpu_vm_update_pdes(struct amdgpu_device *adev, 450 struct amdgpu_vm *vm, bool immediate); 451 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 452 struct amdgpu_vm *vm, 453 struct dma_fence **fence); 454 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 455 struct amdgpu_vm *vm, 456 struct ww_acquire_ctx *ticket); 457 int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev, 458 struct amdgpu_vm *vm, 459 uint32_t flush_type, 460 uint32_t xcc_mask); 461 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, 462 struct amdgpu_vm *vm, struct amdgpu_bo *bo); 463 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, 464 bool immediate, bool unlocked, bool flush_tlb, bool allow_override, 465 struct dma_resv *resv, uint64_t start, uint64_t last, 466 uint64_t flags, uint64_t offset, uint64_t vram_base, 467 struct ttm_resource *res, dma_addr_t *pages_addr, 468 struct dma_fence **fence); 469 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 470 struct amdgpu_bo_va *bo_va, 471 bool clear); 472 bool amdgpu_vm_evictable(struct amdgpu_bo *bo); 473 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 474 struct amdgpu_bo *bo, bool evicted); 475 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 476 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 477 struct amdgpu_bo *bo); 478 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 479 struct amdgpu_vm *vm, 480 struct amdgpu_bo *bo); 481 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 482 struct amdgpu_bo_va *bo_va, 483 uint64_t addr, uint64_t offset, 484 uint64_t size, uint64_t flags); 485 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 486 struct amdgpu_bo_va *bo_va, 487 uint64_t addr, uint64_t offset, 488 uint64_t size, uint64_t flags); 489 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 490 struct amdgpu_bo_va *bo_va, 491 uint64_t addr); 492 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 493 struct amdgpu_vm *vm, 494 uint64_t saddr, uint64_t size); 495 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 496 uint64_t addr); 497 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 498 void amdgpu_vm_bo_del(struct amdgpu_device *adev, 499 struct amdgpu_bo_va *bo_va); 500 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 501 uint32_t fragment_size_default, unsigned max_level, 502 unsigned max_bits); 503 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 504 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 505 struct amdgpu_job *job); 506 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 507 508 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid, 509 struct amdgpu_task_info *task_info); 510 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 511 u32 vmid, u32 node_id, uint64_t addr, 512 bool write_fault); 513 514 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 515 516 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 517 struct amdgpu_vm *vm); 518 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, 519 struct amdgpu_mem_stats *stats); 520 521 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, 522 struct amdgpu_bo_vm *vmbo, bool immediate); 523 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, 524 int level, bool immediate, struct amdgpu_bo_vm **vmbo, 525 int32_t xcp_id); 526 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm); 527 bool amdgpu_vm_pt_is_root_clean(struct amdgpu_device *adev, 528 struct amdgpu_vm *vm); 529 530 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params, 531 struct amdgpu_vm_bo_base *entry); 532 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, 533 uint64_t start, uint64_t end, 534 uint64_t dst, uint64_t flags); 535 void amdgpu_vm_pt_free_work(struct work_struct *work); 536 537 #if defined(CONFIG_DEBUG_FS) 538 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); 539 #endif 540 541 int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm); 542 543 /** 544 * amdgpu_vm_tlb_seq - return tlb flush sequence number 545 * @vm: the amdgpu_vm structure to query 546 * 547 * Returns the tlb flush sequence number which indicates that the VM TLBs needs 548 * to be invalidated whenever the sequence number change. 549 */ 550 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm) 551 { 552 unsigned long flags; 553 spinlock_t *lock; 554 555 /* 556 * Workaround to stop racing between the fence signaling and handling 557 * the cb. The lock is static after initially setting it up, just make 558 * sure that the dma_fence structure isn't freed up. 559 */ 560 rcu_read_lock(); 561 lock = vm->last_tlb_flush->lock; 562 rcu_read_unlock(); 563 564 spin_lock_irqsave(lock, flags); 565 spin_unlock_irqrestore(lock, flags); 566 567 return atomic64_read(&vm->tlb_seq); 568 } 569 570 /* 571 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS 572 * happens while holding this lock anywhere to prevent deadlocks when 573 * an MMU notifier runs in reclaim-FS context. 574 */ 575 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm) 576 { 577 mutex_lock(&vm->eviction_lock); 578 vm->saved_flags = memalloc_noreclaim_save(); 579 } 580 581 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) 582 { 583 if (mutex_trylock(&vm->eviction_lock)) { 584 vm->saved_flags = memalloc_noreclaim_save(); 585 return true; 586 } 587 return false; 588 } 589 590 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) 591 { 592 memalloc_noreclaim_restore(vm->saved_flags); 593 mutex_unlock(&vm->eviction_lock); 594 } 595 596 void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, 597 unsigned int pasid, 598 uint64_t addr, 599 uint32_t status, 600 unsigned int vmhub); 601 602 #endif 603