1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 #include <drm/ttm/ttm_bo.h> 33 #include <linux/sched/mm.h> 34 35 #include "amdgpu_sync.h" 36 #include "amdgpu_ring.h" 37 #include "amdgpu_ids.h" 38 39 struct drm_exec; 40 41 struct amdgpu_bo_va; 42 struct amdgpu_job; 43 struct amdgpu_bo_list_entry; 44 struct amdgpu_bo_vm; 45 struct amdgpu_mem_stats; 46 47 /* 48 * GPUVM handling 49 */ 50 51 /* Maximum number of PTEs the hardware can write with one command */ 52 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 53 54 /* number of entries in page table */ 55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 56 57 #define AMDGPU_PTE_VALID (1ULL << 0) 58 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 59 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 60 61 /* RV+ */ 62 #define AMDGPU_PTE_TMZ (1ULL << 3) 63 64 /* VI only */ 65 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 66 67 #define AMDGPU_PTE_READABLE (1ULL << 5) 68 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 69 70 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 71 72 /* TILED for VEGA10, reserved for older ASICs */ 73 #define AMDGPU_PTE_PRT (1ULL << 51) 74 75 /* PDE is handled as PTE for VEGA10 */ 76 #define AMDGPU_PDE_PTE (1ULL << 54) 77 78 #define AMDGPU_PTE_LOG (1ULL << 55) 79 80 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 81 #define AMDGPU_PTE_TF (1ULL << 56) 82 83 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */ 84 #define AMDGPU_PTE_NOALLOC (1ULL << 58) 85 86 /* PDE Block Fragment Size for VEGA10 */ 87 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 88 89 /* Flag combination to set no-retry with TF disabled */ 90 #define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \ 91 AMDGPU_PTE_TF) 92 93 /* Flag combination to set no-retry with TF enabled */ 94 #define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \ 95 AMDGPU_PTE_PRT) 96 /* For GFX9 */ 97 #define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57) 98 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL) 99 100 #define AMDGPU_MTYPE_NC 0 101 #define AMDGPU_MTYPE_CC 2 102 103 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 104 | AMDGPU_PTE_SNOOPED \ 105 | AMDGPU_PTE_EXECUTABLE \ 106 | AMDGPU_PTE_READABLE \ 107 | AMDGPU_PTE_WRITEABLE \ 108 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) 109 110 /* gfx10 */ 111 #define AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype) ((uint64_t)(mtype) << 48) 112 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10_SHIFT(7ULL) 113 #define AMDGPU_PTE_MTYPE_NV10(flags, mtype) \ 114 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_NV10_MASK)) | \ 115 AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype)) 116 117 /* gfx12 */ 118 #define AMDGPU_PTE_PRT_GFX12 (1ULL << 56) 119 #define AMDGPU_PTE_PRT_FLAG(adev) \ 120 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT) 121 122 #define AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype) ((uint64_t)(mtype) << 54) 123 #define AMDGPU_PTE_MTYPE_GFX12_MASK AMDGPU_PTE_MTYPE_GFX12_SHIFT(3ULL) 124 #define AMDGPU_PTE_MTYPE_GFX12(flags, mtype) \ 125 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_GFX12_MASK)) | \ 126 AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype)) 127 128 #define AMDGPU_PTE_IS_PTE (1ULL << 63) 129 130 /* PDE Block Fragment Size for gfx v12 */ 131 #define AMDGPU_PDE_BFS_GFX12(a) ((uint64_t)((a) & 0x1fULL) << 58) 132 #define AMDGPU_PDE_BFS_FLAG(adev, a) \ 133 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGPU_PDE_BFS(a)) 134 /* PDE is handled as PTE for gfx v12 */ 135 #define AMDGPU_PDE_PTE_GFX12 (1ULL << 63) 136 #define AMDGPU_PDE_PTE_FLAG(adev) \ 137 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_PDE_PTE) 138 139 /* How to program VM fault handling */ 140 #define AMDGPU_VM_FAULT_STOP_NEVER 0 141 #define AMDGPU_VM_FAULT_STOP_FIRST 1 142 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 143 144 /* How much VRAM be reserved for page tables */ 145 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) 146 147 /* 148 * max number of VMHUB 149 * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1 150 */ 151 #define AMDGPU_MAX_VMHUBS 13 152 #define AMDGPU_GFXHUB_START 0 153 #define AMDGPU_MMHUB0_START 8 154 #define AMDGPU_MMHUB1_START 12 155 #define AMDGPU_GFXHUB(x) (AMDGPU_GFXHUB_START + (x)) 156 #define AMDGPU_MMHUB0(x) (AMDGPU_MMHUB0_START + (x)) 157 #define AMDGPU_MMHUB1(x) (AMDGPU_MMHUB1_START + (x)) 158 159 #define AMDGPU_IS_GFXHUB(x) ((x) >= AMDGPU_GFXHUB_START && (x) < AMDGPU_MMHUB0_START) 160 #define AMDGPU_IS_MMHUB0(x) ((x) >= AMDGPU_MMHUB0_START && (x) < AMDGPU_MMHUB1_START) 161 #define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS) 162 163 /* Reserve space at top/bottom of address space for kernel use */ 164 #define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20) 165 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \ 166 << AMDGPU_GPU_PAGE_SHIFT) \ 167 - AMDGPU_VA_RESERVED_CSA_SIZE) 168 #define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20) 169 #define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \ 170 - AMDGPU_VA_RESERVED_SEQ64_SIZE) 171 #define AMDGPU_VA_RESERVED_TRAP_SIZE (2ULL << 12) 172 #define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \ 173 - AMDGPU_VA_RESERVED_TRAP_SIZE) 174 #define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16) 175 #define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_TRAP_SIZE + \ 176 AMDGPU_VA_RESERVED_SEQ64_SIZE + \ 177 AMDGPU_VA_RESERVED_CSA_SIZE) 178 179 /* See vm_update_mode */ 180 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 181 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 182 183 /* VMPT level enumerate, and the hiberachy is: 184 * PDB2->PDB1->PDB0->PTB 185 */ 186 enum amdgpu_vm_level { 187 AMDGPU_VM_PDB2, 188 AMDGPU_VM_PDB1, 189 AMDGPU_VM_PDB0, 190 AMDGPU_VM_PTB 191 }; 192 193 /* base structure for tracking BO usage in a VM */ 194 struct amdgpu_vm_bo_base { 195 /* constant after initialization */ 196 struct amdgpu_vm *vm; 197 struct amdgpu_bo *bo; 198 199 /* protected by bo being reserved */ 200 struct amdgpu_vm_bo_base *next; 201 202 /* protected by spinlock */ 203 struct list_head vm_status; 204 205 /* protected by the BO being reserved */ 206 bool moved; 207 }; 208 209 /* provided by hw blocks that can write ptes, e.g., sdma */ 210 struct amdgpu_vm_pte_funcs { 211 /* number of dw to reserve per operation */ 212 unsigned copy_pte_num_dw; 213 214 /* copy pte entries from GART */ 215 void (*copy_pte)(struct amdgpu_ib *ib, 216 uint64_t pe, uint64_t src, 217 unsigned count); 218 219 /* write pte one entry at a time with addr mapping */ 220 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 221 uint64_t value, unsigned count, 222 uint32_t incr); 223 /* for linear pte/pde updates without addr mapping */ 224 void (*set_pte_pde)(struct amdgpu_ib *ib, 225 uint64_t pe, 226 uint64_t addr, unsigned count, 227 uint32_t incr, uint64_t flags); 228 }; 229 230 struct amdgpu_task_info { 231 char process_name[TASK_COMM_LEN]; 232 char task_name[TASK_COMM_LEN]; 233 pid_t pid; 234 pid_t tgid; 235 struct kref refcount; 236 }; 237 238 /** 239 * struct amdgpu_vm_update_params 240 * 241 * Encapsulate some VM table update parameters to reduce 242 * the number of function parameters 243 * 244 */ 245 struct amdgpu_vm_update_params { 246 247 /** 248 * @adev: amdgpu device we do this update for 249 */ 250 struct amdgpu_device *adev; 251 252 /** 253 * @vm: optional amdgpu_vm we do this update for 254 */ 255 struct amdgpu_vm *vm; 256 257 /** 258 * @immediate: if changes should be made immediately 259 */ 260 bool immediate; 261 262 /** 263 * @unlocked: true if the root BO is not locked 264 */ 265 bool unlocked; 266 267 /** 268 * @pages_addr: 269 * 270 * DMA addresses to use for mapping 271 */ 272 dma_addr_t *pages_addr; 273 274 /** 275 * @job: job to used for hw submission 276 */ 277 struct amdgpu_job *job; 278 279 /** 280 * @num_dw_left: number of dw left for the IB 281 */ 282 unsigned int num_dw_left; 283 284 /** 285 * @needs_flush: true whenever we need to invalidate the TLB 286 */ 287 bool needs_flush; 288 289 /** 290 * @allow_override: true for memory that is not uncached: allows MTYPE 291 * to be overridden for NUMA local memory. 292 */ 293 bool allow_override; 294 295 /** 296 * @tlb_flush_waitlist: temporary storage for BOs until tlb_flush 297 */ 298 struct list_head tlb_flush_waitlist; 299 }; 300 301 struct amdgpu_vm_update_funcs { 302 int (*map_table)(struct amdgpu_bo_vm *bo); 303 int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv, 304 enum amdgpu_sync_mode sync_mode); 305 int (*update)(struct amdgpu_vm_update_params *p, 306 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, 307 unsigned count, uint32_t incr, uint64_t flags); 308 int (*commit)(struct amdgpu_vm_update_params *p, 309 struct dma_fence **fence); 310 }; 311 312 struct amdgpu_vm_fault_info { 313 /* fault address */ 314 uint64_t addr; 315 /* fault status register */ 316 uint32_t status; 317 /* which vmhub? gfxhub, mmhub, etc. */ 318 unsigned int vmhub; 319 }; 320 321 struct amdgpu_vm { 322 /* tree of virtual addresses mapped */ 323 struct rb_root_cached va; 324 325 /* Lock to prevent eviction while we are updating page tables 326 * use vm_eviction_lock/unlock(vm) 327 */ 328 struct mutex eviction_lock; 329 bool evicting; 330 unsigned int saved_flags; 331 332 /* Lock to protect vm_bo add/del/move on all lists of vm */ 333 spinlock_t status_lock; 334 335 /* Per-VM and PT BOs who needs a validation */ 336 struct list_head evicted; 337 338 /* BOs for user mode queues that need a validation */ 339 struct list_head evicted_user; 340 341 /* PT BOs which relocated and their parent need an update */ 342 struct list_head relocated; 343 344 /* per VM BOs moved, but not yet updated in the PT */ 345 struct list_head moved; 346 347 /* All BOs of this VM not currently in the state machine */ 348 struct list_head idle; 349 350 /* regular invalidated BOs, but not yet updated in the PT */ 351 struct list_head invalidated; 352 353 /* BO mappings freed, but not yet updated in the PT */ 354 struct list_head freed; 355 356 /* BOs which are invalidated, has been updated in the PTs */ 357 struct list_head done; 358 359 /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */ 360 struct list_head pt_freed; 361 struct work_struct pt_free_work; 362 363 /* contains the page directory */ 364 struct amdgpu_vm_bo_base root; 365 struct dma_fence *last_update; 366 367 /* Scheduler entities for page table updates */ 368 struct drm_sched_entity immediate; 369 struct drm_sched_entity delayed; 370 371 /* Last finished delayed update */ 372 atomic64_t tlb_seq; 373 struct dma_fence *last_tlb_flush; 374 atomic64_t kfd_last_flushed_seq; 375 uint64_t tlb_fence_context; 376 377 /* How many times we had to re-generate the page tables */ 378 uint64_t generation; 379 380 /* Last unlocked submission to the scheduler entities */ 381 struct dma_fence *last_unlocked; 382 383 unsigned int pasid; 384 bool reserved_vmid[AMDGPU_MAX_VMHUBS]; 385 386 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 387 bool use_cpu_for_update; 388 389 /* Functions to use for VM table updates */ 390 const struct amdgpu_vm_update_funcs *update_funcs; 391 392 /* Up to 128 pending retry page faults */ 393 DECLARE_KFIFO(faults, u64, 128); 394 395 /* Points to the KFD process VM info */ 396 struct amdkfd_process_info *process_info; 397 398 /* List node in amdkfd_process_info.vm_list_head */ 399 struct list_head vm_list_node; 400 401 /* Valid while the PD is reserved or fenced */ 402 uint64_t pd_phys_addr; 403 404 /* Some basic info about the task */ 405 struct amdgpu_task_info *task_info; 406 407 /* Store positions of group of BOs */ 408 struct ttm_lru_bulk_move lru_bulk_move; 409 /* Flag to indicate if VM is used for compute */ 410 bool is_compute_context; 411 412 /* Memory partition number, -1 means any partition */ 413 int8_t mem_id; 414 415 /* cached fault info */ 416 struct amdgpu_vm_fault_info fault_info; 417 }; 418 419 struct amdgpu_vm_manager { 420 /* Handling of VMIDs */ 421 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 422 unsigned int first_kfd_vmid; 423 bool concurrent_flush; 424 425 /* Handling of VM fences */ 426 u64 fence_context; 427 unsigned seqno[AMDGPU_MAX_RINGS]; 428 429 uint64_t max_pfn; 430 uint32_t num_level; 431 uint32_t block_size; 432 uint32_t fragment_size; 433 enum amdgpu_vm_level root_level; 434 /* vram base address for page table entry */ 435 u64 vram_base_offset; 436 /* vm pte handling */ 437 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 438 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; 439 unsigned vm_pte_num_scheds; 440 struct amdgpu_ring *page_fault; 441 442 /* partial resident texture handling */ 443 spinlock_t prt_lock; 444 atomic_t num_prt_users; 445 446 /* controls how VM page tables are updated for Graphics and Compute. 447 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 448 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 449 */ 450 int vm_update_mode; 451 452 /* PASID to VM mapping, will be used in interrupt context to 453 * look up VM of a page fault 454 */ 455 struct xarray pasids; 456 /* Global registration of recent page fault information */ 457 struct amdgpu_vm_fault_info fault_info; 458 }; 459 460 struct amdgpu_bo_va_mapping; 461 462 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 463 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 464 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 465 466 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; 467 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; 468 469 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 470 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 471 472 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, 473 u32 pasid); 474 475 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 476 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id); 477 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 478 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 479 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 480 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, 481 unsigned int num_fences); 482 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 483 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm); 484 int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, 485 struct ww_acquire_ctx *ticket, 486 int (*callback)(void *p, struct amdgpu_bo *bo), 487 void *param); 488 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 489 int amdgpu_vm_update_pdes(struct amdgpu_device *adev, 490 struct amdgpu_vm *vm, bool immediate); 491 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 492 struct amdgpu_vm *vm, 493 struct dma_fence **fence); 494 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 495 struct amdgpu_vm *vm, 496 struct ww_acquire_ctx *ticket); 497 int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev, 498 struct amdgpu_vm *vm, 499 uint32_t flush_type, 500 uint32_t xcc_mask); 501 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, 502 struct amdgpu_vm *vm, struct amdgpu_bo *bo); 503 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, 504 bool immediate, bool unlocked, bool flush_tlb, bool allow_override, 505 struct dma_resv *resv, uint64_t start, uint64_t last, 506 uint64_t flags, uint64_t offset, uint64_t vram_base, 507 struct ttm_resource *res, dma_addr_t *pages_addr, 508 struct dma_fence **fence); 509 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 510 struct amdgpu_bo_va *bo_va, 511 bool clear); 512 bool amdgpu_vm_evictable(struct amdgpu_bo *bo); 513 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 514 struct amdgpu_bo *bo, bool evicted); 515 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 516 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 517 struct amdgpu_bo *bo); 518 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 519 struct amdgpu_vm *vm, 520 struct amdgpu_bo *bo); 521 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 522 struct amdgpu_bo_va *bo_va, 523 uint64_t addr, uint64_t offset, 524 uint64_t size, uint64_t flags); 525 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 526 struct amdgpu_bo_va *bo_va, 527 uint64_t addr, uint64_t offset, 528 uint64_t size, uint64_t flags); 529 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 530 struct amdgpu_bo_va *bo_va, 531 uint64_t addr); 532 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 533 struct amdgpu_vm *vm, 534 uint64_t saddr, uint64_t size); 535 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 536 uint64_t addr); 537 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 538 void amdgpu_vm_bo_del(struct amdgpu_device *adev, 539 struct amdgpu_bo_va *bo_va); 540 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 541 uint32_t fragment_size_default, unsigned max_level, 542 unsigned max_bits); 543 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 544 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 545 struct amdgpu_job *job); 546 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 547 548 struct amdgpu_task_info * 549 amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid); 550 551 struct amdgpu_task_info * 552 amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm); 553 554 void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info); 555 556 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 557 u32 vmid, u32 node_id, uint64_t addr, 558 bool write_fault); 559 560 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 561 562 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 563 struct amdgpu_vm *vm); 564 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, 565 struct amdgpu_mem_stats *stats); 566 567 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, 568 struct amdgpu_bo_vm *vmbo, bool immediate); 569 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, 570 int level, bool immediate, struct amdgpu_bo_vm **vmbo, 571 int32_t xcp_id); 572 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm); 573 574 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params, 575 struct amdgpu_vm_bo_base *entry); 576 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, 577 uint64_t start, uint64_t end, 578 uint64_t dst, uint64_t flags); 579 void amdgpu_vm_pt_free_work(struct work_struct *work); 580 void amdgpu_vm_pt_free_list(struct amdgpu_device *adev, 581 struct amdgpu_vm_update_params *params); 582 583 #if defined(CONFIG_DEBUG_FS) 584 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); 585 #endif 586 587 int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm); 588 589 bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo); 590 591 /** 592 * amdgpu_vm_tlb_seq - return tlb flush sequence number 593 * @vm: the amdgpu_vm structure to query 594 * 595 * Returns the tlb flush sequence number which indicates that the VM TLBs needs 596 * to be invalidated whenever the sequence number change. 597 */ 598 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm) 599 { 600 unsigned long flags; 601 spinlock_t *lock; 602 603 /* 604 * Workaround to stop racing between the fence signaling and handling 605 * the cb. The lock is static after initially setting it up, just make 606 * sure that the dma_fence structure isn't freed up. 607 */ 608 rcu_read_lock(); 609 lock = vm->last_tlb_flush->lock; 610 rcu_read_unlock(); 611 612 spin_lock_irqsave(lock, flags); 613 spin_unlock_irqrestore(lock, flags); 614 615 return atomic64_read(&vm->tlb_seq); 616 } 617 618 /* 619 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS 620 * happens while holding this lock anywhere to prevent deadlocks when 621 * an MMU notifier runs in reclaim-FS context. 622 */ 623 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm) 624 { 625 mutex_lock(&vm->eviction_lock); 626 vm->saved_flags = memalloc_noreclaim_save(); 627 } 628 629 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) 630 { 631 if (mutex_trylock(&vm->eviction_lock)) { 632 vm->saved_flags = memalloc_noreclaim_save(); 633 return true; 634 } 635 return false; 636 } 637 638 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) 639 { 640 memalloc_noreclaim_restore(vm->saved_flags); 641 mutex_unlock(&vm->eviction_lock); 642 } 643 644 void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, 645 unsigned int pasid, 646 uint64_t addr, 647 uint32_t status, 648 unsigned int vmhub); 649 void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, 650 struct amdgpu_vm *vm, 651 struct dma_fence **fence); 652 653 #endif 654