1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 #include <drm/ttm/ttm_bo.h> 33 #include <linux/sched/mm.h> 34 35 #include "amdgpu_sync.h" 36 #include "amdgpu_ring.h" 37 #include "amdgpu_ids.h" 38 #include "amdgpu_ttm.h" 39 40 struct drm_exec; 41 42 struct amdgpu_bo_va; 43 struct amdgpu_job; 44 struct amdgpu_bo_list_entry; 45 struct amdgpu_bo_vm; 46 47 /* 48 * GPUVM handling 49 */ 50 51 /* Maximum number of PTEs the hardware can write with one command */ 52 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 53 54 /* number of entries in page table */ 55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 56 57 #define AMDGPU_PTE_VALID (1ULL << 0) 58 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 59 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 60 61 /* RV+ */ 62 #define AMDGPU_PTE_TMZ (1ULL << 3) 63 64 /* VI only */ 65 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 66 67 #define AMDGPU_PTE_READABLE (1ULL << 5) 68 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 69 70 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 71 72 /* TILED for VEGA10, reserved for older ASICs */ 73 #define AMDGPU_PTE_PRT (1ULL << 51) 74 75 /* PDE is handled as PTE for VEGA10 */ 76 #define AMDGPU_PDE_PTE (1ULL << 54) 77 78 #define AMDGPU_PTE_LOG (1ULL << 55) 79 80 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 81 #define AMDGPU_PTE_TF (1ULL << 56) 82 83 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */ 84 #define AMDGPU_PTE_NOALLOC (1ULL << 58) 85 86 /* PDE Block Fragment Size for VEGA10 */ 87 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 88 89 /* Flag combination to set no-retry with TF disabled */ 90 #define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \ 91 AMDGPU_PTE_TF) 92 93 /* Flag combination to set no-retry with TF enabled */ 94 #define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \ 95 AMDGPU_PTE_PRT) 96 /* For GFX9 */ 97 #define AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype) ((uint64_t)(mtype) << 57) 98 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10_SHIFT(3ULL) 99 #define AMDGPU_PTE_MTYPE_VG10(flags, mtype) \ 100 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_VG10_MASK)) | \ 101 AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype)) 102 103 #define AMDGPU_MTYPE_NC 0 104 #define AMDGPU_MTYPE_CC 2 105 106 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 107 | AMDGPU_PTE_SNOOPED \ 108 | AMDGPU_PTE_EXECUTABLE \ 109 | AMDGPU_PTE_READABLE \ 110 | AMDGPU_PTE_WRITEABLE \ 111 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) 112 113 /* gfx10 */ 114 #define AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype) ((uint64_t)(mtype) << 48) 115 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10_SHIFT(7ULL) 116 #define AMDGPU_PTE_MTYPE_NV10(flags, mtype) \ 117 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_NV10_MASK)) | \ 118 AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype)) 119 120 /* gfx12 */ 121 #define AMDGPU_PTE_PRT_GFX12 (1ULL << 56) 122 #define AMDGPU_PTE_PRT_FLAG(adev) \ 123 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT) 124 125 #define AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype) ((uint64_t)(mtype) << 54) 126 #define AMDGPU_PTE_MTYPE_GFX12_MASK AMDGPU_PTE_MTYPE_GFX12_SHIFT(3ULL) 127 #define AMDGPU_PTE_MTYPE_GFX12(flags, mtype) \ 128 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_GFX12_MASK)) | \ 129 AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype)) 130 131 #define AMDGPU_PTE_DCC (1ULL << 58) 132 #define AMDGPU_PTE_BUS_ATOMICS (1ULL << 59) 133 #define AMDGPU_PTE_IS_PTE (1ULL << 63) 134 135 /* PDE Block Fragment Size for gfx v12 */ 136 #define AMDGPU_PDE_BFS_GFX12(a) ((uint64_t)((a) & 0x1fULL) << 58) 137 #define AMDGPU_PDE_BFS_FLAG(adev, a) \ 138 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGPU_PDE_BFS(a)) 139 /* PDE is handled as PTE for gfx v12 */ 140 #define AMDGPU_PDE_PTE_GFX12 (1ULL << 63) 141 #define AMDGPU_PDE_PTE_FLAG(adev) \ 142 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_PDE_PTE) 143 144 /* How to program VM fault handling */ 145 #define AMDGPU_VM_FAULT_STOP_NEVER 0 146 #define AMDGPU_VM_FAULT_STOP_FIRST 1 147 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 148 149 /* How much VRAM be reserved for page tables */ 150 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) 151 152 /* 153 * max number of VMHUB 154 * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1 155 */ 156 #define AMDGPU_MAX_VMHUBS 13 157 #define AMDGPU_GFXHUB_START 0 158 #define AMDGPU_MMHUB0_START 8 159 #define AMDGPU_MMHUB1_START 12 160 #define AMDGPU_GFXHUB(x) (AMDGPU_GFXHUB_START + (x)) 161 #define AMDGPU_MMHUB0(x) (AMDGPU_MMHUB0_START + (x)) 162 #define AMDGPU_MMHUB1(x) (AMDGPU_MMHUB1_START + (x)) 163 164 #define AMDGPU_IS_GFXHUB(x) ((x) >= AMDGPU_GFXHUB_START && (x) < AMDGPU_MMHUB0_START) 165 #define AMDGPU_IS_MMHUB0(x) ((x) >= AMDGPU_MMHUB0_START && (x) < AMDGPU_MMHUB1_START) 166 #define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS) 167 168 /* Reserve space at top/bottom of address space for kernel use */ 169 #define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20) 170 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \ 171 << AMDGPU_GPU_PAGE_SHIFT) \ 172 - AMDGPU_VA_RESERVED_CSA_SIZE) 173 #define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20) 174 #define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \ 175 - AMDGPU_VA_RESERVED_SEQ64_SIZE) 176 #define AMDGPU_VA_RESERVED_TRAP_SIZE (1ULL << 16) 177 #define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \ 178 - AMDGPU_VA_RESERVED_TRAP_SIZE) 179 #define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16) 180 #define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_TRAP_SIZE + \ 181 AMDGPU_VA_RESERVED_SEQ64_SIZE + \ 182 AMDGPU_VA_RESERVED_CSA_SIZE) 183 184 /* See vm_update_mode */ 185 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 186 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 187 188 /* VMPT level enumerate, and the hiberachy is: 189 * PDB3->PDB2->PDB1->PDB0->PTB 190 */ 191 enum amdgpu_vm_level { 192 AMDGPU_VM_PDB3, 193 AMDGPU_VM_PDB2, 194 AMDGPU_VM_PDB1, 195 AMDGPU_VM_PDB0, 196 AMDGPU_VM_PTB 197 }; 198 199 /* base structure for tracking BO usage in a VM */ 200 struct amdgpu_vm_bo_base { 201 /* constant after initialization */ 202 struct amdgpu_vm *vm; 203 struct amdgpu_bo *bo; 204 205 /* protected by bo being reserved */ 206 struct amdgpu_vm_bo_base *next; 207 208 /* protected by vm reservation and invalidated_lock */ 209 struct list_head vm_status; 210 211 /* if the bo is counted as shared in mem stats 212 * protected by vm BO being reserved */ 213 bool shared; 214 215 /* if the BO was moved and all mappings are invalid 216 * protected by the BO being reserved */ 217 bool moved; 218 }; 219 220 /* 221 * The following status lists contain amdgpu_vm_bo_base objects for 222 * either PD/PTs, per VM BOs or BOs with individual resv object. 223 * 224 * The state transits are: evicted -> needs_update -> idle 225 */ 226 struct amdgpu_vm_bo_status { 227 /* BOs evicted which need to move into place again */ 228 struct list_head evicted; 229 230 /* BOs whose mappings changed but PDs/PTs haven't been updated */ 231 struct list_head needs_update; 232 233 /* BOs done with the state machine and need no further action */ 234 struct list_head idle; 235 }; 236 237 /* provided by hw blocks that can write ptes, e.g., sdma */ 238 struct amdgpu_vm_pte_funcs { 239 /* number of dw to reserve per operation */ 240 unsigned copy_pte_num_dw; 241 242 /* copy pte entries from GART */ 243 void (*copy_pte)(struct amdgpu_ib *ib, 244 uint64_t pe, uint64_t src, 245 unsigned count); 246 247 /* write pte one entry at a time with addr mapping */ 248 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 249 uint64_t value, unsigned count, 250 uint32_t incr); 251 /* for linear pte/pde updates without addr mapping */ 252 void (*set_pte_pde)(struct amdgpu_ib *ib, 253 uint64_t pe, 254 uint64_t addr, unsigned count, 255 uint32_t incr, uint64_t flags); 256 }; 257 258 struct amdgpu_task_info { 259 struct drm_wedge_task_info task; 260 char process_name[TASK_COMM_LEN]; 261 pid_t tgid; 262 struct kref refcount; 263 }; 264 265 /** 266 * struct amdgpu_vm_update_params 267 * 268 * Encapsulate some VM table update parameters to reduce 269 * the number of function parameters 270 * 271 */ 272 struct amdgpu_vm_update_params { 273 274 /** 275 * @adev: amdgpu device we do this update for 276 */ 277 struct amdgpu_device *adev; 278 279 /** 280 * @vm: optional amdgpu_vm we do this update for 281 */ 282 struct amdgpu_vm *vm; 283 284 /** 285 * @immediate: if changes should be made immediately 286 */ 287 bool immediate; 288 289 /** 290 * @unlocked: true if the root BO is not locked 291 */ 292 bool unlocked; 293 294 /** 295 * @pages_addr: 296 * 297 * DMA addresses to use for mapping 298 */ 299 dma_addr_t *pages_addr; 300 301 /** 302 * @job: job to used for hw submission 303 */ 304 struct amdgpu_job *job; 305 306 /** 307 * @num_dw_left: number of dw left for the IB 308 */ 309 unsigned int num_dw_left; 310 311 /** 312 * @needs_flush: true whenever we need to invalidate the TLB 313 */ 314 bool needs_flush; 315 316 /** 317 * @override_pte: true for memory that is not uncached and gmc override function is 318 * implemented to allow MTYPE to be overridden for NUMA local memory. 319 */ 320 bool override_pte; 321 322 /** 323 * @tlb_flush_waitlist: temporary storage for BOs until tlb_flush 324 */ 325 struct list_head tlb_flush_waitlist; 326 }; 327 328 struct amdgpu_vm_update_funcs { 329 int (*map_table)(struct amdgpu_bo_vm *bo); 330 int (*prepare)(struct amdgpu_vm_update_params *p, 331 struct amdgpu_sync *sync, u64 k_job_id); 332 int (*update)(struct amdgpu_vm_update_params *p, 333 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, 334 unsigned count, uint32_t incr, uint64_t flags); 335 int (*commit)(struct amdgpu_vm_update_params *p, 336 struct dma_fence **fence); 337 }; 338 339 struct amdgpu_vm_fault_info { 340 /* fault address */ 341 uint64_t addr; 342 /* fault status register */ 343 uint32_t status; 344 /* which vmhub? gfxhub, mmhub, etc. */ 345 unsigned int vmhub; 346 }; 347 348 struct amdgpu_mem_stats { 349 struct drm_memory_stats drm; 350 351 /* buffers that requested this placement but are currently evicted */ 352 uint64_t evicted; 353 }; 354 355 struct amdgpu_vm { 356 /* tree of virtual addresses mapped */ 357 struct rb_root_cached va; 358 359 /* Lock to prevent eviction while we are updating page tables 360 * use vm_eviction_lock/unlock(vm) 361 */ 362 struct mutex eviction_lock; 363 bool evicting; 364 unsigned int saved_flags; 365 366 /* Memory statistics for this vm, protected by stats_lock */ 367 spinlock_t stats_lock; 368 struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM]; 369 370 /* BO's belonging to PD/PT which are internal to the kernel. */ 371 struct amdgpu_vm_bo_status kernel; 372 373 /* 374 * BOs allocated by userspace where the dma_resv is shared with the 375 * root PD 376 */ 377 struct amdgpu_vm_bo_status always_valid; 378 379 /* 380 * The following lists contain amdgpu_vm_bo_base objects for BOs which 381 * have their own dma_resv object and not depend on the root PD. 382 * 383 * Lists are protected by the individual_lock. 384 */ 385 spinlock_t individual_lock; 386 387 /* Userspace BOs with individual resv object */ 388 struct amdgpu_vm_bo_status individual; 389 390 /* 391 * This list contains amdgpu_bo_va_mapping objects which have been freed 392 * but not updated in the PTs 393 */ 394 struct list_head freed; 395 396 /* contains the page directory */ 397 struct amdgpu_vm_bo_base root; 398 struct dma_fence *last_update; 399 400 /* Scheduler entities for page table updates */ 401 struct drm_sched_entity immediate; 402 struct drm_sched_entity delayed; 403 404 /* Last finished delayed update */ 405 atomic64_t tlb_seq; 406 struct dma_fence *last_tlb_flush; 407 atomic64_t kfd_last_flushed_seq; 408 uint64_t tlb_fence_context; 409 410 /* How many times we had to re-generate the page tables */ 411 uint64_t generation; 412 413 /* Last unlocked submission to the scheduler entities */ 414 struct dma_fence *last_unlocked; 415 416 unsigned int pasid; 417 struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS]; 418 419 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 420 bool use_cpu_for_update; 421 422 /* Functions to use for VM table updates */ 423 const struct amdgpu_vm_update_funcs *update_funcs; 424 425 /* Up to 128 pending retry page faults */ 426 DECLARE_KFIFO(faults, u64, 128); 427 428 /* Points to the KFD process VM info */ 429 struct amdkfd_process_info *process_info; 430 431 /* List node in amdkfd_process_info.vm_list_head */ 432 struct list_head vm_list_node; 433 434 /* Valid while the PD is reserved or fenced */ 435 uint64_t pd_phys_addr; 436 437 /* Some basic info about the task */ 438 struct amdgpu_task_info *task_info; 439 440 /* Store positions of group of BOs */ 441 struct ttm_lru_bulk_move lru_bulk_move; 442 /* Flag to indicate if VM is used for compute */ 443 bool is_compute_context; 444 /* Flag to indicate if VM needs a TLB fence (KFD or KGD) */ 445 bool need_tlb_fence; 446 447 /* Memory partition number, -1 means any partition */ 448 int8_t mem_id; 449 450 /* cached fault info */ 451 struct amdgpu_vm_fault_info fault_info; 452 }; 453 454 struct amdgpu_vm_manager { 455 /* Handling of VMIDs */ 456 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 457 unsigned int first_kfd_vmid; 458 bool concurrent_flush; 459 460 uint64_t max_pfn; 461 uint32_t max_level; 462 uint32_t num_level; 463 uint32_t block_size; 464 uint32_t fragment_size; 465 enum amdgpu_vm_level root_level; 466 /* vram base address for page table entry */ 467 u64 vram_base_offset; 468 /* vm pte handling */ 469 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 470 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; 471 unsigned vm_pte_num_scheds; 472 struct amdgpu_ring *page_fault; 473 474 /* partial resident texture handling */ 475 spinlock_t prt_lock; 476 atomic_t num_prt_users; 477 478 /* controls how VM page tables are updated for Graphics and Compute. 479 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 480 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 481 */ 482 int vm_update_mode; 483 484 /* PASID to VM mapping, will be used in interrupt context to 485 * look up VM of a page fault 486 */ 487 struct xarray pasids; 488 /* Global registration of recent page fault information */ 489 struct amdgpu_vm_fault_info fault_info; 490 }; 491 492 struct amdgpu_bo_va_mapping; 493 494 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 495 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 496 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 497 498 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; 499 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; 500 501 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 502 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 503 504 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 505 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id, uint32_t pasid); 506 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 507 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 508 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, 509 unsigned int num_fences); 510 int amdgpu_vm_lock_individual(struct amdgpu_vm *vm, struct drm_exec *exec, 511 unsigned int num_fences); 512 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 513 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm); 514 int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, 515 struct ww_acquire_ctx *ticket, 516 int (*callback)(void *p, struct amdgpu_bo *bo), 517 void *param); 518 void amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 519 int amdgpu_vm_update_pdes(struct amdgpu_device *adev, 520 struct amdgpu_vm *vm, bool immediate); 521 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 522 struct amdgpu_vm *vm, 523 struct dma_fence **fence); 524 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 525 struct amdgpu_vm *vm, 526 struct ww_acquire_ctx *ticket); 527 int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev, 528 struct amdgpu_vm *vm, 529 uint32_t flush_type, 530 uint32_t xcc_mask); 531 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, 532 struct amdgpu_vm *vm, struct amdgpu_bo *bo); 533 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, 534 bool immediate, bool unlocked, bool flush_tlb, 535 bool allow_override, struct amdgpu_sync *sync, 536 uint64_t start, uint64_t last, uint64_t flags, 537 uint64_t offset, uint64_t vram_base, 538 struct ttm_resource *res, dma_addr_t *pages_addr, 539 struct dma_fence **fence); 540 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 541 struct amdgpu_bo_va *bo_va, 542 bool clear); 543 bool amdgpu_vm_evictable(struct amdgpu_bo *bo); 544 void amdgpu_vm_bo_invalidate(struct amdgpu_bo *bo, bool evicted); 545 void amdgpu_vm_update_stats(struct amdgpu_vm_bo_base *base, 546 struct ttm_resource *new_res, int sign); 547 void amdgpu_vm_bo_update_shared(struct amdgpu_bo *bo); 548 void amdgpu_vm_bo_move(struct amdgpu_bo *bo, struct ttm_resource *new_mem, 549 bool evicted); 550 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 551 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 552 struct amdgpu_bo *bo); 553 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 554 struct amdgpu_vm *vm, 555 struct amdgpu_bo *bo); 556 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 557 struct amdgpu_bo_va *bo_va, 558 uint64_t addr, uint64_t offset, 559 uint64_t size, uint32_t flags); 560 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 561 struct amdgpu_bo_va *bo_va, 562 uint64_t addr, uint64_t offset, 563 uint64_t size, uint32_t flags); 564 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 565 struct amdgpu_bo_va *bo_va, 566 uint64_t addr); 567 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 568 struct amdgpu_vm *vm, 569 uint64_t saddr, uint64_t size); 570 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 571 uint64_t addr); 572 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 573 void amdgpu_vm_bo_del(struct amdgpu_device *adev, 574 struct amdgpu_bo_va *bo_va); 575 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 576 uint32_t fragment_size_default, unsigned max_level, 577 unsigned max_bits); 578 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 579 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 580 struct amdgpu_job *job); 581 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 582 583 struct amdgpu_task_info * 584 amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid); 585 586 struct amdgpu_task_info * 587 amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm); 588 589 void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info); 590 591 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 592 u32 vmid, u32 node_id, uint64_t addr, uint64_t ts, 593 bool write_fault); 594 595 struct amdgpu_vm *amdgpu_vm_lock_by_pasid(struct amdgpu_device *adev, 596 u32 pasid, struct drm_exec *exec); 597 598 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 599 600 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 601 struct amdgpu_vm *vm); 602 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, 603 struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM]); 604 605 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, 606 struct amdgpu_bo_vm *vmbo, bool immediate); 607 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, 608 int level, bool immediate, struct amdgpu_bo_vm **vmbo, 609 int32_t xcp_id); 610 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm); 611 612 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params, 613 struct amdgpu_vm_bo_base *entry); 614 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, 615 uint64_t start, uint64_t end, 616 uint64_t dst, uint64_t flags); 617 void amdgpu_vm_pt_free_work(struct work_struct *work); 618 void amdgpu_vm_pt_free_list(struct amdgpu_device *adev, 619 struct amdgpu_vm_update_params *params); 620 621 #if defined(CONFIG_DEBUG_FS) 622 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); 623 #endif 624 625 int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm); 626 627 bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo); 628 629 /** 630 * amdgpu_vm_tlb_seq - return tlb flush sequence number 631 * @vm: the amdgpu_vm structure to query 632 * 633 * Returns the tlb flush sequence number which indicates that the VM TLBs needs 634 * to be invalidated whenever the sequence number change. 635 */ 636 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm) 637 { 638 unsigned long flags; 639 spinlock_t *lock; 640 641 /* 642 * Workaround to stop racing between the fence signaling and handling 643 * the cb. The lock is static after initially setting it up, just make 644 * sure that the dma_fence structure isn't freed up. 645 */ 646 rcu_read_lock(); 647 lock = dma_fence_spinlock(vm->last_tlb_flush); 648 rcu_read_unlock(); 649 650 spin_lock_irqsave(lock, flags); 651 spin_unlock_irqrestore(lock, flags); 652 653 return atomic64_read(&vm->tlb_seq); 654 } 655 656 /* 657 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS 658 * happens while holding this lock anywhere to prevent deadlocks when 659 * an MMU notifier runs in reclaim-FS context. 660 */ 661 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm) 662 { 663 mutex_lock(&vm->eviction_lock); 664 vm->saved_flags = memalloc_noreclaim_save(); 665 } 666 667 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) 668 { 669 if (mutex_trylock(&vm->eviction_lock)) { 670 vm->saved_flags = memalloc_noreclaim_save(); 671 return true; 672 } 673 return false; 674 } 675 676 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) 677 { 678 memalloc_noreclaim_restore(vm->saved_flags); 679 mutex_unlock(&vm->eviction_lock); 680 } 681 682 void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, 683 unsigned int pasid, 684 uint64_t addr, 685 uint32_t status, 686 unsigned int vmhub); 687 void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, 688 struct amdgpu_vm *vm, 689 struct dma_fence **fence); 690 691 void amdgpu_vm_print_task_info(struct amdgpu_device *adev, 692 struct amdgpu_task_info *task_info); 693 694 #define amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) \ 695 list_for_each_entry(mapping, &(bo_va)->valids, list) 696 #define amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) \ 697 list_for_each_entry(mapping, &(bo_va)->invalids, list) 698 699 #endif 700