1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 #include <drm/ttm/ttm_bo.h> 33 #include <linux/sched/mm.h> 34 35 #include "amdgpu_sync.h" 36 #include "amdgpu_ring.h" 37 #include "amdgpu_ids.h" 38 39 struct drm_exec; 40 41 struct amdgpu_bo_va; 42 struct amdgpu_job; 43 struct amdgpu_bo_list_entry; 44 struct amdgpu_bo_vm; 45 struct amdgpu_mem_stats; 46 47 /* 48 * GPUVM handling 49 */ 50 51 /* Maximum number of PTEs the hardware can write with one command */ 52 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 53 54 /* number of entries in page table */ 55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 56 57 #define AMDGPU_PTE_VALID (1ULL << 0) 58 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 59 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 60 61 /* RV+ */ 62 #define AMDGPU_PTE_TMZ (1ULL << 3) 63 64 /* VI only */ 65 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 66 67 #define AMDGPU_PTE_READABLE (1ULL << 5) 68 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 69 70 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 71 72 /* TILED for VEGA10, reserved for older ASICs */ 73 #define AMDGPU_PTE_PRT (1ULL << 51) 74 75 /* PDE is handled as PTE for VEGA10 */ 76 #define AMDGPU_PDE_PTE (1ULL << 54) 77 78 #define AMDGPU_PTE_LOG (1ULL << 55) 79 80 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 81 #define AMDGPU_PTE_TF (1ULL << 56) 82 83 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */ 84 #define AMDGPU_PTE_NOALLOC (1ULL << 58) 85 86 /* PDE Block Fragment Size for VEGA10 */ 87 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 88 89 /* Flag combination to set no-retry with TF disabled */ 90 #define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \ 91 AMDGPU_PTE_TF) 92 93 /* Flag combination to set no-retry with TF enabled */ 94 #define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \ 95 AMDGPU_PTE_PRT) 96 /* For GFX9 */ 97 #define AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype) ((uint64_t)(mtype) << 57) 98 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10_SHIFT(3ULL) 99 #define AMDGPU_PTE_MTYPE_VG10(flags, mtype) \ 100 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_VG10_MASK)) | \ 101 AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype)) 102 103 #define AMDGPU_MTYPE_NC 0 104 #define AMDGPU_MTYPE_CC 2 105 106 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 107 | AMDGPU_PTE_SNOOPED \ 108 | AMDGPU_PTE_EXECUTABLE \ 109 | AMDGPU_PTE_READABLE \ 110 | AMDGPU_PTE_WRITEABLE \ 111 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) 112 113 /* gfx10 */ 114 #define AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype) ((uint64_t)(mtype) << 48) 115 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10_SHIFT(7ULL) 116 #define AMDGPU_PTE_MTYPE_NV10(flags, mtype) \ 117 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_NV10_MASK)) | \ 118 AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype)) 119 120 /* gfx12 */ 121 #define AMDGPU_PTE_PRT_GFX12 (1ULL << 56) 122 #define AMDGPU_PTE_PRT_FLAG(adev) \ 123 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT) 124 125 #define AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype) ((uint64_t)(mtype) << 54) 126 #define AMDGPU_PTE_MTYPE_GFX12_MASK AMDGPU_PTE_MTYPE_GFX12_SHIFT(3ULL) 127 #define AMDGPU_PTE_MTYPE_GFX12(flags, mtype) \ 128 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_GFX12_MASK)) | \ 129 AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype)) 130 131 #define AMDGPU_PTE_IS_PTE (1ULL << 63) 132 133 /* PDE Block Fragment Size for gfx v12 */ 134 #define AMDGPU_PDE_BFS_GFX12(a) ((uint64_t)((a) & 0x1fULL) << 58) 135 #define AMDGPU_PDE_BFS_FLAG(adev, a) \ 136 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGPU_PDE_BFS(a)) 137 /* PDE is handled as PTE for gfx v12 */ 138 #define AMDGPU_PDE_PTE_GFX12 (1ULL << 63) 139 #define AMDGPU_PDE_PTE_FLAG(adev) \ 140 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_PDE_PTE) 141 142 /* How to program VM fault handling */ 143 #define AMDGPU_VM_FAULT_STOP_NEVER 0 144 #define AMDGPU_VM_FAULT_STOP_FIRST 1 145 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 146 147 /* How much VRAM be reserved for page tables */ 148 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) 149 150 /* 151 * max number of VMHUB 152 * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1 153 */ 154 #define AMDGPU_MAX_VMHUBS 13 155 #define AMDGPU_GFXHUB_START 0 156 #define AMDGPU_MMHUB0_START 8 157 #define AMDGPU_MMHUB1_START 12 158 #define AMDGPU_GFXHUB(x) (AMDGPU_GFXHUB_START + (x)) 159 #define AMDGPU_MMHUB0(x) (AMDGPU_MMHUB0_START + (x)) 160 #define AMDGPU_MMHUB1(x) (AMDGPU_MMHUB1_START + (x)) 161 162 #define AMDGPU_IS_GFXHUB(x) ((x) >= AMDGPU_GFXHUB_START && (x) < AMDGPU_MMHUB0_START) 163 #define AMDGPU_IS_MMHUB0(x) ((x) >= AMDGPU_MMHUB0_START && (x) < AMDGPU_MMHUB1_START) 164 #define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS) 165 166 /* Reserve space at top/bottom of address space for kernel use */ 167 #define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20) 168 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \ 169 << AMDGPU_GPU_PAGE_SHIFT) \ 170 - AMDGPU_VA_RESERVED_CSA_SIZE) 171 #define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20) 172 #define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \ 173 - AMDGPU_VA_RESERVED_SEQ64_SIZE) 174 #define AMDGPU_VA_RESERVED_TRAP_SIZE (2ULL << 12) 175 #define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \ 176 - AMDGPU_VA_RESERVED_TRAP_SIZE) 177 #define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16) 178 #define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_TRAP_SIZE + \ 179 AMDGPU_VA_RESERVED_SEQ64_SIZE + \ 180 AMDGPU_VA_RESERVED_CSA_SIZE) 181 182 /* See vm_update_mode */ 183 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 184 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 185 186 /* VMPT level enumerate, and the hiberachy is: 187 * PDB2->PDB1->PDB0->PTB 188 */ 189 enum amdgpu_vm_level { 190 AMDGPU_VM_PDB2, 191 AMDGPU_VM_PDB1, 192 AMDGPU_VM_PDB0, 193 AMDGPU_VM_PTB 194 }; 195 196 /* base structure for tracking BO usage in a VM */ 197 struct amdgpu_vm_bo_base { 198 /* constant after initialization */ 199 struct amdgpu_vm *vm; 200 struct amdgpu_bo *bo; 201 202 /* protected by bo being reserved */ 203 struct amdgpu_vm_bo_base *next; 204 205 /* protected by spinlock */ 206 struct list_head vm_status; 207 208 /* protected by the BO being reserved */ 209 bool moved; 210 }; 211 212 /* provided by hw blocks that can write ptes, e.g., sdma */ 213 struct amdgpu_vm_pte_funcs { 214 /* number of dw to reserve per operation */ 215 unsigned copy_pte_num_dw; 216 217 /* copy pte entries from GART */ 218 void (*copy_pte)(struct amdgpu_ib *ib, 219 uint64_t pe, uint64_t src, 220 unsigned count); 221 222 /* write pte one entry at a time with addr mapping */ 223 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 224 uint64_t value, unsigned count, 225 uint32_t incr); 226 /* for linear pte/pde updates without addr mapping */ 227 void (*set_pte_pde)(struct amdgpu_ib *ib, 228 uint64_t pe, 229 uint64_t addr, unsigned count, 230 uint32_t incr, uint64_t flags); 231 }; 232 233 struct amdgpu_task_info { 234 char process_name[TASK_COMM_LEN]; 235 char task_name[TASK_COMM_LEN]; 236 pid_t pid; 237 pid_t tgid; 238 struct kref refcount; 239 }; 240 241 /** 242 * struct amdgpu_vm_update_params 243 * 244 * Encapsulate some VM table update parameters to reduce 245 * the number of function parameters 246 * 247 */ 248 struct amdgpu_vm_update_params { 249 250 /** 251 * @adev: amdgpu device we do this update for 252 */ 253 struct amdgpu_device *adev; 254 255 /** 256 * @vm: optional amdgpu_vm we do this update for 257 */ 258 struct amdgpu_vm *vm; 259 260 /** 261 * @immediate: if changes should be made immediately 262 */ 263 bool immediate; 264 265 /** 266 * @unlocked: true if the root BO is not locked 267 */ 268 bool unlocked; 269 270 /** 271 * @pages_addr: 272 * 273 * DMA addresses to use for mapping 274 */ 275 dma_addr_t *pages_addr; 276 277 /** 278 * @job: job to used for hw submission 279 */ 280 struct amdgpu_job *job; 281 282 /** 283 * @num_dw_left: number of dw left for the IB 284 */ 285 unsigned int num_dw_left; 286 287 /** 288 * @needs_flush: true whenever we need to invalidate the TLB 289 */ 290 bool needs_flush; 291 292 /** 293 * @allow_override: true for memory that is not uncached: allows MTYPE 294 * to be overridden for NUMA local memory. 295 */ 296 bool allow_override; 297 298 /** 299 * @tlb_flush_waitlist: temporary storage for BOs until tlb_flush 300 */ 301 struct list_head tlb_flush_waitlist; 302 }; 303 304 struct amdgpu_vm_update_funcs { 305 int (*map_table)(struct amdgpu_bo_vm *bo); 306 int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv, 307 enum amdgpu_sync_mode sync_mode); 308 int (*update)(struct amdgpu_vm_update_params *p, 309 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, 310 unsigned count, uint32_t incr, uint64_t flags); 311 int (*commit)(struct amdgpu_vm_update_params *p, 312 struct dma_fence **fence); 313 }; 314 315 struct amdgpu_vm_fault_info { 316 /* fault address */ 317 uint64_t addr; 318 /* fault status register */ 319 uint32_t status; 320 /* which vmhub? gfxhub, mmhub, etc. */ 321 unsigned int vmhub; 322 }; 323 324 struct amdgpu_vm { 325 /* tree of virtual addresses mapped */ 326 struct rb_root_cached va; 327 328 /* Lock to prevent eviction while we are updating page tables 329 * use vm_eviction_lock/unlock(vm) 330 */ 331 struct mutex eviction_lock; 332 bool evicting; 333 unsigned int saved_flags; 334 335 /* Lock to protect vm_bo add/del/move on all lists of vm */ 336 spinlock_t status_lock; 337 338 /* Per-VM and PT BOs who needs a validation */ 339 struct list_head evicted; 340 341 /* BOs for user mode queues that need a validation */ 342 struct list_head evicted_user; 343 344 /* PT BOs which relocated and their parent need an update */ 345 struct list_head relocated; 346 347 /* per VM BOs moved, but not yet updated in the PT */ 348 struct list_head moved; 349 350 /* All BOs of this VM not currently in the state machine */ 351 struct list_head idle; 352 353 /* regular invalidated BOs, but not yet updated in the PT */ 354 struct list_head invalidated; 355 356 /* BO mappings freed, but not yet updated in the PT */ 357 struct list_head freed; 358 359 /* BOs which are invalidated, has been updated in the PTs */ 360 struct list_head done; 361 362 /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */ 363 struct list_head pt_freed; 364 struct work_struct pt_free_work; 365 366 /* contains the page directory */ 367 struct amdgpu_vm_bo_base root; 368 struct dma_fence *last_update; 369 370 /* Scheduler entities for page table updates */ 371 struct drm_sched_entity immediate; 372 struct drm_sched_entity delayed; 373 374 /* Last finished delayed update */ 375 atomic64_t tlb_seq; 376 struct dma_fence *last_tlb_flush; 377 atomic64_t kfd_last_flushed_seq; 378 uint64_t tlb_fence_context; 379 380 /* How many times we had to re-generate the page tables */ 381 uint64_t generation; 382 383 /* Last unlocked submission to the scheduler entities */ 384 struct dma_fence *last_unlocked; 385 386 unsigned int pasid; 387 bool reserved_vmid[AMDGPU_MAX_VMHUBS]; 388 389 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 390 bool use_cpu_for_update; 391 392 /* Functions to use for VM table updates */ 393 const struct amdgpu_vm_update_funcs *update_funcs; 394 395 /* Up to 128 pending retry page faults */ 396 DECLARE_KFIFO(faults, u64, 128); 397 398 /* Points to the KFD process VM info */ 399 struct amdkfd_process_info *process_info; 400 401 /* List node in amdkfd_process_info.vm_list_head */ 402 struct list_head vm_list_node; 403 404 /* Valid while the PD is reserved or fenced */ 405 uint64_t pd_phys_addr; 406 407 /* Some basic info about the task */ 408 struct amdgpu_task_info *task_info; 409 410 /* Store positions of group of BOs */ 411 struct ttm_lru_bulk_move lru_bulk_move; 412 /* Flag to indicate if VM is used for compute */ 413 bool is_compute_context; 414 415 /* Memory partition number, -1 means any partition */ 416 int8_t mem_id; 417 418 /* cached fault info */ 419 struct amdgpu_vm_fault_info fault_info; 420 }; 421 422 struct amdgpu_vm_manager { 423 /* Handling of VMIDs */ 424 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 425 unsigned int first_kfd_vmid; 426 bool concurrent_flush; 427 428 /* Handling of VM fences */ 429 u64 fence_context; 430 unsigned seqno[AMDGPU_MAX_RINGS]; 431 432 uint64_t max_pfn; 433 uint32_t num_level; 434 uint32_t block_size; 435 uint32_t fragment_size; 436 enum amdgpu_vm_level root_level; 437 /* vram base address for page table entry */ 438 u64 vram_base_offset; 439 /* vm pte handling */ 440 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 441 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; 442 unsigned vm_pte_num_scheds; 443 struct amdgpu_ring *page_fault; 444 445 /* partial resident texture handling */ 446 spinlock_t prt_lock; 447 atomic_t num_prt_users; 448 449 /* controls how VM page tables are updated for Graphics and Compute. 450 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 451 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 452 */ 453 int vm_update_mode; 454 455 /* PASID to VM mapping, will be used in interrupt context to 456 * look up VM of a page fault 457 */ 458 struct xarray pasids; 459 /* Global registration of recent page fault information */ 460 struct amdgpu_vm_fault_info fault_info; 461 }; 462 463 struct amdgpu_bo_va_mapping; 464 465 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 466 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 467 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 468 469 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; 470 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; 471 472 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 473 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 474 475 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, 476 u32 pasid); 477 478 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 479 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id); 480 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 481 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 482 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 483 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, 484 unsigned int num_fences); 485 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 486 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm); 487 int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, 488 struct ww_acquire_ctx *ticket, 489 int (*callback)(void *p, struct amdgpu_bo *bo), 490 void *param); 491 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 492 int amdgpu_vm_update_pdes(struct amdgpu_device *adev, 493 struct amdgpu_vm *vm, bool immediate); 494 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 495 struct amdgpu_vm *vm, 496 struct dma_fence **fence); 497 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 498 struct amdgpu_vm *vm, 499 struct ww_acquire_ctx *ticket); 500 int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev, 501 struct amdgpu_vm *vm, 502 uint32_t flush_type, 503 uint32_t xcc_mask); 504 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, 505 struct amdgpu_vm *vm, struct amdgpu_bo *bo); 506 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, 507 bool immediate, bool unlocked, bool flush_tlb, bool allow_override, 508 struct dma_resv *resv, uint64_t start, uint64_t last, 509 uint64_t flags, uint64_t offset, uint64_t vram_base, 510 struct ttm_resource *res, dma_addr_t *pages_addr, 511 struct dma_fence **fence); 512 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 513 struct amdgpu_bo_va *bo_va, 514 bool clear); 515 bool amdgpu_vm_evictable(struct amdgpu_bo *bo); 516 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 517 struct amdgpu_bo *bo, bool evicted); 518 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 519 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 520 struct amdgpu_bo *bo); 521 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 522 struct amdgpu_vm *vm, 523 struct amdgpu_bo *bo); 524 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 525 struct amdgpu_bo_va *bo_va, 526 uint64_t addr, uint64_t offset, 527 uint64_t size, uint64_t flags); 528 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 529 struct amdgpu_bo_va *bo_va, 530 uint64_t addr, uint64_t offset, 531 uint64_t size, uint64_t flags); 532 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 533 struct amdgpu_bo_va *bo_va, 534 uint64_t addr); 535 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 536 struct amdgpu_vm *vm, 537 uint64_t saddr, uint64_t size); 538 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 539 uint64_t addr); 540 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 541 void amdgpu_vm_bo_del(struct amdgpu_device *adev, 542 struct amdgpu_bo_va *bo_va); 543 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 544 uint32_t fragment_size_default, unsigned max_level, 545 unsigned max_bits); 546 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 547 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 548 struct amdgpu_job *job); 549 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 550 551 struct amdgpu_task_info * 552 amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid); 553 554 struct amdgpu_task_info * 555 amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm); 556 557 void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info); 558 559 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 560 u32 vmid, u32 node_id, uint64_t addr, 561 bool write_fault); 562 563 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 564 565 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 566 struct amdgpu_vm *vm); 567 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, 568 struct amdgpu_mem_stats *stats); 569 570 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, 571 struct amdgpu_bo_vm *vmbo, bool immediate); 572 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, 573 int level, bool immediate, struct amdgpu_bo_vm **vmbo, 574 int32_t xcp_id); 575 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm); 576 577 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params, 578 struct amdgpu_vm_bo_base *entry); 579 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, 580 uint64_t start, uint64_t end, 581 uint64_t dst, uint64_t flags); 582 void amdgpu_vm_pt_free_work(struct work_struct *work); 583 void amdgpu_vm_pt_free_list(struct amdgpu_device *adev, 584 struct amdgpu_vm_update_params *params); 585 586 #if defined(CONFIG_DEBUG_FS) 587 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); 588 #endif 589 590 int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm); 591 592 bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo); 593 594 /** 595 * amdgpu_vm_tlb_seq - return tlb flush sequence number 596 * @vm: the amdgpu_vm structure to query 597 * 598 * Returns the tlb flush sequence number which indicates that the VM TLBs needs 599 * to be invalidated whenever the sequence number change. 600 */ 601 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm) 602 { 603 unsigned long flags; 604 spinlock_t *lock; 605 606 /* 607 * Workaround to stop racing between the fence signaling and handling 608 * the cb. The lock is static after initially setting it up, just make 609 * sure that the dma_fence structure isn't freed up. 610 */ 611 rcu_read_lock(); 612 lock = vm->last_tlb_flush->lock; 613 rcu_read_unlock(); 614 615 spin_lock_irqsave(lock, flags); 616 spin_unlock_irqrestore(lock, flags); 617 618 return atomic64_read(&vm->tlb_seq); 619 } 620 621 /* 622 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS 623 * happens while holding this lock anywhere to prevent deadlocks when 624 * an MMU notifier runs in reclaim-FS context. 625 */ 626 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm) 627 { 628 mutex_lock(&vm->eviction_lock); 629 vm->saved_flags = memalloc_noreclaim_save(); 630 } 631 632 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) 633 { 634 if (mutex_trylock(&vm->eviction_lock)) { 635 vm->saved_flags = memalloc_noreclaim_save(); 636 return true; 637 } 638 return false; 639 } 640 641 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) 642 { 643 memalloc_noreclaim_restore(vm->saved_flags); 644 mutex_unlock(&vm->eviction_lock); 645 } 646 647 void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, 648 unsigned int pasid, 649 uint64_t addr, 650 uint32_t status, 651 unsigned int vmhub); 652 void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, 653 struct amdgpu_vm *vm, 654 struct dma_fence **fence); 655 656 #endif 657