xref: /linux/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c (revision 6af91e3d2cfc8bb579b1aa2d22cd91f8c34acdf6) 
1 // SPDX-License-Identifier: GPL-2.0+
2 
3 #include <drm/drm_atomic_helper.h>
4 #include <drm/drm_edid.h>
5 #include <drm/drm_simple_kms_helper.h>
6 #include <drm/drm_gem_framebuffer_helper.h>
7 #include <drm/drm_vblank.h>
8 
9 #include "amdgpu.h"
10 #ifdef CONFIG_DRM_AMDGPU_SI
11 #include "dce_v6_0.h"
12 #endif
13 #ifdef CONFIG_DRM_AMDGPU_CIK
14 #include "dce_v8_0.h"
15 #endif
16 #include "dce_v10_0.h"
17 #include "dce_v11_0.h"
18 #include "ivsrcid/ivsrcid_vislands30.h"
19 #include "amdgpu_vkms.h"
20 #include "amdgpu_display.h"
21 #include "atom.h"
22 #include "amdgpu_irq.h"
23 
24 /**
25  * DOC: amdgpu_vkms
26  *
27  * The amdgpu vkms interface provides a virtual KMS interface for several use
28  * cases: devices without display hardware, platforms where the actual display
29  * hardware is not useful (e.g., servers), SR-IOV virtual functions, device
30  * emulation/simulation, and device bring up prior to display hardware being
31  * usable. We previously emulated a legacy KMS interface, but there was a desire
32  * to move to the atomic KMS interface. The vkms driver did everything we
33  * needed, but we wanted KMS support natively in the driver without buffer
34  * sharing and the ability to support an instance of VKMS per device. We first
35  * looked at splitting vkms into a stub driver and a helper module that other
36  * drivers could use to implement a virtual display, but this strategy ended up
37  * being messy due to driver specific callbacks needed for buffer management.
38  * Ultimately, it proved easier to import the vkms code as it mostly used core
39  * drm helpers anyway.
40  */
41 
42 static const u32 amdgpu_vkms_formats[] = {
43 	DRM_FORMAT_XRGB8888,
44 };
45 
46 static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer)
47 {
48 	struct amdgpu_crtc *amdgpu_crtc = container_of(timer, struct amdgpu_crtc, vblank_timer);
49 	struct drm_crtc *crtc = &amdgpu_crtc->base;
50 	struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc);
51 	u64 ret_overrun;
52 	bool ret;
53 
54 	ret_overrun = hrtimer_forward_now(&amdgpu_crtc->vblank_timer,
55 					  output->period_ns);
56 	if (ret_overrun != 1)
57 		DRM_WARN("%s: vblank timer overrun\n", __func__);
58 
59 	ret = drm_crtc_handle_vblank(crtc);
60 	/* Don't queue timer again when vblank is disabled. */
61 	if (!ret)
62 		return HRTIMER_NORESTART;
63 
64 	return HRTIMER_RESTART;
65 }
66 
67 static int amdgpu_vkms_enable_vblank(struct drm_crtc *crtc)
68 {
69 	struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
70 	struct amdgpu_vkms_output *out = drm_crtc_to_amdgpu_vkms_output(crtc);
71 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
72 
73 	drm_calc_timestamping_constants(crtc, &crtc->mode);
74 
75 	out->period_ns = ktime_set(0, vblank->framedur_ns);
76 	hrtimer_start(&amdgpu_crtc->vblank_timer, out->period_ns, HRTIMER_MODE_REL);
77 
78 	return 0;
79 }
80 
81 static void amdgpu_vkms_disable_vblank(struct drm_crtc *crtc)
82 {
83 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
84 
85 	hrtimer_try_to_cancel(&amdgpu_crtc->vblank_timer);
86 }
87 
88 static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc,
89 					     int *max_error,
90 					     ktime_t *vblank_time,
91 					     bool in_vblank_irq)
92 {
93 	struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc);
94 	struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
95 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
96 
97 	if (!READ_ONCE(vblank->enabled)) {
98 		*vblank_time = ktime_get();
99 		return true;
100 	}
101 
102 	*vblank_time = READ_ONCE(amdgpu_crtc->vblank_timer.node.expires);
103 
104 	if (WARN_ON(*vblank_time == vblank->time))
105 		return true;
106 
107 	/*
108 	 * To prevent races we roll the hrtimer forward before we do any
109 	 * interrupt processing - this is how real hw works (the interrupt is
110 	 * only generated after all the vblank registers are updated) and what
111 	 * the vblank core expects. Therefore we need to always correct the
112 	 * timestampe by one frame.
113 	 */
114 	*vblank_time -= output->period_ns;
115 
116 	return true;
117 }
118 
119 static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = {
120 	.set_config             = drm_atomic_helper_set_config,
121 	.destroy                = drm_crtc_cleanup,
122 	.page_flip              = drm_atomic_helper_page_flip,
123 	.reset                  = drm_atomic_helper_crtc_reset,
124 	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
125 	.atomic_destroy_state   = drm_atomic_helper_crtc_destroy_state,
126 	.enable_vblank		= amdgpu_vkms_enable_vblank,
127 	.disable_vblank		= amdgpu_vkms_disable_vblank,
128 	.get_vblank_timestamp	= amdgpu_vkms_get_vblank_timestamp,
129 };
130 
131 static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc,
132 					   struct drm_atomic_state *state)
133 {
134 	drm_crtc_vblank_on(crtc);
135 }
136 
137 static void amdgpu_vkms_crtc_atomic_disable(struct drm_crtc *crtc,
138 					    struct drm_atomic_state *state)
139 {
140 	drm_crtc_vblank_off(crtc);
141 }
142 
143 static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc,
144 					  struct drm_atomic_state *state)
145 {
146 	unsigned long flags;
147 	if (crtc->state->event) {
148 		spin_lock_irqsave(&crtc->dev->event_lock, flags);
149 
150 		if (drm_crtc_vblank_get(crtc) != 0)
151 			drm_crtc_send_vblank_event(crtc, crtc->state->event);
152 		else
153 			drm_crtc_arm_vblank_event(crtc, crtc->state->event);
154 
155 		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
156 
157 		crtc->state->event = NULL;
158 	}
159 }
160 
161 static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = {
162 	.atomic_flush	= amdgpu_vkms_crtc_atomic_flush,
163 	.atomic_enable	= amdgpu_vkms_crtc_atomic_enable,
164 	.atomic_disable	= amdgpu_vkms_crtc_atomic_disable,
165 };
166 
167 static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc,
168 			  struct drm_plane *primary, struct drm_plane *cursor)
169 {
170 	struct amdgpu_device *adev = drm_to_adev(dev);
171 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
172 	int ret;
173 
174 	ret = drm_crtc_init_with_planes(dev, crtc, primary, cursor,
175 					&amdgpu_vkms_crtc_funcs, NULL);
176 	if (ret) {
177 		DRM_ERROR("Failed to init CRTC\n");
178 		return ret;
179 	}
180 
181 	drm_crtc_helper_add(crtc, &amdgpu_vkms_crtc_helper_funcs);
182 
183 	amdgpu_crtc->crtc_id = drm_crtc_index(crtc);
184 	adev->mode_info.crtcs[drm_crtc_index(crtc)] = amdgpu_crtc;
185 
186 	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
187 	amdgpu_crtc->encoder = NULL;
188 	amdgpu_crtc->connector = NULL;
189 	amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
190 
191 	hrtimer_init(&amdgpu_crtc->vblank_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
192 	amdgpu_crtc->vblank_timer.function = &amdgpu_vkms_vblank_simulate;
193 
194 	return ret;
195 }
196 
197 static const struct drm_connector_funcs amdgpu_vkms_connector_funcs = {
198 	.fill_modes = drm_helper_probe_single_connector_modes,
199 	.destroy = drm_connector_cleanup,
200 	.reset = drm_atomic_helper_connector_reset,
201 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
202 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
203 };
204 
205 static int amdgpu_vkms_conn_get_modes(struct drm_connector *connector)
206 {
207 	struct drm_device *dev = connector->dev;
208 	struct drm_display_mode *mode = NULL;
209 	unsigned i;
210 	static const struct mode_size {
211 		int w;
212 		int h;
213 	} common_modes[] = {
214 		{ 640,  480},
215 		{ 720,  480},
216 		{ 800,  600},
217 		{ 848,  480},
218 		{1024,  768},
219 		{1152,  768},
220 		{1280,  720},
221 		{1280,  800},
222 		{1280,  854},
223 		{1280,  960},
224 		{1280, 1024},
225 		{1440,  900},
226 		{1400, 1050},
227 		{1680, 1050},
228 		{1600, 1200},
229 		{1920, 1080},
230 		{1920, 1200},
231 		{2560, 1440},
232 		{4096, 3112},
233 		{3656, 2664},
234 		{3840, 2160},
235 		{4096, 2160},
236 	};
237 
238 	for (i = 0; i < ARRAY_SIZE(common_modes); i++) {
239 		mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
240 		if (!mode)
241 			continue;
242 		drm_mode_probed_add(connector, mode);
243 	}
244 
245 	drm_set_preferred_mode(connector, XRES_DEF, YRES_DEF);
246 
247 	return ARRAY_SIZE(common_modes);
248 }
249 
250 static const struct drm_connector_helper_funcs amdgpu_vkms_conn_helper_funcs = {
251 	.get_modes    = amdgpu_vkms_conn_get_modes,
252 };
253 
254 static const struct drm_plane_funcs amdgpu_vkms_plane_funcs = {
255 	.update_plane		= drm_atomic_helper_update_plane,
256 	.disable_plane		= drm_atomic_helper_disable_plane,
257 	.destroy		= drm_plane_cleanup,
258 	.reset			= drm_atomic_helper_plane_reset,
259 	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
260 	.atomic_destroy_state	= drm_atomic_helper_plane_destroy_state,
261 };
262 
263 static void amdgpu_vkms_plane_atomic_update(struct drm_plane *plane,
264 					    struct drm_atomic_state *old_state)
265 {
266 	return;
267 }
268 
269 static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane,
270 					  struct drm_atomic_state *state)
271 {
272 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
273 										 plane);
274 	struct drm_crtc_state *crtc_state;
275 	int ret;
276 
277 	if (!new_plane_state->fb || WARN_ON(!new_plane_state->crtc))
278 		return 0;
279 
280 	crtc_state = drm_atomic_get_crtc_state(state,
281 					       new_plane_state->crtc);
282 	if (IS_ERR(crtc_state))
283 		return PTR_ERR(crtc_state);
284 
285 	ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
286 						  DRM_PLANE_NO_SCALING,
287 						  DRM_PLANE_NO_SCALING,
288 						  false, true);
289 	if (ret != 0)
290 		return ret;
291 
292 	/* for now primary plane must be visible and full screen */
293 	if (!new_plane_state->visible)
294 		return -EINVAL;
295 
296 	return 0;
297 }
298 
299 static int amdgpu_vkms_prepare_fb(struct drm_plane *plane,
300 				  struct drm_plane_state *new_state)
301 {
302 	struct amdgpu_framebuffer *afb;
303 	struct drm_gem_object *obj;
304 	struct amdgpu_device *adev;
305 	struct amdgpu_bo *rbo;
306 	uint32_t domain;
307 	int r;
308 
309 	if (!new_state->fb) {
310 		DRM_DEBUG_KMS("No FB bound\n");
311 		return 0;
312 	}
313 	afb = to_amdgpu_framebuffer(new_state->fb);
314 
315 	obj = drm_gem_fb_get_obj(new_state->fb, 0);
316 	if (!obj) {
317 		DRM_ERROR("Failed to get obj from framebuffer\n");
318 		return -EINVAL;
319 	}
320 
321 	rbo = gem_to_amdgpu_bo(obj);
322 	adev = amdgpu_ttm_adev(rbo->tbo.bdev);
323 
324 	r = amdgpu_bo_reserve(rbo, true);
325 	if (r) {
326 		dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
327 		return r;
328 	}
329 
330 	r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1);
331 	if (r) {
332 		dev_err(adev->dev, "allocating fence slot failed (%d)\n", r);
333 		goto error_unlock;
334 	}
335 
336 	if (plane->type != DRM_PLANE_TYPE_CURSOR)
337 		domain = amdgpu_display_supported_domains(adev, rbo->flags);
338 	else
339 		domain = AMDGPU_GEM_DOMAIN_VRAM;
340 
341 	r = amdgpu_bo_pin(rbo, domain);
342 	if (unlikely(r != 0)) {
343 		if (r != -ERESTARTSYS)
344 			DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
345 		goto error_unlock;
346 	}
347 
348 	r = amdgpu_ttm_alloc_gart(&rbo->tbo);
349 	if (unlikely(r != 0)) {
350 		DRM_ERROR("%p bind failed\n", rbo);
351 		goto error_unpin;
352 	}
353 
354 	amdgpu_bo_unreserve(rbo);
355 
356 	afb->address = amdgpu_bo_gpu_offset(rbo);
357 
358 	amdgpu_bo_ref(rbo);
359 
360 	return 0;
361 
362 error_unpin:
363 	amdgpu_bo_unpin(rbo);
364 
365 error_unlock:
366 	amdgpu_bo_unreserve(rbo);
367 	return r;
368 }
369 
370 static void amdgpu_vkms_cleanup_fb(struct drm_plane *plane,
371 				   struct drm_plane_state *old_state)
372 {
373 	struct amdgpu_bo *rbo;
374 	struct drm_gem_object *obj;
375 	int r;
376 
377 	if (!old_state->fb)
378 		return;
379 
380 	obj = drm_gem_fb_get_obj(old_state->fb, 0);
381 	if (!obj) {
382 		DRM_ERROR("Failed to get obj from framebuffer\n");
383 		return;
384 	}
385 
386 	rbo = gem_to_amdgpu_bo(obj);
387 	r = amdgpu_bo_reserve(rbo, false);
388 	if (unlikely(r)) {
389 		DRM_ERROR("failed to reserve rbo before unpin\n");
390 		return;
391 	}
392 
393 	amdgpu_bo_unpin(rbo);
394 	amdgpu_bo_unreserve(rbo);
395 	amdgpu_bo_unref(&rbo);
396 }
397 
398 static const struct drm_plane_helper_funcs amdgpu_vkms_primary_helper_funcs = {
399 	.atomic_update		= amdgpu_vkms_plane_atomic_update,
400 	.atomic_check		= amdgpu_vkms_plane_atomic_check,
401 	.prepare_fb		= amdgpu_vkms_prepare_fb,
402 	.cleanup_fb		= amdgpu_vkms_cleanup_fb,
403 };
404 
405 static struct drm_plane *amdgpu_vkms_plane_init(struct drm_device *dev,
406 						enum drm_plane_type type,
407 						int index)
408 {
409 	struct drm_plane *plane;
410 	int ret;
411 
412 	plane = kzalloc(sizeof(*plane), GFP_KERNEL);
413 	if (!plane)
414 		return ERR_PTR(-ENOMEM);
415 
416 	ret = drm_universal_plane_init(dev, plane, 1 << index,
417 				       &amdgpu_vkms_plane_funcs,
418 				       amdgpu_vkms_formats,
419 				       ARRAY_SIZE(amdgpu_vkms_formats),
420 				       NULL, type, NULL);
421 	if (ret) {
422 		kfree(plane);
423 		return ERR_PTR(ret);
424 	}
425 
426 	drm_plane_helper_add(plane, &amdgpu_vkms_primary_helper_funcs);
427 
428 	return plane;
429 }
430 
431 static int amdgpu_vkms_output_init(struct drm_device *dev, struct
432 				   amdgpu_vkms_output *output, int index)
433 {
434 	struct drm_connector *connector = &output->connector;
435 	struct drm_encoder *encoder = &output->encoder;
436 	struct drm_crtc *crtc = &output->crtc.base;
437 	struct drm_plane *primary, *cursor = NULL;
438 	int ret;
439 
440 	primary = amdgpu_vkms_plane_init(dev, DRM_PLANE_TYPE_PRIMARY, index);
441 	if (IS_ERR(primary))
442 		return PTR_ERR(primary);
443 
444 	ret = amdgpu_vkms_crtc_init(dev, crtc, primary, cursor);
445 	if (ret)
446 		goto err_crtc;
447 
448 	ret = drm_connector_init(dev, connector, &amdgpu_vkms_connector_funcs,
449 				 DRM_MODE_CONNECTOR_VIRTUAL);
450 	if (ret) {
451 		DRM_ERROR("Failed to init connector\n");
452 		goto err_connector;
453 	}
454 
455 	drm_connector_helper_add(connector, &amdgpu_vkms_conn_helper_funcs);
456 
457 	ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_VIRTUAL);
458 	if (ret) {
459 		DRM_ERROR("Failed to init encoder\n");
460 		goto err_encoder;
461 	}
462 	encoder->possible_crtcs = 1 << index;
463 
464 	ret = drm_connector_attach_encoder(connector, encoder);
465 	if (ret) {
466 		DRM_ERROR("Failed to attach connector to encoder\n");
467 		goto err_attach;
468 	}
469 
470 	drm_mode_config_reset(dev);
471 
472 	return 0;
473 
474 err_attach:
475 	drm_encoder_cleanup(encoder);
476 
477 err_encoder:
478 	drm_connector_cleanup(connector);
479 
480 err_connector:
481 	drm_crtc_cleanup(crtc);
482 
483 err_crtc:
484 	drm_plane_cleanup(primary);
485 
486 	return ret;
487 }
488 
489 const struct drm_mode_config_funcs amdgpu_vkms_mode_funcs = {
490 	.fb_create = amdgpu_display_user_framebuffer_create,
491 	.atomic_check = drm_atomic_helper_check,
492 	.atomic_commit = drm_atomic_helper_commit,
493 };
494 
495 static int amdgpu_vkms_sw_init(void *handle)
496 {
497 	int r, i;
498 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
499 
500 	adev->amdgpu_vkms_output = kcalloc(adev->mode_info.num_crtc,
501 		sizeof(struct amdgpu_vkms_output), GFP_KERNEL);
502 	if (!adev->amdgpu_vkms_output)
503 		return -ENOMEM;
504 
505 	adev_to_drm(adev)->max_vblank_count = 0;
506 
507 	adev_to_drm(adev)->mode_config.funcs = &amdgpu_vkms_mode_funcs;
508 
509 	adev_to_drm(adev)->mode_config.max_width = XRES_MAX;
510 	adev_to_drm(adev)->mode_config.max_height = YRES_MAX;
511 
512 	adev_to_drm(adev)->mode_config.preferred_depth = 24;
513 	adev_to_drm(adev)->mode_config.prefer_shadow = 1;
514 
515 	adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
516 
517 	r = amdgpu_display_modeset_create_props(adev);
518 	if (r)
519 		return r;
520 
521 	/* allocate crtcs, encoders, connectors */
522 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
523 		r = amdgpu_vkms_output_init(adev_to_drm(adev), &adev->amdgpu_vkms_output[i], i);
524 		if (r)
525 			return r;
526 	}
527 
528 	r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
529 	if (r)
530 		return r;
531 
532 	drm_kms_helper_poll_init(adev_to_drm(adev));
533 
534 	adev->mode_info.mode_config_initialized = true;
535 	return 0;
536 }
537 
538 static int amdgpu_vkms_sw_fini(void *handle)
539 {
540 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
541 	int i = 0;
542 
543 	for (i = 0; i < adev->mode_info.num_crtc; i++)
544 		if (adev->mode_info.crtcs[i])
545 			hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer);
546 
547 	drm_kms_helper_poll_fini(adev_to_drm(adev));
548 	drm_mode_config_cleanup(adev_to_drm(adev));
549 
550 	adev->mode_info.mode_config_initialized = false;
551 
552 	kfree(adev->mode_info.bios_hardcoded_edid);
553 	kfree(adev->amdgpu_vkms_output);
554 	return 0;
555 }
556 
557 static int amdgpu_vkms_hw_init(void *handle)
558 {
559 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
560 
561 	switch (adev->asic_type) {
562 #ifdef CONFIG_DRM_AMDGPU_SI
563 	case CHIP_TAHITI:
564 	case CHIP_PITCAIRN:
565 	case CHIP_VERDE:
566 	case CHIP_OLAND:
567 		dce_v6_0_disable_dce(adev);
568 		break;
569 #endif
570 #ifdef CONFIG_DRM_AMDGPU_CIK
571 	case CHIP_BONAIRE:
572 	case CHIP_HAWAII:
573 	case CHIP_KAVERI:
574 	case CHIP_KABINI:
575 	case CHIP_MULLINS:
576 		dce_v8_0_disable_dce(adev);
577 		break;
578 #endif
579 	case CHIP_FIJI:
580 	case CHIP_TONGA:
581 		dce_v10_0_disable_dce(adev);
582 		break;
583 	case CHIP_CARRIZO:
584 	case CHIP_STONEY:
585 	case CHIP_POLARIS10:
586 	case CHIP_POLARIS11:
587 	case CHIP_VEGAM:
588 		dce_v11_0_disable_dce(adev);
589 		break;
590 	case CHIP_TOPAZ:
591 #ifdef CONFIG_DRM_AMDGPU_SI
592 	case CHIP_HAINAN:
593 #endif
594 		/* no DCE */
595 		break;
596 	default:
597 		break;
598 	}
599 	return 0;
600 }
601 
602 static int amdgpu_vkms_hw_fini(void *handle)
603 {
604 	return 0;
605 }
606 
607 static int amdgpu_vkms_suspend(void *handle)
608 {
609 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
610 	int r;
611 
612 	r = drm_mode_config_helper_suspend(adev_to_drm(adev));
613 	if (r)
614 		return r;
615 	return amdgpu_vkms_hw_fini(handle);
616 }
617 
618 static int amdgpu_vkms_resume(void *handle)
619 {
620 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
621 	int r;
622 
623 	r = amdgpu_vkms_hw_init(handle);
624 	if (r)
625 		return r;
626 	return drm_mode_config_helper_resume(adev_to_drm(adev));
627 }
628 
629 static bool amdgpu_vkms_is_idle(void *handle)
630 {
631 	return true;
632 }
633 
634 static int amdgpu_vkms_wait_for_idle(void *handle)
635 {
636 	return 0;
637 }
638 
639 static int amdgpu_vkms_soft_reset(void *handle)
640 {
641 	return 0;
642 }
643 
644 static int amdgpu_vkms_set_clockgating_state(void *handle,
645 					  enum amd_clockgating_state state)
646 {
647 	return 0;
648 }
649 
650 static int amdgpu_vkms_set_powergating_state(void *handle,
651 					  enum amd_powergating_state state)
652 {
653 	return 0;
654 }
655 
656 static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = {
657 	.name = "amdgpu_vkms",
658 	.early_init = NULL,
659 	.late_init = NULL,
660 	.sw_init = amdgpu_vkms_sw_init,
661 	.sw_fini = amdgpu_vkms_sw_fini,
662 	.hw_init = amdgpu_vkms_hw_init,
663 	.hw_fini = amdgpu_vkms_hw_fini,
664 	.suspend = amdgpu_vkms_suspend,
665 	.resume = amdgpu_vkms_resume,
666 	.is_idle = amdgpu_vkms_is_idle,
667 	.wait_for_idle = amdgpu_vkms_wait_for_idle,
668 	.soft_reset = amdgpu_vkms_soft_reset,
669 	.set_clockgating_state = amdgpu_vkms_set_clockgating_state,
670 	.set_powergating_state = amdgpu_vkms_set_powergating_state,
671 	.dump_ip_state = NULL,
672 	.print_ip_state = NULL,
673 };
674 
675 const struct amdgpu_ip_block_version amdgpu_vkms_ip_block = {
676 	.type = AMD_IP_BLOCK_TYPE_DCE,
677 	.major = 1,
678 	.minor = 0,
679 	.rev = 0,
680 	.funcs = &amdgpu_vkms_ip_funcs,
681 };
682 
683