1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Monk.liu@amd.com 23 */ 24 #ifndef AMDGPU_VIRT_H 25 #define AMDGPU_VIRT_H 26 27 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 28 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 29 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 30 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 31 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 32 33 /* all asic after AI use this offset */ 34 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 35 /* tonga/fiji use this offset */ 36 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 37 38 struct amdgpu_mm_table { 39 struct amdgpu_bo *bo; 40 uint32_t *cpu_addr; 41 uint64_t gpu_addr; 42 }; 43 44 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16 45 46 /* struct error_entry - amdgpu VF error information. */ 47 struct amdgpu_vf_error_buffer { 48 struct mutex lock; 49 int read_count; 50 int write_count; 51 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; 52 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE]; 53 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; 54 }; 55 56 /** 57 * struct amdgpu_virt_ops - amdgpu device virt operations 58 */ 59 struct amdgpu_virt_ops { 60 int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 61 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 62 int (*req_init_data)(struct amdgpu_device *adev); 63 int (*reset_gpu)(struct amdgpu_device *adev); 64 int (*wait_reset)(struct amdgpu_device *adev); 65 void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3); 66 }; 67 68 /* 69 * Firmware Reserve Frame buffer 70 */ 71 struct amdgpu_virt_fw_reserve { 72 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; 73 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; 74 unsigned int checksum_key; 75 }; 76 /* 77 * Defination between PF and VF 78 * Structures forcibly aligned to 4 to keep the same style as PF. 79 */ 80 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024) 81 82 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \ 83 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2)) 84 85 enum AMDGIM_FEATURE_FLAG { 86 /* GIM supports feature of Error log collecting */ 87 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, 88 /* GIM supports feature of loading uCodes */ 89 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, 90 /* VRAM LOST by GIM */ 91 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, 92 /* MM bandwidth */ 93 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8, 94 /* PP ONE VF MODE in GIM */ 95 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4), 96 }; 97 98 struct amd_sriov_msg_pf2vf_info_header { 99 /* the total structure size in byte. */ 100 uint32_t size; 101 /* version of this structure, written by the GIM */ 102 uint32_t version; 103 /* reserved */ 104 uint32_t reserved[2]; 105 } __aligned(4); 106 struct amdgim_pf2vf_info_v1 { 107 /* header contains size and version */ 108 struct amd_sriov_msg_pf2vf_info_header header; 109 /* max_width * max_height */ 110 unsigned int uvd_enc_max_pixels_count; 111 /* 16x16 pixels/sec, codec independent */ 112 unsigned int uvd_enc_max_bandwidth; 113 /* max_width * max_height */ 114 unsigned int vce_enc_max_pixels_count; 115 /* 16x16 pixels/sec, codec independent */ 116 unsigned int vce_enc_max_bandwidth; 117 /* MEC FW position in kb from the start of visible frame buffer */ 118 unsigned int mecfw_kboffset; 119 /* The features flags of the GIM driver supports. */ 120 unsigned int feature_flags; 121 /* use private key from mailbox 2 to create chueksum */ 122 unsigned int checksum; 123 } __aligned(4); 124 125 struct amdgim_pf2vf_info_v2 { 126 /* header contains size and version */ 127 struct amd_sriov_msg_pf2vf_info_header header; 128 /* use private key from mailbox 2 to create chueksum */ 129 uint32_t checksum; 130 /* The features flags of the GIM driver supports. */ 131 uint32_t feature_flags; 132 /* max_width * max_height */ 133 uint32_t uvd_enc_max_pixels_count; 134 /* 16x16 pixels/sec, codec independent */ 135 uint32_t uvd_enc_max_bandwidth; 136 /* max_width * max_height */ 137 uint32_t vce_enc_max_pixels_count; 138 /* 16x16 pixels/sec, codec independent */ 139 uint32_t vce_enc_max_bandwidth; 140 /* MEC FW position in kb from the start of VF visible frame buffer */ 141 uint64_t mecfw_kboffset; 142 /* MEC FW size in KB */ 143 uint32_t mecfw_ksize; 144 /* UVD FW position in kb from the start of VF visible frame buffer */ 145 uint64_t uvdfw_kboffset; 146 /* UVD FW size in KB */ 147 uint32_t uvdfw_ksize; 148 /* VCE FW position in kb from the start of VF visible frame buffer */ 149 uint64_t vcefw_kboffset; 150 /* VCE FW size in KB */ 151 uint32_t vcefw_ksize; 152 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (9 + sizeof(struct amd_sriov_msg_pf2vf_info_header)/sizeof(uint32_t)), 3)]; 153 } __aligned(4); 154 155 156 struct amd_sriov_msg_vf2pf_info_header { 157 /* the total structure size in byte. */ 158 uint32_t size; 159 /*version of this structure, written by the guest */ 160 uint32_t version; 161 /* reserved */ 162 uint32_t reserved[2]; 163 } __aligned(4); 164 165 struct amdgim_vf2pf_info_v1 { 166 /* header contains size and version */ 167 struct amd_sriov_msg_vf2pf_info_header header; 168 /* driver version */ 169 char driver_version[64]; 170 /* driver certification, 1=WHQL, 0=None */ 171 unsigned int driver_cert; 172 /* guest OS type and version: need a define */ 173 unsigned int os_info; 174 /* in the unit of 1M */ 175 unsigned int fb_usage; 176 /* guest gfx engine usage percentage */ 177 unsigned int gfx_usage; 178 /* guest gfx engine health percentage */ 179 unsigned int gfx_health; 180 /* guest compute engine usage percentage */ 181 unsigned int compute_usage; 182 /* guest compute engine health percentage */ 183 unsigned int compute_health; 184 /* guest vce engine usage percentage. 0xffff means N/A. */ 185 unsigned int vce_enc_usage; 186 /* guest vce engine health percentage. 0xffff means N/A. */ 187 unsigned int vce_enc_health; 188 /* guest uvd engine usage percentage. 0xffff means N/A. */ 189 unsigned int uvd_enc_usage; 190 /* guest uvd engine usage percentage. 0xffff means N/A. */ 191 unsigned int uvd_enc_health; 192 unsigned int checksum; 193 } __aligned(4); 194 195 struct amdgim_vf2pf_info_v2 { 196 /* header contains size and version */ 197 struct amd_sriov_msg_vf2pf_info_header header; 198 uint32_t checksum; 199 /* driver version */ 200 uint8_t driver_version[64]; 201 /* driver certification, 1=WHQL, 0=None */ 202 uint32_t driver_cert; 203 /* guest OS type and version: need a define */ 204 uint32_t os_info; 205 /* in the unit of 1M */ 206 uint32_t fb_usage; 207 /* guest gfx engine usage percentage */ 208 uint32_t gfx_usage; 209 /* guest gfx engine health percentage */ 210 uint32_t gfx_health; 211 /* guest compute engine usage percentage */ 212 uint32_t compute_usage; 213 /* guest compute engine health percentage */ 214 uint32_t compute_health; 215 /* guest vce engine usage percentage. 0xffff means N/A. */ 216 uint32_t vce_enc_usage; 217 /* guest vce engine health percentage. 0xffff means N/A. */ 218 uint32_t vce_enc_health; 219 /* guest uvd engine usage percentage. 0xffff means N/A. */ 220 uint32_t uvd_enc_usage; 221 /* guest uvd engine usage percentage. 0xffff means N/A. */ 222 uint32_t uvd_enc_health; 223 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; 224 } __aligned(4); 225 226 #define AMDGPU_FW_VRAM_VF2PF_VER 2 227 typedef struct amdgim_vf2pf_info_v2 amdgim_vf2pf_info ; 228 229 #define AMDGPU_FW_VRAM_VF2PF_WRITE(adev, field, val) \ 230 do { \ 231 ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field = (val); \ 232 } while (0) 233 234 #define AMDGPU_FW_VRAM_VF2PF_READ(adev, field, val) \ 235 do { \ 236 (*val) = ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field; \ 237 } while (0) 238 239 #define AMDGPU_FW_VRAM_PF2VF_READ(adev, field, val) \ 240 do { \ 241 if (!adev->virt.fw_reserve.p_pf2vf) \ 242 *(val) = 0; \ 243 else { \ 244 if (adev->virt.fw_reserve.p_pf2vf->version == 1) \ 245 *(val) = ((struct amdgim_pf2vf_info_v1 *)adev->virt.fw_reserve.p_pf2vf)->field; \ 246 if (adev->virt.fw_reserve.p_pf2vf->version == 2) \ 247 *(val) = ((struct amdgim_pf2vf_info_v2 *)adev->virt.fw_reserve.p_pf2vf)->field; \ 248 } \ 249 } while (0) 250 251 /* GPU virtualization */ 252 struct amdgpu_virt { 253 uint32_t caps; 254 struct amdgpu_bo *csa_obj; 255 void *csa_cpu_addr; 256 bool chained_ib_support; 257 uint32_t reg_val_offs; 258 struct amdgpu_irq_src ack_irq; 259 struct amdgpu_irq_src rcv_irq; 260 struct work_struct flr_work; 261 struct amdgpu_mm_table mm_table; 262 const struct amdgpu_virt_ops *ops; 263 struct amdgpu_vf_error_buffer vf_errors; 264 struct amdgpu_virt_fw_reserve fw_reserve; 265 uint32_t gim_feature; 266 uint32_t reg_access_mode; 267 int req_init_data_ver; 268 }; 269 270 #define amdgpu_sriov_enabled(adev) \ 271 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 272 273 #define amdgpu_sriov_vf(adev) \ 274 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 275 276 #define amdgpu_sriov_bios(adev) \ 277 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 278 279 #define amdgpu_sriov_runtime(adev) \ 280 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 281 282 #define amdgpu_sriov_fullaccess(adev) \ 283 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev))) 284 285 #define amdgpu_passthrough(adev) \ 286 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 287 288 static inline bool is_virtual_machine(void) 289 { 290 #ifdef CONFIG_X86 291 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 292 #else 293 return false; 294 #endif 295 } 296 297 #define amdgpu_sriov_is_pp_one_vf(adev) \ 298 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 299 300 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 301 void amdgpu_virt_init_setting(struct amdgpu_device *adev); 302 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, 303 uint32_t reg0, uint32_t rreg1, 304 uint32_t ref, uint32_t mask); 305 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 306 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 307 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 308 void amdgpu_virt_request_init_data(struct amdgpu_device *adev); 309 int amdgpu_virt_wait_reset(struct amdgpu_device *adev); 310 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); 311 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); 312 int amdgpu_virt_fw_reserve_get_checksum(void *obj, unsigned long obj_size, 313 unsigned int key, 314 unsigned int chksum); 315 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); 316 void amdgpu_detect_virtualization(struct amdgpu_device *adev); 317 #endif 318