1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Monk.liu@amd.com 23 */ 24 #ifndef AMDGPU_VIRT_H 25 #define AMDGPU_VIRT_H 26 27 #include "amdgv_sriovmsg.h" 28 29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 34 #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */ 35 36 /* flags for indirect register access path supported by rlcg for sriov */ 37 #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28) 38 #define AMDGPU_RLCG_GC_WRITE (0x0 << 28) 39 #define AMDGPU_RLCG_GC_READ (0x1 << 28) 40 #define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28) 41 42 /* error code for indirect register access path supported by rlcg for sriov */ 43 #define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000 44 #define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000 45 #define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000 46 47 #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF 48 #define AMDGPU_RLCG_SCRATCH1_ERROR_MASK 0xF000000 49 50 /* all asic after AI use this offset */ 51 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 52 /* tonga/fiji use this offset */ 53 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 54 55 #define AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT 2 56 57 /* Signature used to validate the SR-IOV dynamic critical region init data header ("INDA") */ 58 #define AMDGPU_SRIOV_CRIT_DATA_SIGNATURE "INDA" 59 #define AMDGPU_SRIOV_CRIT_DATA_SIG_LEN 4 60 61 #define IS_SRIOV_CRIT_REGN_ENTRY_VALID(hdr, id) ((hdr)->valid_tables & (1 << (id))) 62 63 enum amdgpu_sriov_vf_mode { 64 SRIOV_VF_MODE_BARE_METAL = 0, 65 SRIOV_VF_MODE_ONE_VF, 66 SRIOV_VF_MODE_MULTI_VF, 67 }; 68 69 struct amdgpu_mm_table { 70 struct amdgpu_bo *bo; 71 uint32_t *cpu_addr; 72 uint64_t gpu_addr; 73 }; 74 75 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16 76 77 /* struct error_entry - amdgpu VF error information. */ 78 struct amdgpu_vf_error_buffer { 79 struct mutex lock; 80 int read_count; 81 int write_count; 82 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; 83 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE]; 84 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; 85 }; 86 87 enum idh_request; 88 89 /** 90 * struct amdgpu_virt_ops - amdgpu device virt operations 91 */ 92 struct amdgpu_virt_ops { 93 int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 94 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 95 int (*req_init_data)(struct amdgpu_device *adev); 96 int (*reset_gpu)(struct amdgpu_device *adev); 97 void (*ready_to_reset)(struct amdgpu_device *adev); 98 int (*wait_reset)(struct amdgpu_device *adev); 99 void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req, 100 u32 data1, u32 data2, u32 data3); 101 void (*ras_poison_handler)(struct amdgpu_device *adev, 102 enum amdgpu_ras_block block); 103 bool (*rcvd_ras_intr)(struct amdgpu_device *adev); 104 int (*req_ras_err_count)(struct amdgpu_device *adev); 105 int (*req_ras_cper_dump)(struct amdgpu_device *adev, u64 vf_rptr); 106 int (*req_bad_pages)(struct amdgpu_device *adev); 107 int (*req_ras_chk_criti)(struct amdgpu_device *adev, u64 addr); 108 int (*req_remote_ras_cmd)(struct amdgpu_device *adev, 109 u32 param1, u32 param2, u32 param3); 110 }; 111 112 /* 113 * Firmware Reserve Frame buffer 114 */ 115 struct amdgpu_virt_fw_reserve { 116 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; 117 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; 118 void *ras_telemetry; 119 unsigned int checksum_key; 120 }; 121 122 /* 123 * Legacy GIM header 124 * 125 * Defination between PF and VF 126 * Structures forcibly aligned to 4 to keep the same style as PF. 127 */ 128 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024) 129 130 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \ 131 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2)) 132 133 enum AMDGIM_FEATURE_FLAG { 134 /* GIM supports feature of Error log collecting */ 135 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, 136 /* GIM supports feature of loading uCodes */ 137 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, 138 /* VRAM LOST by GIM */ 139 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, 140 /* MM bandwidth */ 141 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8, 142 /* PP ONE VF MODE in GIM */ 143 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4), 144 /* Indirect Reg Access enabled */ 145 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5), 146 /* AV1 Support MODE*/ 147 AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6), 148 /* VCN RB decouple */ 149 AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7), 150 /* MES info */ 151 AMDGIM_FEATURE_MES_INFO_ENABLE = (1 << 8), 152 AMDGIM_FEATURE_RAS_CAPS = (1 << 9), 153 AMDGIM_FEATURE_RAS_TELEMETRY = (1 << 10), 154 AMDGIM_FEATURE_RAS_CPER = (1 << 11), 155 AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK = (1 << 12), 156 }; 157 158 enum AMDGIM_REG_ACCESS_FLAG { 159 /* Use PSP to program IH_RB_CNTL */ 160 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0), 161 /* Use RLC to program MMHUB regs */ 162 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1), 163 /* Use RLC to program GC regs */ 164 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2), 165 /* Use PSP to program L1_TLB_CNTL */ 166 AMDGIM_FEATURE_L1_TLB_CNTL_PSP_EN = (1 << 3), 167 /* Use RLCG to program SQ_CONFIG1 */ 168 AMDGIM_FEATURE_REG_ACCESS_SQ_CONFIG = (1 << 4), 169 }; 170 171 struct amdgim_pf2vf_info_v1 { 172 /* header contains size and version */ 173 struct amd_sriov_msg_pf2vf_info_header header; 174 /* max_width * max_height */ 175 unsigned int uvd_enc_max_pixels_count; 176 /* 16x16 pixels/sec, codec independent */ 177 unsigned int uvd_enc_max_bandwidth; 178 /* max_width * max_height */ 179 unsigned int vce_enc_max_pixels_count; 180 /* 16x16 pixels/sec, codec independent */ 181 unsigned int vce_enc_max_bandwidth; 182 /* MEC FW position in kb from the start of visible frame buffer */ 183 unsigned int mecfw_kboffset; 184 /* The features flags of the GIM driver supports. */ 185 unsigned int feature_flags; 186 /* use private key from mailbox 2 to create chueksum */ 187 unsigned int checksum; 188 } __aligned(4); 189 190 struct amdgim_vf2pf_info_v1 { 191 /* header contains size and version */ 192 struct amd_sriov_msg_vf2pf_info_header header; 193 /* driver version */ 194 char driver_version[64]; 195 /* driver certification, 1=WHQL, 0=None */ 196 unsigned int driver_cert; 197 /* guest OS type and version: need a define */ 198 unsigned int os_info; 199 /* in the unit of 1M */ 200 unsigned int fb_usage; 201 /* guest gfx engine usage percentage */ 202 unsigned int gfx_usage; 203 /* guest gfx engine health percentage */ 204 unsigned int gfx_health; 205 /* guest compute engine usage percentage */ 206 unsigned int compute_usage; 207 /* guest compute engine health percentage */ 208 unsigned int compute_health; 209 /* guest vce engine usage percentage. 0xffff means N/A. */ 210 unsigned int vce_enc_usage; 211 /* guest vce engine health percentage. 0xffff means N/A. */ 212 unsigned int vce_enc_health; 213 /* guest uvd engine usage percentage. 0xffff means N/A. */ 214 unsigned int uvd_enc_usage; 215 /* guest uvd engine usage percentage. 0xffff means N/A. */ 216 unsigned int uvd_enc_health; 217 unsigned int checksum; 218 } __aligned(4); 219 220 struct amdgim_vf2pf_info_v2 { 221 /* header contains size and version */ 222 struct amd_sriov_msg_vf2pf_info_header header; 223 uint32_t checksum; 224 /* driver version */ 225 uint8_t driver_version[64]; 226 /* driver certification, 1=WHQL, 0=None */ 227 uint32_t driver_cert; 228 /* guest OS type and version: need a define */ 229 uint32_t os_info; 230 /* in the unit of 1M */ 231 uint32_t fb_usage; 232 /* guest gfx engine usage percentage */ 233 uint32_t gfx_usage; 234 /* guest gfx engine health percentage */ 235 uint32_t gfx_health; 236 /* guest compute engine usage percentage */ 237 uint32_t compute_usage; 238 /* guest compute engine health percentage */ 239 uint32_t compute_health; 240 /* guest vce engine usage percentage. 0xffff means N/A. */ 241 uint32_t vce_enc_usage; 242 /* guest vce engine health percentage. 0xffff means N/A. */ 243 uint32_t vce_enc_health; 244 /* guest uvd engine usage percentage. 0xffff means N/A. */ 245 uint32_t uvd_enc_usage; 246 /* guest uvd engine usage percentage. 0xffff means N/A. */ 247 uint32_t uvd_enc_health; 248 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; 249 } __aligned(4); 250 251 struct amdgpu_virt_ras_err_handler_data { 252 /* point to bad page records array */ 253 struct eeprom_table_record *bps; 254 /* point to reserved bo array */ 255 struct amdgpu_bo **bps_bo; 256 /* the count of entries */ 257 int count; 258 /* last reserved entry's index + 1 */ 259 int last_reserved; 260 }; 261 262 struct amdgpu_virt_ras { 263 struct ratelimit_state ras_error_cnt_rs; 264 struct ratelimit_state ras_cper_dump_rs; 265 struct ratelimit_state ras_chk_criti_rs; 266 struct mutex ras_telemetry_mutex; 267 uint64_t cper_rptr; 268 }; 269 270 #define AMDGPU_VIRT_CAPS_LIST(X) X(AMDGPU_VIRT_CAP_POWER_LIMIT) 271 272 DECLARE_ATTR_CAP_CLASS(amdgpu_virt, AMDGPU_VIRT_CAPS_LIST); 273 274 struct amdgpu_virt_region { 275 uint32_t offset; 276 uint32_t size_kb; 277 }; 278 279 /* GPU virtualization */ 280 struct amdgpu_virt { 281 uint32_t caps; 282 struct amdgpu_bo *csa_obj; 283 void *csa_cpu_addr; 284 bool chained_ib_support; 285 uint32_t reg_val_offs; 286 struct amdgpu_irq_src ack_irq; 287 struct amdgpu_irq_src rcv_irq; 288 289 struct work_struct flr_work; 290 struct work_struct req_bad_pages_work; 291 struct work_struct handle_bad_pages_work; 292 293 struct amdgpu_mm_table mm_table; 294 const struct amdgpu_virt_ops *ops; 295 struct amdgpu_vf_error_buffer vf_errors; 296 struct amdgpu_virt_fw_reserve fw_reserve; 297 struct amdgpu_virt_caps virt_caps; 298 uint32_t gim_feature; 299 uint32_t reg_access_mode; 300 int req_init_data_ver; 301 bool tdr_debug; 302 struct amdgpu_virt_ras_err_handler_data *virt_eh_data; 303 bool ras_init_done; 304 uint32_t reg_access; 305 306 /* dynamic(v2) critical regions */ 307 struct amdgpu_virt_region init_data_header; 308 struct amdgpu_virt_region crit_regn; 309 struct amdgpu_virt_region crit_regn_tbl[AMD_SRIOV_MSG_MAX_TABLE_ID]; 310 bool is_dynamic_crit_regn_enabled; 311 312 /* vf2pf message */ 313 struct delayed_work vf2pf_work; 314 uint32_t vf2pf_update_interval_ms; 315 int vf2pf_update_retry_cnt; 316 317 /* multimedia bandwidth config */ 318 bool is_mm_bw_enabled; 319 uint32_t decode_max_dimension_pixels; 320 uint32_t decode_max_frame_pixels; 321 uint32_t encode_max_dimension_pixels; 322 uint32_t encode_max_frame_pixels; 323 324 /* the ucode id to signal the autoload */ 325 uint32_t autoload_ucode_id; 326 327 /* Spinlock to protect access to the RLCG register interface */ 328 spinlock_t rlcg_reg_lock; 329 330 struct mutex access_req_mutex; 331 332 union amd_sriov_ras_caps ras_en_caps; 333 union amd_sriov_ras_caps ras_telemetry_en_caps; 334 struct amdgpu_virt_ras ras; 335 struct amd_sriov_ras_telemetry_error_count count_cache; 336 337 /* hibernate and resume with different VF feature for xgmi enabled system */ 338 bool is_xgmi_node_migrate_enabled; 339 }; 340 341 struct amdgpu_video_codec_info; 342 343 #define amdgpu_sriov_enabled(adev) \ 344 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 345 346 #define amdgpu_sriov_vf(adev) \ 347 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 348 349 #define amdgpu_sriov_bios(adev) \ 350 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 351 352 #define amdgpu_sriov_runtime(adev) \ 353 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 354 355 #define amdgpu_sriov_fullaccess(adev) \ 356 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev))) 357 358 #define amdgpu_sriov_reg_indirect_en(adev) \ 359 (amdgpu_sriov_vf((adev)) && \ 360 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS))) 361 362 #define amdgpu_sriov_reg_indirect_ih(adev) \ 363 (amdgpu_sriov_vf((adev)) && \ 364 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN))) 365 366 #define amdgpu_sriov_reg_indirect_mmhub(adev) \ 367 (amdgpu_sriov_vf((adev)) && \ 368 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN))) 369 370 #define amdgpu_sriov_reg_indirect_gc(adev) \ 371 (amdgpu_sriov_vf((adev)) && \ 372 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN))) 373 374 #define amdgpu_sriov_reg_indirect_l1_tlb_cntl(adev) \ 375 (amdgpu_sriov_vf((adev)) && \ 376 ((adev)->virt.reg_access & (AMDGIM_FEATURE_L1_TLB_CNTL_PSP_EN))) 377 378 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \ 379 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev)) 380 381 #define amdgpu_sriov_reg_access_sq_config(adev) \ 382 (amdgpu_sriov_vf((adev)) && \ 383 ((adev)->virt.reg_access & (AMDGIM_FEATURE_REG_ACCESS_SQ_CONFIG))) 384 385 #define amdgpu_passthrough(adev) \ 386 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 387 388 #define amdgpu_sriov_vf_mmio_access_protection(adev) \ 389 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT) 390 391 #define amdgpu_sriov_ras_caps_en(adev) \ 392 ((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CAPS) 393 394 #define amdgpu_sriov_ras_telemetry_en(adev) \ 395 (((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_TELEMETRY) && (adev)->virt.fw_reserve.ras_telemetry) 396 397 #define amdgpu_sriov_ras_telemetry_block_en(adev, sriov_blk) \ 398 (amdgpu_sriov_ras_telemetry_en((adev)) && (adev)->virt.ras_telemetry_en_caps.all & BIT(sriov_blk)) 399 400 #define amdgpu_sriov_ras_cper_en(adev) \ 401 ((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CPER) 402 403 #define amdgpu_sriov_xgmi_ta_ext_peer_link_en(adev) \ 404 ((adev)->virt.gim_feature & AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK) 405 406 static inline bool is_virtual_machine(void) 407 { 408 #if defined(CONFIG_X86) 409 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 410 #elif defined(CONFIG_ARM64) 411 return !is_kernel_in_hyp_mode(); 412 #else 413 return false; 414 #endif 415 } 416 417 #define amdgpu_sriov_is_pp_one_vf(adev) \ 418 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 419 #define amdgpu_sriov_multi_vf_mode(adev) \ 420 (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 421 #define amdgpu_sriov_is_debug(adev) \ 422 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug) 423 #define amdgpu_sriov_is_normal(adev) \ 424 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug)) 425 #define amdgpu_sriov_is_av1_support(adev) \ 426 ((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT) 427 #define amdgpu_sriov_is_vcn_rb_decouple(adev) \ 428 ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE) 429 #define amdgpu_sriov_is_mes_info_enable(adev) \ 430 ((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE) 431 432 #define amdgpu_virt_xgmi_migrate_enabled(adev) \ 433 ((adev)->virt.is_xgmi_node_migrate_enabled && (adev)->gmc.xgmi.node_segment_size != 0) 434 435 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 436 void amdgpu_virt_init_setting(struct amdgpu_device *adev); 437 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 438 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 439 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 440 void amdgpu_virt_request_init_data(struct amdgpu_device *adev); 441 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev); 442 int amdgpu_virt_wait_reset(struct amdgpu_device *adev); 443 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); 444 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); 445 bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev); 446 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev); 447 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); 448 void amdgpu_virt_exchange_data(struct amdgpu_device *adev); 449 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); 450 void amdgpu_virt_init(struct amdgpu_device *adev); 451 452 int amdgpu_virt_init_critical_region(struct amdgpu_device *adev); 453 int amdgpu_virt_get_dynamic_data_info(struct amdgpu_device *adev, 454 int data_id, uint8_t *binary, u32 *size); 455 456 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); 457 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); 458 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); 459 460 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); 461 462 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 463 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 464 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size); 465 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 466 u32 offset, u32 value, 467 u32 acc_flags, u32 hwip, u32 xcc_id); 468 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 469 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id); 470 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, 471 uint32_t ucode_id); 472 void amdgpu_virt_pre_reset(struct amdgpu_device *adev); 473 void amdgpu_virt_post_reset(struct amdgpu_device *adev); 474 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev); 475 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 476 u32 acc_flags, u32 hwip, 477 bool write, u32 *rlcg_flag); 478 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id); 479 bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev); 480 int amdgpu_virt_req_ras_err_count(struct amdgpu_device *adev, enum amdgpu_ras_block block, 481 struct ras_err_data *err_data); 482 int amdgpu_virt_req_ras_cper_dump(struct amdgpu_device *adev, bool force_update); 483 int amdgpu_virt_ras_telemetry_post_reset(struct amdgpu_device *adev); 484 bool amdgpu_virt_ras_telemetry_block_en(struct amdgpu_device *adev, 485 enum amdgpu_ras_block block); 486 void amdgpu_virt_request_bad_pages(struct amdgpu_device *adev); 487 int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, bool *hit); 488 int amdgpu_virt_send_remote_ras_cmd(struct amdgpu_device *adev, 489 uint64_t buf, uint32_t buf_len); 490 #endif 491