1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Monk.liu@amd.com 23 */ 24 #ifndef AMDGPU_VIRT_H 25 #define AMDGPU_VIRT_H 26 27 #include "amdgv_sriovmsg.h" 28 29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 34 #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */ 35 36 /* flags for indirect register access path supported by rlcg for sriov */ 37 #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28) 38 #define AMDGPU_RLCG_GC_WRITE (0x0 << 28) 39 #define AMDGPU_RLCG_GC_READ (0x1 << 28) 40 #define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28) 41 42 /* error code for indirect register access path supported by rlcg for sriov */ 43 #define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000 44 #define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000 45 #define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000 46 47 #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF 48 #define AMDGPU_RLCG_SCRATCH1_ERROR_MASK 0xF000000 49 50 #define AMDGPU_RLCG_VFI_CMD__WR 0x0 51 #define AMDGPU_RLCG_VFI_CMD__RD 0x1 52 53 #define AMDGPU_RLCG_VFI_STAT__BUSY 0x0 54 #define AMDGPU_RLCG_VFI_STAT__DONE 0x1 55 #define AMDGPU_RLCG_VFI_STAT__INV_CMD 0x2 56 #define AMDGPU_RLCG_VFI_STAT__INV_ADDR 0x3 57 #define AMDGPU_RLCG_VFI_STAT__ERR 0xFF 58 59 /* all asic after AI use this offset */ 60 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 61 /* tonga/fiji use this offset */ 62 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 63 64 #define AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT 2 65 66 /* Signature used to validate the SR-IOV dynamic critical region init data header ("INDA") */ 67 #define AMDGPU_SRIOV_CRIT_DATA_SIGNATURE "INDA" 68 #define AMDGPU_SRIOV_CRIT_DATA_SIG_LEN 4 69 70 #define IS_SRIOV_CRIT_REGN_ENTRY_VALID(hdr, id) ((hdr)->valid_tables & (1 << (id))) 71 72 enum amdgpu_sriov_vf_mode { 73 SRIOV_VF_MODE_BARE_METAL = 0, 74 SRIOV_VF_MODE_ONE_VF, 75 SRIOV_VF_MODE_MULTI_VF, 76 }; 77 78 struct amdgpu_mm_table { 79 struct amdgpu_bo *bo; 80 uint32_t *cpu_addr; 81 uint64_t gpu_addr; 82 }; 83 84 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16 85 86 /* struct error_entry - amdgpu VF error information. */ 87 struct amdgpu_vf_error_buffer { 88 struct mutex lock; 89 int read_count; 90 int write_count; 91 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; 92 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE]; 93 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; 94 }; 95 96 enum idh_request; 97 98 /** 99 * struct amdgpu_virt_ops - amdgpu device virt operations 100 */ 101 struct amdgpu_virt_ops { 102 int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 103 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 104 int (*req_init_data)(struct amdgpu_device *adev); 105 int (*reset_gpu)(struct amdgpu_device *adev); 106 void (*ready_to_reset)(struct amdgpu_device *adev); 107 int (*wait_reset)(struct amdgpu_device *adev); 108 void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req, 109 u32 data1, u32 data2, u32 data3); 110 void (*ras_poison_handler)(struct amdgpu_device *adev, 111 enum amdgpu_ras_block block); 112 bool (*rcvd_ras_intr)(struct amdgpu_device *adev); 113 int (*req_ras_err_count)(struct amdgpu_device *adev); 114 int (*req_ras_cper_dump)(struct amdgpu_device *adev, u64 vf_rptr); 115 int (*req_bad_pages)(struct amdgpu_device *adev); 116 int (*req_ras_chk_criti)(struct amdgpu_device *adev, u64 addr); 117 int (*req_remote_ras_cmd)(struct amdgpu_device *adev, 118 u32 param1, u32 param2, u32 param3); 119 }; 120 121 /* 122 * Firmware Reserve Frame buffer 123 */ 124 struct amdgpu_virt_fw_reserve { 125 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; 126 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; 127 void *ras_telemetry; 128 unsigned int checksum_key; 129 }; 130 131 /* 132 * Legacy GIM header 133 * 134 * Defination between PF and VF 135 * Structures forcibly aligned to 4 to keep the same style as PF. 136 */ 137 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024) 138 139 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \ 140 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2)) 141 142 enum AMDGIM_FEATURE_FLAG { 143 /* GIM supports feature of Error log collecting */ 144 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, 145 /* GIM supports feature of loading uCodes */ 146 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, 147 /* VRAM LOST by GIM */ 148 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, 149 /* MM bandwidth */ 150 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8, 151 /* PP ONE VF MODE in GIM */ 152 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4), 153 /* Indirect Reg Access enabled */ 154 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5), 155 /* AV1 Support MODE*/ 156 AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6), 157 /* VCN RB decouple */ 158 AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7), 159 /* MES info */ 160 AMDGIM_FEATURE_MES_INFO_ENABLE = (1 << 8), 161 AMDGIM_FEATURE_RAS_CAPS = (1 << 9), 162 AMDGIM_FEATURE_RAS_TELEMETRY = (1 << 10), 163 AMDGIM_FEATURE_RAS_CPER = (1 << 11), 164 AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK = (1 << 12), 165 AMDGIM_FEATURE_XGMI_CONNECTED_TO_CPU = (1 << 13), 166 AMDGIM_FEATURE_PTL_SUPPORT = (1 << 14), 167 AMDGIM_FEATURE_UNITID_SUPPORT = (1 << 15), 168 }; 169 170 enum AMDGIM_REG_ACCESS_FLAG { 171 /* Use PSP to program IH_RB_CNTL */ 172 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0), 173 /* Use RLC to program MMHUB regs */ 174 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1), 175 /* Use RLC to program GC regs */ 176 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2), 177 /* Use PSP to program L1_TLB_CNTL */ 178 AMDGIM_FEATURE_L1_TLB_CNTL_PSP_EN = (1 << 3), 179 /* Use RLCG to program SQ_CONFIG1 */ 180 AMDGIM_FEATURE_REG_ACCESS_SQ_CONFIG = (1 << 4), 181 }; 182 183 struct amdgim_pf2vf_info_v1 { 184 /* header contains size and version */ 185 struct amd_sriov_msg_pf2vf_info_header header; 186 /* max_width * max_height */ 187 unsigned int uvd_enc_max_pixels_count; 188 /* 16x16 pixels/sec, codec independent */ 189 unsigned int uvd_enc_max_bandwidth; 190 /* max_width * max_height */ 191 unsigned int vce_enc_max_pixels_count; 192 /* 16x16 pixels/sec, codec independent */ 193 unsigned int vce_enc_max_bandwidth; 194 /* MEC FW position in kb from the start of visible frame buffer */ 195 unsigned int mecfw_kboffset; 196 /* The features flags of the GIM driver supports. */ 197 unsigned int feature_flags; 198 /* use private key from mailbox 2 to create chueksum */ 199 unsigned int checksum; 200 } __aligned(4); 201 202 struct amdgim_vf2pf_info_v1 { 203 /* header contains size and version */ 204 struct amd_sriov_msg_vf2pf_info_header header; 205 /* driver version */ 206 char driver_version[64]; 207 /* driver certification, 1=WHQL, 0=None */ 208 unsigned int driver_cert; 209 /* guest OS type and version: need a define */ 210 unsigned int os_info; 211 /* in the unit of 1M */ 212 unsigned int fb_usage; 213 /* guest gfx engine usage percentage */ 214 unsigned int gfx_usage; 215 /* guest gfx engine health percentage */ 216 unsigned int gfx_health; 217 /* guest compute engine usage percentage */ 218 unsigned int compute_usage; 219 /* guest compute engine health percentage */ 220 unsigned int compute_health; 221 /* guest vce engine usage percentage. 0xffff means N/A. */ 222 unsigned int vce_enc_usage; 223 /* guest vce engine health percentage. 0xffff means N/A. */ 224 unsigned int vce_enc_health; 225 /* guest uvd engine usage percentage. 0xffff means N/A. */ 226 unsigned int uvd_enc_usage; 227 /* guest uvd engine usage percentage. 0xffff means N/A. */ 228 unsigned int uvd_enc_health; 229 unsigned int checksum; 230 } __aligned(4); 231 232 struct amdgim_vf2pf_info_v2 { 233 /* header contains size and version */ 234 struct amd_sriov_msg_vf2pf_info_header header; 235 uint32_t checksum; 236 /* driver version */ 237 uint8_t driver_version[64]; 238 /* driver certification, 1=WHQL, 0=None */ 239 uint32_t driver_cert; 240 /* guest OS type and version: need a define */ 241 uint32_t os_info; 242 /* in the unit of 1M */ 243 uint32_t fb_usage; 244 /* guest gfx engine usage percentage */ 245 uint32_t gfx_usage; 246 /* guest gfx engine health percentage */ 247 uint32_t gfx_health; 248 /* guest compute engine usage percentage */ 249 uint32_t compute_usage; 250 /* guest compute engine health percentage */ 251 uint32_t compute_health; 252 /* guest vce engine usage percentage. 0xffff means N/A. */ 253 uint32_t vce_enc_usage; 254 /* guest vce engine health percentage. 0xffff means N/A. */ 255 uint32_t vce_enc_health; 256 /* guest uvd engine usage percentage. 0xffff means N/A. */ 257 uint32_t uvd_enc_usage; 258 /* guest uvd engine usage percentage. 0xffff means N/A. */ 259 uint32_t uvd_enc_health; 260 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; 261 } __aligned(4); 262 263 struct amdgpu_virt_ras_err_handler_data { 264 /* point to bad page records array */ 265 struct eeprom_table_record *bps; 266 /* point to reserved bo array */ 267 struct amdgpu_bo **bps_bo; 268 /* the count of entries */ 269 int count; 270 /* last reserved entry's index + 1 */ 271 int last_reserved; 272 }; 273 274 struct amdgpu_virt_ras { 275 struct ratelimit_state ras_error_cnt_rs; 276 struct ratelimit_state ras_cper_dump_rs; 277 struct ratelimit_state ras_chk_criti_rs; 278 struct mutex ras_telemetry_mutex; 279 uint64_t cper_rptr; 280 }; 281 282 #define AMDGPU_VIRT_CAPS_LIST(X) X(AMDGPU_VIRT_CAP_POWER_LIMIT) 283 284 DECLARE_ATTR_CAP_CLASS(amdgpu_virt, AMDGPU_VIRT_CAPS_LIST); 285 286 struct amdgpu_virt_region { 287 uint32_t offset; 288 uint32_t size_kb; 289 }; 290 291 /* GPU virtualization */ 292 struct amdgpu_virt { 293 uint32_t caps; 294 struct amdgpu_bo *csa_obj; 295 void *csa_cpu_addr; 296 bool chained_ib_support; 297 uint32_t reg_val_offs; 298 struct amdgpu_irq_src ack_irq; 299 struct amdgpu_irq_src rcv_irq; 300 301 struct work_struct flr_work; 302 struct work_struct req_bad_pages_work; 303 struct work_struct handle_bad_pages_work; 304 305 struct amdgpu_mm_table mm_table; 306 const struct amdgpu_virt_ops *ops; 307 struct amdgpu_vf_error_buffer vf_errors; 308 struct amdgpu_virt_fw_reserve fw_reserve; 309 struct amdgpu_virt_caps virt_caps; 310 uint32_t gim_feature; 311 uint32_t reg_access_mode; 312 int req_init_data_ver; 313 bool tdr_debug; 314 struct amdgpu_virt_ras_err_handler_data *virt_eh_data; 315 bool ras_init_done; 316 uint32_t reg_access; 317 318 /* dynamic(v2) critical regions */ 319 struct amdgpu_virt_region init_data_header; 320 struct amdgpu_virt_region crit_regn; 321 struct amdgpu_virt_region crit_regn_tbl[AMD_SRIOV_MSG_MAX_TABLE_ID]; 322 bool is_dynamic_crit_regn_enabled; 323 324 /* vf2pf message */ 325 struct delayed_work vf2pf_work; 326 uint32_t vf2pf_update_interval_ms; 327 int vf2pf_update_retry_cnt; 328 329 /* multimedia bandwidth config */ 330 bool is_mm_bw_enabled; 331 uint32_t decode_max_dimension_pixels; 332 uint32_t decode_max_frame_pixels; 333 uint32_t encode_max_dimension_pixels; 334 uint32_t encode_max_frame_pixels; 335 336 /* the ucode id to signal the autoload */ 337 uint32_t autoload_ucode_id; 338 339 /* Spinlock to protect access to the RLCG register interface */ 340 spinlock_t rlcg_reg_lock; 341 342 struct mutex access_req_mutex; 343 344 union amd_sriov_ras_caps ras_en_caps; 345 union amd_sriov_ras_caps ras_telemetry_en_caps; 346 struct amdgpu_virt_ras ras; 347 struct amd_sriov_ras_telemetry_error_count count_cache; 348 349 /* hibernate and resume with different VF feature for xgmi enabled system */ 350 bool is_xgmi_node_migrate_enabled; 351 }; 352 353 struct amdgpu_video_codec_info; 354 355 #define amdgpu_sriov_enabled(adev) \ 356 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 357 358 #define amdgpu_sriov_vf(adev) \ 359 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 360 361 #define amdgpu_sriov_bios(adev) \ 362 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 363 364 #define amdgpu_sriov_runtime(adev) \ 365 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 366 367 #define amdgpu_sriov_fullaccess(adev) \ 368 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev))) 369 370 #define amdgpu_sriov_reg_indirect_en(adev) \ 371 (amdgpu_sriov_vf((adev)) && \ 372 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS))) 373 374 #define amdgpu_sriov_reg_indirect_ih(adev) \ 375 (amdgpu_sriov_vf((adev)) && \ 376 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN))) 377 378 #define amdgpu_sriov_reg_indirect_mmhub(adev) \ 379 (amdgpu_sriov_vf((adev)) && \ 380 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN))) 381 382 #define amdgpu_sriov_reg_indirect_gc(adev) \ 383 (amdgpu_sriov_vf((adev)) && \ 384 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN))) 385 386 #define amdgpu_sriov_reg_indirect_l1_tlb_cntl(adev) \ 387 (amdgpu_sriov_vf((adev)) && \ 388 ((adev)->virt.reg_access & (AMDGIM_FEATURE_L1_TLB_CNTL_PSP_EN))) 389 390 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \ 391 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev)) 392 393 #define amdgpu_sriov_reg_access_sq_config(adev) \ 394 (amdgpu_sriov_vf((adev)) && \ 395 ((adev)->virt.reg_access & (AMDGIM_FEATURE_REG_ACCESS_SQ_CONFIG))) 396 397 #define amdgpu_passthrough(adev) \ 398 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 399 400 #define amdgpu_sriov_vf_mmio_access_protection(adev) \ 401 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT) 402 403 #define amdgpu_sriov_ras_caps_en(adev) \ 404 ((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CAPS) 405 406 #define amdgpu_sriov_ras_telemetry_en(adev) \ 407 (((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_TELEMETRY) && (adev)->virt.fw_reserve.ras_telemetry) 408 409 #define amdgpu_sriov_ras_telemetry_block_en(adev, sriov_blk) \ 410 (amdgpu_sriov_ras_telemetry_en((adev)) && (adev)->virt.ras_telemetry_en_caps.all & BIT(sriov_blk)) 411 412 #define amdgpu_sriov_ras_cper_en(adev) \ 413 ((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CPER) 414 415 #define amdgpu_sriov_xgmi_ta_ext_peer_link_en(adev) \ 416 ((adev)->virt.gim_feature & AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK) 417 418 #define amdgpu_sriov_xgmi_connected_to_cpu(adev) \ 419 ((adev)->virt.gim_feature & AMDGIM_FEATURE_XGMI_CONNECTED_TO_CPU) 420 421 static inline bool is_virtual_machine(void) 422 { 423 #if defined(CONFIG_X86) 424 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 425 #elif defined(CONFIG_ARM64) 426 return !is_kernel_in_hyp_mode(); 427 #else 428 return false; 429 #endif 430 } 431 432 #define amdgpu_sriov_is_pp_one_vf(adev) \ 433 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 434 #define amdgpu_sriov_multi_vf_mode(adev) \ 435 (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 436 #define amdgpu_sriov_is_debug(adev) \ 437 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug) 438 #define amdgpu_sriov_is_normal(adev) \ 439 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug)) 440 #define amdgpu_sriov_is_av1_support(adev) \ 441 ((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT) 442 #define amdgpu_sriov_is_vcn_rb_decouple(adev) \ 443 ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE) 444 #define amdgpu_sriov_is_mes_info_enable(adev) \ 445 ((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE) 446 #define amdgpu_sriov_is_unitid_support(adev) \ 447 ((adev)->virt.gim_feature & AMDGIM_FEATURE_UNITID_SUPPORT) 448 449 #define amdgpu_virt_xgmi_migrate_enabled(adev) \ 450 ((adev)->virt.is_xgmi_node_migrate_enabled && (adev)->gmc.xgmi.node_segment_size != 0) 451 452 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 453 void amdgpu_virt_init_setting(struct amdgpu_device *adev); 454 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 455 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 456 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 457 void amdgpu_virt_request_init_data(struct amdgpu_device *adev); 458 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev); 459 int amdgpu_virt_wait_reset(struct amdgpu_device *adev); 460 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); 461 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); 462 bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev); 463 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev); 464 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); 465 void amdgpu_virt_exchange_data(struct amdgpu_device *adev); 466 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); 467 void amdgpu_virt_init(struct amdgpu_device *adev); 468 469 int amdgpu_virt_init_critical_region(struct amdgpu_device *adev); 470 int amdgpu_virt_get_dynamic_data_info(struct amdgpu_device *adev, 471 int data_id, uint8_t *binary, u32 *size); 472 473 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); 474 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); 475 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); 476 477 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); 478 479 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 480 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 481 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size); 482 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 483 u32 offset, u32 value, 484 u32 acc_flags, u32 hwip, u32 xcc_id); 485 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 486 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id); 487 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, 488 uint32_t ucode_id); 489 void amdgpu_virt_pre_reset(struct amdgpu_device *adev); 490 void amdgpu_virt_post_reset(struct amdgpu_device *adev); 491 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev); 492 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 493 u32 acc_flags, u32 hwip, 494 bool write, u32 *rlcg_flag); 495 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id); 496 bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev); 497 int amdgpu_virt_req_ras_err_count(struct amdgpu_device *adev, enum amdgpu_ras_block block, 498 struct ras_err_data *err_data); 499 int amdgpu_virt_req_ras_cper_dump(struct amdgpu_device *adev, bool force_update); 500 int amdgpu_virt_ras_telemetry_post_reset(struct amdgpu_device *adev); 501 bool amdgpu_virt_ras_telemetry_block_en(struct amdgpu_device *adev, 502 enum amdgpu_ras_block block); 503 void amdgpu_virt_request_bad_pages(struct amdgpu_device *adev); 504 int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, bool *hit); 505 int amdgpu_virt_send_remote_ras_cmd(struct amdgpu_device *adev, 506 uint64_t buf, uint32_t buf_len); 507 #endif 508