1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Monk.liu@amd.com 23 */ 24 #ifndef AMDGPU_VIRT_H 25 #define AMDGPU_VIRT_H 26 27 #include "amdgv_sriovmsg.h" 28 29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 34 #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */ 35 36 /* flags for indirect register access path supported by rlcg for sriov */ 37 #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28) 38 #define AMDGPU_RLCG_GC_WRITE (0x0 << 28) 39 #define AMDGPU_RLCG_GC_READ (0x1 << 28) 40 #define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28) 41 42 /* error code for indirect register access path supported by rlcg for sriov */ 43 #define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000 44 #define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000 45 #define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000 46 47 #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF 48 49 /* all asic after AI use this offset */ 50 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 51 /* tonga/fiji use this offset */ 52 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 53 54 enum amdgpu_sriov_vf_mode { 55 SRIOV_VF_MODE_BARE_METAL = 0, 56 SRIOV_VF_MODE_ONE_VF, 57 SRIOV_VF_MODE_MULTI_VF, 58 }; 59 60 struct amdgpu_mm_table { 61 struct amdgpu_bo *bo; 62 uint32_t *cpu_addr; 63 uint64_t gpu_addr; 64 }; 65 66 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16 67 68 /* struct error_entry - amdgpu VF error information. */ 69 struct amdgpu_vf_error_buffer { 70 struct mutex lock; 71 int read_count; 72 int write_count; 73 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; 74 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE]; 75 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; 76 }; 77 78 enum idh_request; 79 80 /** 81 * struct amdgpu_virt_ops - amdgpu device virt operations 82 */ 83 struct amdgpu_virt_ops { 84 int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 85 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 86 int (*req_init_data)(struct amdgpu_device *adev); 87 int (*reset_gpu)(struct amdgpu_device *adev); 88 int (*wait_reset)(struct amdgpu_device *adev); 89 void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req, 90 u32 data1, u32 data2, u32 data3); 91 }; 92 93 /* 94 * Firmware Reserve Frame buffer 95 */ 96 struct amdgpu_virt_fw_reserve { 97 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; 98 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; 99 unsigned int checksum_key; 100 }; 101 102 /* 103 * Legacy GIM header 104 * 105 * Defination between PF and VF 106 * Structures forcibly aligned to 4 to keep the same style as PF. 107 */ 108 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024) 109 110 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \ 111 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2)) 112 113 enum AMDGIM_FEATURE_FLAG { 114 /* GIM supports feature of Error log collecting */ 115 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, 116 /* GIM supports feature of loading uCodes */ 117 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, 118 /* VRAM LOST by GIM */ 119 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, 120 /* MM bandwidth */ 121 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8, 122 /* PP ONE VF MODE in GIM */ 123 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4), 124 /* Indirect Reg Access enabled */ 125 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5), 126 }; 127 128 enum AMDGIM_REG_ACCESS_FLAG { 129 /* Use PSP to program IH_RB_CNTL */ 130 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0), 131 /* Use RLC to program MMHUB regs */ 132 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1), 133 /* Use RLC to program GC regs */ 134 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2), 135 }; 136 137 struct amdgim_pf2vf_info_v1 { 138 /* header contains size and version */ 139 struct amd_sriov_msg_pf2vf_info_header header; 140 /* max_width * max_height */ 141 unsigned int uvd_enc_max_pixels_count; 142 /* 16x16 pixels/sec, codec independent */ 143 unsigned int uvd_enc_max_bandwidth; 144 /* max_width * max_height */ 145 unsigned int vce_enc_max_pixels_count; 146 /* 16x16 pixels/sec, codec independent */ 147 unsigned int vce_enc_max_bandwidth; 148 /* MEC FW position in kb from the start of visible frame buffer */ 149 unsigned int mecfw_kboffset; 150 /* The features flags of the GIM driver supports. */ 151 unsigned int feature_flags; 152 /* use private key from mailbox 2 to create chueksum */ 153 unsigned int checksum; 154 } __aligned(4); 155 156 struct amdgim_vf2pf_info_v1 { 157 /* header contains size and version */ 158 struct amd_sriov_msg_vf2pf_info_header header; 159 /* driver version */ 160 char driver_version[64]; 161 /* driver certification, 1=WHQL, 0=None */ 162 unsigned int driver_cert; 163 /* guest OS type and version: need a define */ 164 unsigned int os_info; 165 /* in the unit of 1M */ 166 unsigned int fb_usage; 167 /* guest gfx engine usage percentage */ 168 unsigned int gfx_usage; 169 /* guest gfx engine health percentage */ 170 unsigned int gfx_health; 171 /* guest compute engine usage percentage */ 172 unsigned int compute_usage; 173 /* guest compute engine health percentage */ 174 unsigned int compute_health; 175 /* guest vce engine usage percentage. 0xffff means N/A. */ 176 unsigned int vce_enc_usage; 177 /* guest vce engine health percentage. 0xffff means N/A. */ 178 unsigned int vce_enc_health; 179 /* guest uvd engine usage percentage. 0xffff means N/A. */ 180 unsigned int uvd_enc_usage; 181 /* guest uvd engine usage percentage. 0xffff means N/A. */ 182 unsigned int uvd_enc_health; 183 unsigned int checksum; 184 } __aligned(4); 185 186 struct amdgim_vf2pf_info_v2 { 187 /* header contains size and version */ 188 struct amd_sriov_msg_vf2pf_info_header header; 189 uint32_t checksum; 190 /* driver version */ 191 uint8_t driver_version[64]; 192 /* driver certification, 1=WHQL, 0=None */ 193 uint32_t driver_cert; 194 /* guest OS type and version: need a define */ 195 uint32_t os_info; 196 /* in the unit of 1M */ 197 uint32_t fb_usage; 198 /* guest gfx engine usage percentage */ 199 uint32_t gfx_usage; 200 /* guest gfx engine health percentage */ 201 uint32_t gfx_health; 202 /* guest compute engine usage percentage */ 203 uint32_t compute_usage; 204 /* guest compute engine health percentage */ 205 uint32_t compute_health; 206 /* guest vce engine usage percentage. 0xffff means N/A. */ 207 uint32_t vce_enc_usage; 208 /* guest vce engine health percentage. 0xffff means N/A. */ 209 uint32_t vce_enc_health; 210 /* guest uvd engine usage percentage. 0xffff means N/A. */ 211 uint32_t uvd_enc_usage; 212 /* guest uvd engine usage percentage. 0xffff means N/A. */ 213 uint32_t uvd_enc_health; 214 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; 215 } __aligned(4); 216 217 struct amdgpu_virt_ras_err_handler_data { 218 /* point to bad page records array */ 219 struct eeprom_table_record *bps; 220 /* point to reserved bo array */ 221 struct amdgpu_bo **bps_bo; 222 /* the count of entries */ 223 int count; 224 /* last reserved entry's index + 1 */ 225 int last_reserved; 226 }; 227 228 /* GPU virtualization */ 229 struct amdgpu_virt { 230 uint32_t caps; 231 struct amdgpu_bo *csa_obj; 232 void *csa_cpu_addr; 233 bool chained_ib_support; 234 uint32_t reg_val_offs; 235 struct amdgpu_irq_src ack_irq; 236 struct amdgpu_irq_src rcv_irq; 237 struct work_struct flr_work; 238 struct amdgpu_mm_table mm_table; 239 const struct amdgpu_virt_ops *ops; 240 struct amdgpu_vf_error_buffer vf_errors; 241 struct amdgpu_virt_fw_reserve fw_reserve; 242 uint32_t gim_feature; 243 uint32_t reg_access_mode; 244 int req_init_data_ver; 245 bool tdr_debug; 246 struct amdgpu_virt_ras_err_handler_data *virt_eh_data; 247 bool ras_init_done; 248 uint32_t reg_access; 249 250 /* vf2pf message */ 251 struct delayed_work vf2pf_work; 252 uint32_t vf2pf_update_interval_ms; 253 254 /* multimedia bandwidth config */ 255 bool is_mm_bw_enabled; 256 uint32_t decode_max_dimension_pixels; 257 uint32_t decode_max_frame_pixels; 258 uint32_t encode_max_dimension_pixels; 259 uint32_t encode_max_frame_pixels; 260 261 /* the ucode id to signal the autoload */ 262 uint32_t autoload_ucode_id; 263 }; 264 265 struct amdgpu_video_codec_info; 266 267 #define amdgpu_sriov_enabled(adev) \ 268 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 269 270 #define amdgpu_sriov_vf(adev) \ 271 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 272 273 #define amdgpu_sriov_bios(adev) \ 274 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 275 276 #define amdgpu_sriov_runtime(adev) \ 277 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 278 279 #define amdgpu_sriov_fullaccess(adev) \ 280 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev))) 281 282 #define amdgpu_sriov_reg_indirect_en(adev) \ 283 (amdgpu_sriov_vf((adev)) && \ 284 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS))) 285 286 #define amdgpu_sriov_reg_indirect_ih(adev) \ 287 (amdgpu_sriov_vf((adev)) && \ 288 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN))) 289 290 #define amdgpu_sriov_reg_indirect_mmhub(adev) \ 291 (amdgpu_sriov_vf((adev)) && \ 292 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN))) 293 294 #define amdgpu_sriov_reg_indirect_gc(adev) \ 295 (amdgpu_sriov_vf((adev)) && \ 296 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN))) 297 298 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \ 299 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev)) 300 301 #define amdgpu_passthrough(adev) \ 302 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 303 304 #define amdgpu_sriov_vf_mmio_access_protection(adev) \ 305 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT) 306 307 static inline bool is_virtual_machine(void) 308 { 309 #if defined(CONFIG_X86) 310 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 311 #elif defined(CONFIG_ARM64) 312 return !is_kernel_in_hyp_mode(); 313 #else 314 return false; 315 #endif 316 } 317 318 #define amdgpu_sriov_is_pp_one_vf(adev) \ 319 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 320 #define amdgpu_sriov_is_debug(adev) \ 321 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug) 322 #define amdgpu_sriov_is_normal(adev) \ 323 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug)) 324 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 325 void amdgpu_virt_init_setting(struct amdgpu_device *adev); 326 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, 327 uint32_t reg0, uint32_t rreg1, 328 uint32_t ref, uint32_t mask); 329 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 330 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 331 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 332 void amdgpu_virt_request_init_data(struct amdgpu_device *adev); 333 int amdgpu_virt_wait_reset(struct amdgpu_device *adev); 334 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); 335 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); 336 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev); 337 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); 338 void amdgpu_virt_exchange_data(struct amdgpu_device *adev); 339 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); 340 void amdgpu_detect_virtualization(struct amdgpu_device *adev); 341 342 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); 343 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); 344 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); 345 346 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); 347 348 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 349 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 350 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size); 351 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 352 u32 offset, u32 value, 353 u32 acc_flags, u32 hwip); 354 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 355 u32 offset, u32 acc_flags, u32 hwip); 356 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, 357 uint32_t ucode_id); 358 #endif 359