1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Monk.liu@amd.com 23 */ 24 #ifndef AMDGPU_VIRT_H 25 #define AMDGPU_VIRT_H 26 27 #include "amdgv_sriovmsg.h" 28 29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 34 #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */ 35 36 /* flags for indirect register access path supported by rlcg for sriov */ 37 #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28) 38 #define AMDGPU_RLCG_GC_WRITE (0x0 << 28) 39 #define AMDGPU_RLCG_GC_READ (0x1 << 28) 40 #define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28) 41 42 /* error code for indirect register access path supported by rlcg for sriov */ 43 #define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000 44 #define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000 45 #define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000 46 47 #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF 48 #define AMDGPU_RLCG_SCRATCH1_ERROR_MASK 0xF000000 49 50 /* all asic after AI use this offset */ 51 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 52 /* tonga/fiji use this offset */ 53 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 54 55 #define AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT 2 56 57 enum amdgpu_sriov_vf_mode { 58 SRIOV_VF_MODE_BARE_METAL = 0, 59 SRIOV_VF_MODE_ONE_VF, 60 SRIOV_VF_MODE_MULTI_VF, 61 }; 62 63 struct amdgpu_mm_table { 64 struct amdgpu_bo *bo; 65 uint32_t *cpu_addr; 66 uint64_t gpu_addr; 67 }; 68 69 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16 70 71 /* struct error_entry - amdgpu VF error information. */ 72 struct amdgpu_vf_error_buffer { 73 struct mutex lock; 74 int read_count; 75 int write_count; 76 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; 77 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE]; 78 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; 79 }; 80 81 enum idh_request; 82 83 /** 84 * struct amdgpu_virt_ops - amdgpu device virt operations 85 */ 86 struct amdgpu_virt_ops { 87 int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 88 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 89 int (*req_init_data)(struct amdgpu_device *adev); 90 int (*reset_gpu)(struct amdgpu_device *adev); 91 void (*ready_to_reset)(struct amdgpu_device *adev); 92 int (*wait_reset)(struct amdgpu_device *adev); 93 void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req, 94 u32 data1, u32 data2, u32 data3); 95 void (*ras_poison_handler)(struct amdgpu_device *adev, 96 enum amdgpu_ras_block block); 97 bool (*rcvd_ras_intr)(struct amdgpu_device *adev); 98 }; 99 100 /* 101 * Firmware Reserve Frame buffer 102 */ 103 struct amdgpu_virt_fw_reserve { 104 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; 105 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; 106 unsigned int checksum_key; 107 }; 108 109 /* 110 * Legacy GIM header 111 * 112 * Defination between PF and VF 113 * Structures forcibly aligned to 4 to keep the same style as PF. 114 */ 115 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024) 116 117 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \ 118 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2)) 119 120 enum AMDGIM_FEATURE_FLAG { 121 /* GIM supports feature of Error log collecting */ 122 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, 123 /* GIM supports feature of loading uCodes */ 124 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, 125 /* VRAM LOST by GIM */ 126 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, 127 /* MM bandwidth */ 128 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8, 129 /* PP ONE VF MODE in GIM */ 130 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4), 131 /* Indirect Reg Access enabled */ 132 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5), 133 /* AV1 Support MODE*/ 134 AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6), 135 /* VCN RB decouple */ 136 AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7), 137 /* MES info */ 138 AMDGIM_FEATURE_MES_INFO_ENABLE = (1 << 8), 139 }; 140 141 enum AMDGIM_REG_ACCESS_FLAG { 142 /* Use PSP to program IH_RB_CNTL */ 143 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0), 144 /* Use RLC to program MMHUB regs */ 145 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1), 146 /* Use RLC to program GC regs */ 147 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2), 148 }; 149 150 struct amdgim_pf2vf_info_v1 { 151 /* header contains size and version */ 152 struct amd_sriov_msg_pf2vf_info_header header; 153 /* max_width * max_height */ 154 unsigned int uvd_enc_max_pixels_count; 155 /* 16x16 pixels/sec, codec independent */ 156 unsigned int uvd_enc_max_bandwidth; 157 /* max_width * max_height */ 158 unsigned int vce_enc_max_pixels_count; 159 /* 16x16 pixels/sec, codec independent */ 160 unsigned int vce_enc_max_bandwidth; 161 /* MEC FW position in kb from the start of visible frame buffer */ 162 unsigned int mecfw_kboffset; 163 /* The features flags of the GIM driver supports. */ 164 unsigned int feature_flags; 165 /* use private key from mailbox 2 to create chueksum */ 166 unsigned int checksum; 167 } __aligned(4); 168 169 struct amdgim_vf2pf_info_v1 { 170 /* header contains size and version */ 171 struct amd_sriov_msg_vf2pf_info_header header; 172 /* driver version */ 173 char driver_version[64]; 174 /* driver certification, 1=WHQL, 0=None */ 175 unsigned int driver_cert; 176 /* guest OS type and version: need a define */ 177 unsigned int os_info; 178 /* in the unit of 1M */ 179 unsigned int fb_usage; 180 /* guest gfx engine usage percentage */ 181 unsigned int gfx_usage; 182 /* guest gfx engine health percentage */ 183 unsigned int gfx_health; 184 /* guest compute engine usage percentage */ 185 unsigned int compute_usage; 186 /* guest compute engine health percentage */ 187 unsigned int compute_health; 188 /* guest vce engine usage percentage. 0xffff means N/A. */ 189 unsigned int vce_enc_usage; 190 /* guest vce engine health percentage. 0xffff means N/A. */ 191 unsigned int vce_enc_health; 192 /* guest uvd engine usage percentage. 0xffff means N/A. */ 193 unsigned int uvd_enc_usage; 194 /* guest uvd engine usage percentage. 0xffff means N/A. */ 195 unsigned int uvd_enc_health; 196 unsigned int checksum; 197 } __aligned(4); 198 199 struct amdgim_vf2pf_info_v2 { 200 /* header contains size and version */ 201 struct amd_sriov_msg_vf2pf_info_header header; 202 uint32_t checksum; 203 /* driver version */ 204 uint8_t driver_version[64]; 205 /* driver certification, 1=WHQL, 0=None */ 206 uint32_t driver_cert; 207 /* guest OS type and version: need a define */ 208 uint32_t os_info; 209 /* in the unit of 1M */ 210 uint32_t fb_usage; 211 /* guest gfx engine usage percentage */ 212 uint32_t gfx_usage; 213 /* guest gfx engine health percentage */ 214 uint32_t gfx_health; 215 /* guest compute engine usage percentage */ 216 uint32_t compute_usage; 217 /* guest compute engine health percentage */ 218 uint32_t compute_health; 219 /* guest vce engine usage percentage. 0xffff means N/A. */ 220 uint32_t vce_enc_usage; 221 /* guest vce engine health percentage. 0xffff means N/A. */ 222 uint32_t vce_enc_health; 223 /* guest uvd engine usage percentage. 0xffff means N/A. */ 224 uint32_t uvd_enc_usage; 225 /* guest uvd engine usage percentage. 0xffff means N/A. */ 226 uint32_t uvd_enc_health; 227 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; 228 } __aligned(4); 229 230 struct amdgpu_virt_ras_err_handler_data { 231 /* point to bad page records array */ 232 struct eeprom_table_record *bps; 233 /* point to reserved bo array */ 234 struct amdgpu_bo **bps_bo; 235 /* the count of entries */ 236 int count; 237 /* last reserved entry's index + 1 */ 238 int last_reserved; 239 }; 240 241 /* GPU virtualization */ 242 struct amdgpu_virt { 243 uint32_t caps; 244 struct amdgpu_bo *csa_obj; 245 void *csa_cpu_addr; 246 bool chained_ib_support; 247 uint32_t reg_val_offs; 248 struct amdgpu_irq_src ack_irq; 249 struct amdgpu_irq_src rcv_irq; 250 struct work_struct flr_work; 251 struct amdgpu_mm_table mm_table; 252 const struct amdgpu_virt_ops *ops; 253 struct amdgpu_vf_error_buffer vf_errors; 254 struct amdgpu_virt_fw_reserve fw_reserve; 255 uint32_t gim_feature; 256 uint32_t reg_access_mode; 257 int req_init_data_ver; 258 bool tdr_debug; 259 struct amdgpu_virt_ras_err_handler_data *virt_eh_data; 260 bool ras_init_done; 261 uint32_t reg_access; 262 263 /* vf2pf message */ 264 struct delayed_work vf2pf_work; 265 uint32_t vf2pf_update_interval_ms; 266 int vf2pf_update_retry_cnt; 267 268 /* multimedia bandwidth config */ 269 bool is_mm_bw_enabled; 270 uint32_t decode_max_dimension_pixels; 271 uint32_t decode_max_frame_pixels; 272 uint32_t encode_max_dimension_pixels; 273 uint32_t encode_max_frame_pixels; 274 275 /* the ucode id to signal the autoload */ 276 uint32_t autoload_ucode_id; 277 278 struct mutex rlcg_reg_lock; 279 }; 280 281 struct amdgpu_video_codec_info; 282 283 #define amdgpu_sriov_enabled(adev) \ 284 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 285 286 #define amdgpu_sriov_vf(adev) \ 287 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 288 289 #define amdgpu_sriov_bios(adev) \ 290 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 291 292 #define amdgpu_sriov_runtime(adev) \ 293 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 294 295 #define amdgpu_sriov_fullaccess(adev) \ 296 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev))) 297 298 #define amdgpu_sriov_reg_indirect_en(adev) \ 299 (amdgpu_sriov_vf((adev)) && \ 300 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS))) 301 302 #define amdgpu_sriov_reg_indirect_ih(adev) \ 303 (amdgpu_sriov_vf((adev)) && \ 304 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN))) 305 306 #define amdgpu_sriov_reg_indirect_mmhub(adev) \ 307 (amdgpu_sriov_vf((adev)) && \ 308 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN))) 309 310 #define amdgpu_sriov_reg_indirect_gc(adev) \ 311 (amdgpu_sriov_vf((adev)) && \ 312 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN))) 313 314 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \ 315 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev)) 316 317 #define amdgpu_passthrough(adev) \ 318 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 319 320 #define amdgpu_sriov_vf_mmio_access_protection(adev) \ 321 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT) 322 323 static inline bool is_virtual_machine(void) 324 { 325 #if defined(CONFIG_X86) 326 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 327 #elif defined(CONFIG_ARM64) 328 return !is_kernel_in_hyp_mode(); 329 #else 330 return false; 331 #endif 332 } 333 334 #define amdgpu_sriov_is_pp_one_vf(adev) \ 335 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 336 #define amdgpu_sriov_is_debug(adev) \ 337 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug) 338 #define amdgpu_sriov_is_normal(adev) \ 339 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug)) 340 #define amdgpu_sriov_is_av1_support(adev) \ 341 ((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT) 342 #define amdgpu_sriov_is_vcn_rb_decouple(adev) \ 343 ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE) 344 #define amdgpu_sriov_is_mes_info_enable(adev) \ 345 ((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE) 346 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 347 void amdgpu_virt_init_setting(struct amdgpu_device *adev); 348 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 349 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 350 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 351 void amdgpu_virt_request_init_data(struct amdgpu_device *adev); 352 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev); 353 int amdgpu_virt_wait_reset(struct amdgpu_device *adev); 354 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); 355 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); 356 bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev); 357 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev); 358 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); 359 void amdgpu_virt_exchange_data(struct amdgpu_device *adev); 360 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); 361 void amdgpu_detect_virtualization(struct amdgpu_device *adev); 362 363 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); 364 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); 365 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); 366 367 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); 368 369 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 370 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 371 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size); 372 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 373 u32 offset, u32 value, 374 u32 acc_flags, u32 hwip, u32 xcc_id); 375 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 376 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id); 377 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, 378 uint32_t ucode_id); 379 void amdgpu_virt_post_reset(struct amdgpu_device *adev); 380 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev); 381 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 382 u32 acc_flags, u32 hwip, 383 bool write, u32 *rlcg_flag); 384 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id); 385 #endif 386