1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Monk.liu@amd.com 23 */ 24 #ifndef AMDGPU_VIRT_H 25 #define AMDGPU_VIRT_H 26 27 #include "amdgv_sriovmsg.h" 28 29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 34 #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */ 35 #define AMDGPU_VIRT_VRAM_IS_SPM (1 << 6) /* FB BAR0 is absent; VRAM is SPM */ 36 37 /* flags for indirect register access path supported by rlcg for sriov */ 38 #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28) 39 #define AMDGPU_RLCG_GC_WRITE (0x0 << 28) 40 #define AMDGPU_RLCG_GC_READ (0x1 << 28) 41 #define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28) 42 43 /* error code for indirect register access path supported by rlcg for sriov */ 44 #define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000 45 #define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000 46 #define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000 47 48 #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF 49 #define AMDGPU_RLCG_SCRATCH1_ERROR_MASK 0xF000000 50 51 #define AMDGPU_RLCG_VFI_CMD__WR 0x0 52 #define AMDGPU_RLCG_VFI_CMD__RD 0x1 53 54 #define AMDGPU_RLCG_VFI_STAT__BUSY 0x0 55 #define AMDGPU_RLCG_VFI_STAT__DONE 0x1 56 #define AMDGPU_RLCG_VFI_STAT__INV_CMD 0x2 57 #define AMDGPU_RLCG_VFI_STAT__INV_ADDR 0x3 58 #define AMDGPU_RLCG_VFI_STAT__ERR 0xFF 59 60 /* all asic after AI use this offset */ 61 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 62 /* tonga/fiji use this offset */ 63 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 64 65 #define AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT 2 66 67 /* Signature used to validate the SR-IOV dynamic critical region init data header ("INDA") */ 68 #define AMDGPU_SRIOV_CRIT_DATA_SIGNATURE "INDA" 69 #define AMDGPU_SRIOV_CRIT_DATA_SIG_LEN 4 70 71 #define IS_SRIOV_CRIT_REGN_ENTRY_VALID(hdr, id) ((hdr)->valid_tables & (1 << (id))) 72 73 enum amdgpu_sriov_vf_mode { 74 SRIOV_VF_MODE_BARE_METAL = 0, 75 SRIOV_VF_MODE_ONE_VF, 76 SRIOV_VF_MODE_MULTI_VF, 77 }; 78 79 struct amdgpu_mm_table { 80 struct amdgpu_bo *bo; 81 uint32_t *cpu_addr; 82 uint64_t gpu_addr; 83 }; 84 85 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16 86 87 /* struct error_entry - amdgpu VF error information. */ 88 struct amdgpu_vf_error_buffer { 89 struct mutex lock; 90 int read_count; 91 int write_count; 92 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; 93 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE]; 94 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; 95 }; 96 97 enum idh_request; 98 99 /** 100 * struct amdgpu_virt_ops - amdgpu device virt operations 101 */ 102 struct amdgpu_virt_ops { 103 int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 104 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 105 int (*req_init_data)(struct amdgpu_device *adev); 106 int (*reset_gpu)(struct amdgpu_device *adev); 107 void (*ready_to_reset)(struct amdgpu_device *adev); 108 int (*wait_reset)(struct amdgpu_device *adev); 109 void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req, 110 u32 data1, u32 data2, u32 data3); 111 void (*ras_poison_handler)(struct amdgpu_device *adev, 112 enum amdgpu_ras_block block); 113 bool (*rcvd_ras_intr)(struct amdgpu_device *adev); 114 int (*req_ras_err_count)(struct amdgpu_device *adev); 115 int (*req_ras_cper_dump)(struct amdgpu_device *adev, u64 vf_rptr); 116 int (*req_bad_pages)(struct amdgpu_device *adev); 117 int (*req_ras_chk_criti)(struct amdgpu_device *adev, u64 addr); 118 int (*req_remote_ras_cmd)(struct amdgpu_device *adev, 119 u32 param1, u32 param2, u32 param3); 120 int (*req_ptl_update)(struct amdgpu_device *adev, 121 u32 req_code, u32 ptl_state, u32 fmt1, u32 fmt2); 122 }; 123 124 /* 125 * Firmware Reserve Frame buffer 126 */ 127 struct amdgpu_virt_fw_reserve { 128 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; 129 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; 130 void *ras_telemetry; 131 unsigned int checksum_key; 132 }; 133 134 /* 135 * Legacy GIM header 136 * 137 * Defination between PF and VF 138 * Structures forcibly aligned to 4 to keep the same style as PF. 139 */ 140 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024) 141 142 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \ 143 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2)) 144 145 enum AMDGIM_FEATURE_FLAG { 146 /* GIM supports feature of Error log collecting */ 147 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, 148 /* GIM supports feature of loading uCodes */ 149 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, 150 /* VRAM LOST by GIM */ 151 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, 152 /* MM bandwidth */ 153 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8, 154 /* PP ONE VF MODE in GIM */ 155 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4), 156 /* Indirect Reg Access enabled */ 157 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5), 158 /* AV1 Support MODE*/ 159 AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6), 160 /* VCN RB decouple */ 161 AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7), 162 /* MES info */ 163 AMDGIM_FEATURE_MES_INFO_ENABLE = (1 << 8), 164 AMDGIM_FEATURE_RAS_CAPS = (1 << 9), 165 AMDGIM_FEATURE_RAS_TELEMETRY = (1 << 10), 166 AMDGIM_FEATURE_RAS_CPER = (1 << 11), 167 AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK = (1 << 12), 168 AMDGIM_FEATURE_XGMI_CONNECTED_TO_CPU = (1 << 13), 169 AMDGIM_FEATURE_PTL_SUPPORT = (1 << 14), 170 AMDGIM_FEATURE_UNITID_SUPPORT = (1 << 15), 171 }; 172 173 enum AMDGIM_REG_ACCESS_FLAG { 174 /* Use PSP to program IH_RB_CNTL */ 175 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0), 176 /* Use RLC to program MMHUB regs */ 177 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1), 178 /* Use RLC to program GC regs */ 179 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2), 180 /* Use PSP to program L1_TLB_CNTL */ 181 AMDGIM_FEATURE_L1_TLB_CNTL_PSP_EN = (1 << 3), 182 /* Use RLCG to program SQ_CONFIG1 */ 183 AMDGIM_FEATURE_REG_ACCESS_SQ_CONFIG = (1 << 4), 184 }; 185 186 struct amdgim_pf2vf_info_v1 { 187 /* header contains size and version */ 188 struct amd_sriov_msg_pf2vf_info_header header; 189 /* max_width * max_height */ 190 unsigned int uvd_enc_max_pixels_count; 191 /* 16x16 pixels/sec, codec independent */ 192 unsigned int uvd_enc_max_bandwidth; 193 /* max_width * max_height */ 194 unsigned int vce_enc_max_pixels_count; 195 /* 16x16 pixels/sec, codec independent */ 196 unsigned int vce_enc_max_bandwidth; 197 /* MEC FW position in kb from the start of visible frame buffer */ 198 unsigned int mecfw_kboffset; 199 /* The features flags of the GIM driver supports. */ 200 unsigned int feature_flags; 201 /* use private key from mailbox 2 to create chueksum */ 202 unsigned int checksum; 203 } __aligned(4); 204 205 struct amdgim_vf2pf_info_v1 { 206 /* header contains size and version */ 207 struct amd_sriov_msg_vf2pf_info_header header; 208 /* driver version */ 209 char driver_version[64]; 210 /* driver certification, 1=WHQL, 0=None */ 211 unsigned int driver_cert; 212 /* guest OS type and version: need a define */ 213 unsigned int os_info; 214 /* in the unit of 1M */ 215 unsigned int fb_usage; 216 /* guest gfx engine usage percentage */ 217 unsigned int gfx_usage; 218 /* guest gfx engine health percentage */ 219 unsigned int gfx_health; 220 /* guest compute engine usage percentage */ 221 unsigned int compute_usage; 222 /* guest compute engine health percentage */ 223 unsigned int compute_health; 224 /* guest vce engine usage percentage. 0xffff means N/A. */ 225 unsigned int vce_enc_usage; 226 /* guest vce engine health percentage. 0xffff means N/A. */ 227 unsigned int vce_enc_health; 228 /* guest uvd engine usage percentage. 0xffff means N/A. */ 229 unsigned int uvd_enc_usage; 230 /* guest uvd engine usage percentage. 0xffff means N/A. */ 231 unsigned int uvd_enc_health; 232 unsigned int checksum; 233 } __aligned(4); 234 235 struct amdgim_vf2pf_info_v2 { 236 /* header contains size and version */ 237 struct amd_sriov_msg_vf2pf_info_header header; 238 uint32_t checksum; 239 /* driver version */ 240 uint8_t driver_version[64]; 241 /* driver certification, 1=WHQL, 0=None */ 242 uint32_t driver_cert; 243 /* guest OS type and version: need a define */ 244 uint32_t os_info; 245 /* in the unit of 1M */ 246 uint32_t fb_usage; 247 /* guest gfx engine usage percentage */ 248 uint32_t gfx_usage; 249 /* guest gfx engine health percentage */ 250 uint32_t gfx_health; 251 /* guest compute engine usage percentage */ 252 uint32_t compute_usage; 253 /* guest compute engine health percentage */ 254 uint32_t compute_health; 255 /* guest vce engine usage percentage. 0xffff means N/A. */ 256 uint32_t vce_enc_usage; 257 /* guest vce engine health percentage. 0xffff means N/A. */ 258 uint32_t vce_enc_health; 259 /* guest uvd engine usage percentage. 0xffff means N/A. */ 260 uint32_t uvd_enc_usage; 261 /* guest uvd engine usage percentage. 0xffff means N/A. */ 262 uint32_t uvd_enc_health; 263 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; 264 } __aligned(4); 265 266 struct amdgpu_virt_ras_err_handler_data { 267 /* point to bad page records array */ 268 struct eeprom_table_record *bps; 269 /* point to reserved bo array */ 270 struct amdgpu_bo **bps_bo; 271 /* number of slots in bps[] / bps_bo[] (always >= count) */ 272 int capacity; 273 /* the count of entries */ 274 int count; 275 /* last reserved entry's index + 1 */ 276 int last_reserved; 277 }; 278 279 struct amdgpu_virt_ras { 280 struct ratelimit_state ras_error_cnt_rs; 281 struct ratelimit_state ras_cper_dump_rs; 282 struct ratelimit_state ras_chk_criti_rs; 283 struct mutex ras_telemetry_mutex; 284 uint64_t cper_rptr; 285 }; 286 287 #define AMDGPU_VIRT_CAPS_LIST(X) X(AMDGPU_VIRT_CAP_POWER_LIMIT) 288 289 DECLARE_ATTR_CAP_CLASS(amdgpu_virt, AMDGPU_VIRT_CAPS_LIST); 290 291 struct amdgpu_virt_region { 292 uint32_t offset; 293 uint32_t size_kb; 294 }; 295 296 /* GPU virtualization */ 297 struct amdgpu_virt { 298 uint32_t caps; 299 struct amdgpu_bo *csa_obj; 300 void *csa_cpu_addr; 301 bool chained_ib_support; 302 uint32_t reg_val_offs; 303 struct amdgpu_irq_src ack_irq; 304 struct amdgpu_irq_src rcv_irq; 305 306 struct work_struct flr_work; 307 struct work_struct req_bad_pages_work; 308 struct work_struct handle_bad_pages_work; 309 310 struct amdgpu_mm_table mm_table; 311 const struct amdgpu_virt_ops *ops; 312 struct amdgpu_vf_error_buffer vf_errors; 313 struct amdgpu_virt_fw_reserve fw_reserve; 314 struct amdgpu_virt_caps virt_caps; 315 uint32_t gim_feature; 316 uint32_t reg_access_mode; 317 int req_init_data_ver; 318 bool tdr_debug; 319 struct amdgpu_virt_ras_err_handler_data *virt_eh_data; 320 bool ras_init_done; 321 uint32_t reg_access; 322 323 /* dynamic(v2) critical regions */ 324 struct amdgpu_virt_region init_data_header; 325 struct amdgpu_virt_region crit_regn; 326 struct amdgpu_virt_region crit_regn_tbl[AMD_SRIOV_MSG_MAX_TABLE_ID]; 327 bool is_dynamic_crit_regn_enabled; 328 329 /* vf2pf message */ 330 struct delayed_work vf2pf_work; 331 uint32_t vf2pf_update_interval_ms; 332 int vf2pf_update_retry_cnt; 333 334 /* multimedia bandwidth config */ 335 bool is_mm_bw_enabled; 336 uint32_t decode_max_dimension_pixels; 337 uint32_t decode_max_frame_pixels; 338 uint32_t encode_max_dimension_pixels; 339 uint32_t encode_max_frame_pixels; 340 341 /* the ucode id to signal the autoload */ 342 uint32_t autoload_ucode_id; 343 344 /* Spinlock to protect access to the RLCG register interface */ 345 spinlock_t rlcg_reg_lock; 346 347 /* PTL (Performance Throttle Limiter) response from host */ 348 uint32_t ptl_state; 349 uint32_t ptl_pref_format1; 350 uint32_t ptl_pref_format2; 351 352 struct mutex access_req_mutex; 353 354 union amd_sriov_ras_caps ras_en_caps; 355 union amd_sriov_ras_caps ras_telemetry_en_caps; 356 struct amdgpu_virt_ras ras; 357 struct amd_sriov_ras_telemetry_error_count count_cache; 358 359 /* hibernate and resume with different VF feature for xgmi enabled system */ 360 bool is_xgmi_node_migrate_enabled; 361 }; 362 363 struct amdgpu_video_codec_info; 364 365 #define amdgpu_sriov_enabled(adev) \ 366 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 367 368 #define amdgpu_sriov_vf(adev) \ 369 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 370 371 #define amdgpu_sriov_bios(adev) \ 372 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 373 374 #define amdgpu_sriov_runtime(adev) \ 375 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 376 377 #define amdgpu_sriov_fullaccess(adev) \ 378 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev))) 379 380 #define amdgpu_sriov_reg_indirect_en(adev) \ 381 (amdgpu_sriov_vf((adev)) && \ 382 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS))) 383 384 #define amdgpu_sriov_reg_indirect_ih(adev) \ 385 (amdgpu_sriov_vf((adev)) && \ 386 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN))) 387 388 #define amdgpu_sriov_reg_indirect_mmhub(adev) \ 389 (amdgpu_sriov_vf((adev)) && \ 390 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN))) 391 392 #define amdgpu_sriov_reg_indirect_gc(adev) \ 393 (amdgpu_sriov_vf((adev)) && \ 394 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN))) 395 396 #define amdgpu_sriov_reg_indirect_l1_tlb_cntl(adev) \ 397 (amdgpu_sriov_vf((adev)) && \ 398 ((adev)->virt.reg_access & (AMDGIM_FEATURE_L1_TLB_CNTL_PSP_EN))) 399 400 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \ 401 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev)) 402 403 #define amdgpu_sriov_reg_access_sq_config(adev) \ 404 (amdgpu_sriov_vf((adev)) && \ 405 ((adev)->virt.reg_access & (AMDGIM_FEATURE_REG_ACCESS_SQ_CONFIG))) 406 407 #define amdgpu_passthrough(adev) \ 408 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 409 410 #define amdgpu_virt_vram_is_spm(adev) \ 411 ((adev)->virt.caps & AMDGPU_VIRT_VRAM_IS_SPM) 412 413 #define amdgpu_sriov_vf_mmio_access_protection(adev) \ 414 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT) 415 416 #define amdgpu_sriov_ras_caps_en(adev) \ 417 ((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CAPS) 418 419 #define amdgpu_sriov_ras_telemetry_en(adev) \ 420 (((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_TELEMETRY) && (adev)->virt.fw_reserve.ras_telemetry) 421 422 #define amdgpu_sriov_ras_telemetry_block_en(adev, sriov_blk) \ 423 (amdgpu_sriov_ras_telemetry_en((adev)) && (adev)->virt.ras_telemetry_en_caps.all & BIT(sriov_blk)) 424 425 #define amdgpu_sriov_ras_cper_en(adev) \ 426 ((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CPER) 427 428 #define amdgpu_sriov_xgmi_ta_ext_peer_link_en(adev) \ 429 ((adev)->virt.gim_feature & AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK) 430 431 #define amdgpu_sriov_xgmi_connected_to_cpu(adev) \ 432 ((adev)->virt.gim_feature & AMDGIM_FEATURE_XGMI_CONNECTED_TO_CPU) 433 434 static inline bool is_virtual_machine(void) 435 { 436 #if defined(CONFIG_X86) 437 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 438 #elif defined(CONFIG_ARM64) 439 return !is_kernel_in_hyp_mode(); 440 #else 441 return false; 442 #endif 443 } 444 445 #define amdgpu_sriov_is_pp_one_vf(adev) \ 446 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 447 #define amdgpu_sriov_multi_vf_mode(adev) \ 448 (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 449 #define amdgpu_sriov_is_debug(adev) \ 450 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug) 451 #define amdgpu_sriov_is_normal(adev) \ 452 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug)) 453 #define amdgpu_sriov_is_av1_support(adev) \ 454 ((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT) 455 #define amdgpu_sriov_is_vcn_rb_decouple(adev) \ 456 ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE) 457 #define amdgpu_sriov_is_mes_info_enable(adev) \ 458 ((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE) 459 #define amdgpu_sriov_is_unitid_support(adev) \ 460 ((adev)->virt.gim_feature & AMDGIM_FEATURE_UNITID_SUPPORT) 461 #define amdgpu_sriov_ptl_support(adev) \ 462 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PTL_SUPPORT) 463 464 #define amdgpu_virt_xgmi_migrate_enabled(adev) \ 465 ((adev)->virt.is_xgmi_node_migrate_enabled && (adev)->gmc.xgmi.node_segment_size != 0) 466 467 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 468 void amdgpu_virt_init_setting(struct amdgpu_device *adev); 469 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 470 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 471 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 472 void amdgpu_virt_request_init_data(struct amdgpu_device *adev); 473 int amdgpu_virt_ptl_request(struct amdgpu_device *adev, u32 req_code, 474 uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2); 475 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev); 476 int amdgpu_virt_wait_reset(struct amdgpu_device *adev); 477 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); 478 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); 479 bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev); 480 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev); 481 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); 482 void amdgpu_virt_exchange_data(struct amdgpu_device *adev); 483 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); 484 void amdgpu_virt_init(struct amdgpu_device *adev); 485 486 int amdgpu_virt_init_critical_region(struct amdgpu_device *adev); 487 int amdgpu_virt_get_dynamic_data_info(struct amdgpu_device *adev, 488 int data_id, uint8_t *binary, u32 *size); 489 490 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); 491 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); 492 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); 493 494 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); 495 496 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 497 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 498 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size); 499 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 500 u32 offset, u32 value, 501 u32 acc_flags, u32 hwip, u32 xcc_id); 502 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 503 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id); 504 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, 505 uint32_t ucode_id); 506 void amdgpu_virt_pre_reset(struct amdgpu_device *adev); 507 void amdgpu_virt_post_reset(struct amdgpu_device *adev); 508 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev); 509 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 510 u32 acc_flags, u32 hwip, 511 bool write, u32 *rlcg_flag); 512 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id); 513 int amdgpu_virt_get_uniras_ras_caps(struct amdgpu_device *adev, 514 struct amd_sriov_uniras_caps *caps); 515 bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev); 516 int amdgpu_virt_req_ras_err_count(struct amdgpu_device *adev, enum amdgpu_ras_block block, 517 struct ras_err_data *err_data); 518 int amdgpu_virt_req_ras_cper_dump(struct amdgpu_device *adev, bool force_update); 519 int amdgpu_virt_ras_telemetry_post_reset(struct amdgpu_device *adev); 520 bool amdgpu_virt_ras_telemetry_block_en(struct amdgpu_device *adev, 521 enum amdgpu_ras_block block); 522 void amdgpu_virt_request_bad_pages(struct amdgpu_device *adev); 523 int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, bool *hit); 524 int amdgpu_virt_send_remote_ras_cmd(struct amdgpu_device *adev, 525 uint64_t buf, uint32_t buf_len); 526 #endif 527