1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Monk.liu@amd.com 23 */ 24 #ifndef AMDGPU_VIRT_H 25 #define AMDGPU_VIRT_H 26 27 #include "amdgv_sriovmsg.h" 28 29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 34 #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */ 35 36 /* flags for indirect register access path supported by rlcg for sriov */ 37 #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28) 38 #define AMDGPU_RLCG_GC_WRITE (0x0 << 28) 39 #define AMDGPU_RLCG_GC_READ (0x1 << 28) 40 #define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28) 41 42 /* error code for indirect register access path supported by rlcg for sriov */ 43 #define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000 44 #define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000 45 #define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000 46 47 #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF 48 #define AMDGPU_RLCG_SCRATCH1_ERROR_MASK 0xF000000 49 50 /* all asic after AI use this offset */ 51 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 52 /* tonga/fiji use this offset */ 53 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 54 55 #define AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT 5 56 57 enum amdgpu_sriov_vf_mode { 58 SRIOV_VF_MODE_BARE_METAL = 0, 59 SRIOV_VF_MODE_ONE_VF, 60 SRIOV_VF_MODE_MULTI_VF, 61 }; 62 63 struct amdgpu_mm_table { 64 struct amdgpu_bo *bo; 65 uint32_t *cpu_addr; 66 uint64_t gpu_addr; 67 }; 68 69 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16 70 71 /* struct error_entry - amdgpu VF error information. */ 72 struct amdgpu_vf_error_buffer { 73 struct mutex lock; 74 int read_count; 75 int write_count; 76 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; 77 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE]; 78 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; 79 }; 80 81 enum idh_request; 82 83 /** 84 * struct amdgpu_virt_ops - amdgpu device virt operations 85 */ 86 struct amdgpu_virt_ops { 87 int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 88 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 89 int (*req_init_data)(struct amdgpu_device *adev); 90 int (*reset_gpu)(struct amdgpu_device *adev); 91 void (*ready_to_reset)(struct amdgpu_device *adev); 92 int (*wait_reset)(struct amdgpu_device *adev); 93 void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req, 94 u32 data1, u32 data2, u32 data3); 95 void (*ras_poison_handler)(struct amdgpu_device *adev, 96 enum amdgpu_ras_block block); 97 }; 98 99 /* 100 * Firmware Reserve Frame buffer 101 */ 102 struct amdgpu_virt_fw_reserve { 103 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; 104 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; 105 unsigned int checksum_key; 106 }; 107 108 /* 109 * Legacy GIM header 110 * 111 * Defination between PF and VF 112 * Structures forcibly aligned to 4 to keep the same style as PF. 113 */ 114 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024) 115 116 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \ 117 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2)) 118 119 enum AMDGIM_FEATURE_FLAG { 120 /* GIM supports feature of Error log collecting */ 121 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, 122 /* GIM supports feature of loading uCodes */ 123 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, 124 /* VRAM LOST by GIM */ 125 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, 126 /* MM bandwidth */ 127 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8, 128 /* PP ONE VF MODE in GIM */ 129 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4), 130 /* Indirect Reg Access enabled */ 131 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5), 132 /* AV1 Support MODE*/ 133 AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6), 134 /* VCN RB decouple */ 135 AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7), 136 /* MES info */ 137 AMDGIM_FEATURE_MES_INFO_ENABLE = (1 << 8), 138 }; 139 140 enum AMDGIM_REG_ACCESS_FLAG { 141 /* Use PSP to program IH_RB_CNTL */ 142 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0), 143 /* Use RLC to program MMHUB regs */ 144 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1), 145 /* Use RLC to program GC regs */ 146 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2), 147 }; 148 149 struct amdgim_pf2vf_info_v1 { 150 /* header contains size and version */ 151 struct amd_sriov_msg_pf2vf_info_header header; 152 /* max_width * max_height */ 153 unsigned int uvd_enc_max_pixels_count; 154 /* 16x16 pixels/sec, codec independent */ 155 unsigned int uvd_enc_max_bandwidth; 156 /* max_width * max_height */ 157 unsigned int vce_enc_max_pixels_count; 158 /* 16x16 pixels/sec, codec independent */ 159 unsigned int vce_enc_max_bandwidth; 160 /* MEC FW position in kb from the start of visible frame buffer */ 161 unsigned int mecfw_kboffset; 162 /* The features flags of the GIM driver supports. */ 163 unsigned int feature_flags; 164 /* use private key from mailbox 2 to create chueksum */ 165 unsigned int checksum; 166 } __aligned(4); 167 168 struct amdgim_vf2pf_info_v1 { 169 /* header contains size and version */ 170 struct amd_sriov_msg_vf2pf_info_header header; 171 /* driver version */ 172 char driver_version[64]; 173 /* driver certification, 1=WHQL, 0=None */ 174 unsigned int driver_cert; 175 /* guest OS type and version: need a define */ 176 unsigned int os_info; 177 /* in the unit of 1M */ 178 unsigned int fb_usage; 179 /* guest gfx engine usage percentage */ 180 unsigned int gfx_usage; 181 /* guest gfx engine health percentage */ 182 unsigned int gfx_health; 183 /* guest compute engine usage percentage */ 184 unsigned int compute_usage; 185 /* guest compute engine health percentage */ 186 unsigned int compute_health; 187 /* guest vce engine usage percentage. 0xffff means N/A. */ 188 unsigned int vce_enc_usage; 189 /* guest vce engine health percentage. 0xffff means N/A. */ 190 unsigned int vce_enc_health; 191 /* guest uvd engine usage percentage. 0xffff means N/A. */ 192 unsigned int uvd_enc_usage; 193 /* guest uvd engine usage percentage. 0xffff means N/A. */ 194 unsigned int uvd_enc_health; 195 unsigned int checksum; 196 } __aligned(4); 197 198 struct amdgim_vf2pf_info_v2 { 199 /* header contains size and version */ 200 struct amd_sriov_msg_vf2pf_info_header header; 201 uint32_t checksum; 202 /* driver version */ 203 uint8_t driver_version[64]; 204 /* driver certification, 1=WHQL, 0=None */ 205 uint32_t driver_cert; 206 /* guest OS type and version: need a define */ 207 uint32_t os_info; 208 /* in the unit of 1M */ 209 uint32_t fb_usage; 210 /* guest gfx engine usage percentage */ 211 uint32_t gfx_usage; 212 /* guest gfx engine health percentage */ 213 uint32_t gfx_health; 214 /* guest compute engine usage percentage */ 215 uint32_t compute_usage; 216 /* guest compute engine health percentage */ 217 uint32_t compute_health; 218 /* guest vce engine usage percentage. 0xffff means N/A. */ 219 uint32_t vce_enc_usage; 220 /* guest vce engine health percentage. 0xffff means N/A. */ 221 uint32_t vce_enc_health; 222 /* guest uvd engine usage percentage. 0xffff means N/A. */ 223 uint32_t uvd_enc_usage; 224 /* guest uvd engine usage percentage. 0xffff means N/A. */ 225 uint32_t uvd_enc_health; 226 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; 227 } __aligned(4); 228 229 struct amdgpu_virt_ras_err_handler_data { 230 /* point to bad page records array */ 231 struct eeprom_table_record *bps; 232 /* point to reserved bo array */ 233 struct amdgpu_bo **bps_bo; 234 /* the count of entries */ 235 int count; 236 /* last reserved entry's index + 1 */ 237 int last_reserved; 238 }; 239 240 /* GPU virtualization */ 241 struct amdgpu_virt { 242 uint32_t caps; 243 struct amdgpu_bo *csa_obj; 244 void *csa_cpu_addr; 245 bool chained_ib_support; 246 uint32_t reg_val_offs; 247 struct amdgpu_irq_src ack_irq; 248 struct amdgpu_irq_src rcv_irq; 249 struct work_struct flr_work; 250 struct amdgpu_mm_table mm_table; 251 const struct amdgpu_virt_ops *ops; 252 struct amdgpu_vf_error_buffer vf_errors; 253 struct amdgpu_virt_fw_reserve fw_reserve; 254 uint32_t gim_feature; 255 uint32_t reg_access_mode; 256 int req_init_data_ver; 257 bool tdr_debug; 258 struct amdgpu_virt_ras_err_handler_data *virt_eh_data; 259 bool ras_init_done; 260 uint32_t reg_access; 261 262 /* vf2pf message */ 263 struct delayed_work vf2pf_work; 264 uint32_t vf2pf_update_interval_ms; 265 int vf2pf_update_retry_cnt; 266 267 /* multimedia bandwidth config */ 268 bool is_mm_bw_enabled; 269 uint32_t decode_max_dimension_pixels; 270 uint32_t decode_max_frame_pixels; 271 uint32_t encode_max_dimension_pixels; 272 uint32_t encode_max_frame_pixels; 273 274 /* the ucode id to signal the autoload */ 275 uint32_t autoload_ucode_id; 276 277 struct mutex rlcg_reg_lock; 278 }; 279 280 struct amdgpu_video_codec_info; 281 282 #define amdgpu_sriov_enabled(adev) \ 283 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 284 285 #define amdgpu_sriov_vf(adev) \ 286 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 287 288 #define amdgpu_sriov_bios(adev) \ 289 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 290 291 #define amdgpu_sriov_runtime(adev) \ 292 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 293 294 #define amdgpu_sriov_fullaccess(adev) \ 295 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev))) 296 297 #define amdgpu_sriov_reg_indirect_en(adev) \ 298 (amdgpu_sriov_vf((adev)) && \ 299 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS))) 300 301 #define amdgpu_sriov_reg_indirect_ih(adev) \ 302 (amdgpu_sriov_vf((adev)) && \ 303 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN))) 304 305 #define amdgpu_sriov_reg_indirect_mmhub(adev) \ 306 (amdgpu_sriov_vf((adev)) && \ 307 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN))) 308 309 #define amdgpu_sriov_reg_indirect_gc(adev) \ 310 (amdgpu_sriov_vf((adev)) && \ 311 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN))) 312 313 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \ 314 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev)) 315 316 #define amdgpu_passthrough(adev) \ 317 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 318 319 #define amdgpu_sriov_vf_mmio_access_protection(adev) \ 320 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT) 321 322 static inline bool is_virtual_machine(void) 323 { 324 #if defined(CONFIG_X86) 325 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 326 #elif defined(CONFIG_ARM64) 327 return !is_kernel_in_hyp_mode(); 328 #else 329 return false; 330 #endif 331 } 332 333 #define amdgpu_sriov_is_pp_one_vf(adev) \ 334 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 335 #define amdgpu_sriov_is_debug(adev) \ 336 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug) 337 #define amdgpu_sriov_is_normal(adev) \ 338 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug)) 339 #define amdgpu_sriov_is_av1_support(adev) \ 340 ((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT) 341 #define amdgpu_sriov_is_vcn_rb_decouple(adev) \ 342 ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE) 343 #define amdgpu_sriov_is_mes_info_enable(adev) \ 344 ((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE) 345 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 346 void amdgpu_virt_init_setting(struct amdgpu_device *adev); 347 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 348 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 349 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 350 void amdgpu_virt_request_init_data(struct amdgpu_device *adev); 351 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev); 352 int amdgpu_virt_wait_reset(struct amdgpu_device *adev); 353 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); 354 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); 355 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev); 356 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); 357 void amdgpu_virt_exchange_data(struct amdgpu_device *adev); 358 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); 359 void amdgpu_detect_virtualization(struct amdgpu_device *adev); 360 361 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); 362 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); 363 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); 364 365 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); 366 367 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 368 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 369 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size); 370 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 371 u32 offset, u32 value, 372 u32 acc_flags, u32 hwip, u32 xcc_id); 373 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 374 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id); 375 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, 376 uint32_t ucode_id); 377 void amdgpu_virt_post_reset(struct amdgpu_device *adev); 378 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev); 379 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 380 u32 acc_flags, u32 hwip, 381 bool write, u32 *rlcg_flag); 382 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id); 383 #endif 384