1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Monk.liu@amd.com 23 */ 24 #ifndef AMDGPU_VIRT_H 25 #define AMDGPU_VIRT_H 26 27 #include "amdgv_sriovmsg.h" 28 29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 34 #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */ 35 36 /* flags for indirect register access path supported by rlcg for sriov */ 37 #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28) 38 #define AMDGPU_RLCG_GC_WRITE (0x0 << 28) 39 #define AMDGPU_RLCG_GC_READ (0x1 << 28) 40 #define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28) 41 42 /* error code for indirect register access path supported by rlcg for sriov */ 43 #define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000 44 #define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000 45 #define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000 46 47 #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF 48 49 /* all asic after AI use this offset */ 50 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 51 /* tonga/fiji use this offset */ 52 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 53 54 enum amdgpu_sriov_vf_mode { 55 SRIOV_VF_MODE_BARE_METAL = 0, 56 SRIOV_VF_MODE_ONE_VF, 57 SRIOV_VF_MODE_MULTI_VF, 58 }; 59 60 struct amdgpu_mm_table { 61 struct amdgpu_bo *bo; 62 uint32_t *cpu_addr; 63 uint64_t gpu_addr; 64 }; 65 66 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16 67 68 /* struct error_entry - amdgpu VF error information. */ 69 struct amdgpu_vf_error_buffer { 70 struct mutex lock; 71 int read_count; 72 int write_count; 73 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; 74 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE]; 75 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; 76 }; 77 78 enum idh_request; 79 80 /** 81 * struct amdgpu_virt_ops - amdgpu device virt operations 82 */ 83 struct amdgpu_virt_ops { 84 int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 85 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 86 int (*req_init_data)(struct amdgpu_device *adev); 87 int (*reset_gpu)(struct amdgpu_device *adev); 88 int (*wait_reset)(struct amdgpu_device *adev); 89 void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req, 90 u32 data1, u32 data2, u32 data3); 91 void (*ras_poison_handler)(struct amdgpu_device *adev, 92 enum amdgpu_ras_block block); 93 }; 94 95 /* 96 * Firmware Reserve Frame buffer 97 */ 98 struct amdgpu_virt_fw_reserve { 99 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; 100 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; 101 unsigned int checksum_key; 102 }; 103 104 /* 105 * Legacy GIM header 106 * 107 * Defination between PF and VF 108 * Structures forcibly aligned to 4 to keep the same style as PF. 109 */ 110 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024) 111 112 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \ 113 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2)) 114 115 enum AMDGIM_FEATURE_FLAG { 116 /* GIM supports feature of Error log collecting */ 117 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, 118 /* GIM supports feature of loading uCodes */ 119 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, 120 /* VRAM LOST by GIM */ 121 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, 122 /* MM bandwidth */ 123 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8, 124 /* PP ONE VF MODE in GIM */ 125 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4), 126 /* Indirect Reg Access enabled */ 127 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5), 128 /* AV1 Support MODE*/ 129 AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6), 130 /* VCN RB decouple */ 131 AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7), 132 }; 133 134 enum AMDGIM_REG_ACCESS_FLAG { 135 /* Use PSP to program IH_RB_CNTL */ 136 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0), 137 /* Use RLC to program MMHUB regs */ 138 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1), 139 /* Use RLC to program GC regs */ 140 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2), 141 }; 142 143 struct amdgim_pf2vf_info_v1 { 144 /* header contains size and version */ 145 struct amd_sriov_msg_pf2vf_info_header header; 146 /* max_width * max_height */ 147 unsigned int uvd_enc_max_pixels_count; 148 /* 16x16 pixels/sec, codec independent */ 149 unsigned int uvd_enc_max_bandwidth; 150 /* max_width * max_height */ 151 unsigned int vce_enc_max_pixels_count; 152 /* 16x16 pixels/sec, codec independent */ 153 unsigned int vce_enc_max_bandwidth; 154 /* MEC FW position in kb from the start of visible frame buffer */ 155 unsigned int mecfw_kboffset; 156 /* The features flags of the GIM driver supports. */ 157 unsigned int feature_flags; 158 /* use private key from mailbox 2 to create chueksum */ 159 unsigned int checksum; 160 } __aligned(4); 161 162 struct amdgim_vf2pf_info_v1 { 163 /* header contains size and version */ 164 struct amd_sriov_msg_vf2pf_info_header header; 165 /* driver version */ 166 char driver_version[64]; 167 /* driver certification, 1=WHQL, 0=None */ 168 unsigned int driver_cert; 169 /* guest OS type and version: need a define */ 170 unsigned int os_info; 171 /* in the unit of 1M */ 172 unsigned int fb_usage; 173 /* guest gfx engine usage percentage */ 174 unsigned int gfx_usage; 175 /* guest gfx engine health percentage */ 176 unsigned int gfx_health; 177 /* guest compute engine usage percentage */ 178 unsigned int compute_usage; 179 /* guest compute engine health percentage */ 180 unsigned int compute_health; 181 /* guest vce engine usage percentage. 0xffff means N/A. */ 182 unsigned int vce_enc_usage; 183 /* guest vce engine health percentage. 0xffff means N/A. */ 184 unsigned int vce_enc_health; 185 /* guest uvd engine usage percentage. 0xffff means N/A. */ 186 unsigned int uvd_enc_usage; 187 /* guest uvd engine usage percentage. 0xffff means N/A. */ 188 unsigned int uvd_enc_health; 189 unsigned int checksum; 190 } __aligned(4); 191 192 struct amdgim_vf2pf_info_v2 { 193 /* header contains size and version */ 194 struct amd_sriov_msg_vf2pf_info_header header; 195 uint32_t checksum; 196 /* driver version */ 197 uint8_t driver_version[64]; 198 /* driver certification, 1=WHQL, 0=None */ 199 uint32_t driver_cert; 200 /* guest OS type and version: need a define */ 201 uint32_t os_info; 202 /* in the unit of 1M */ 203 uint32_t fb_usage; 204 /* guest gfx engine usage percentage */ 205 uint32_t gfx_usage; 206 /* guest gfx engine health percentage */ 207 uint32_t gfx_health; 208 /* guest compute engine usage percentage */ 209 uint32_t compute_usage; 210 /* guest compute engine health percentage */ 211 uint32_t compute_health; 212 /* guest vce engine usage percentage. 0xffff means N/A. */ 213 uint32_t vce_enc_usage; 214 /* guest vce engine health percentage. 0xffff means N/A. */ 215 uint32_t vce_enc_health; 216 /* guest uvd engine usage percentage. 0xffff means N/A. */ 217 uint32_t uvd_enc_usage; 218 /* guest uvd engine usage percentage. 0xffff means N/A. */ 219 uint32_t uvd_enc_health; 220 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; 221 } __aligned(4); 222 223 struct amdgpu_virt_ras_err_handler_data { 224 /* point to bad page records array */ 225 struct eeprom_table_record *bps; 226 /* point to reserved bo array */ 227 struct amdgpu_bo **bps_bo; 228 /* the count of entries */ 229 int count; 230 /* last reserved entry's index + 1 */ 231 int last_reserved; 232 }; 233 234 /* GPU virtualization */ 235 struct amdgpu_virt { 236 uint32_t caps; 237 struct amdgpu_bo *csa_obj; 238 void *csa_cpu_addr; 239 bool chained_ib_support; 240 uint32_t reg_val_offs; 241 struct amdgpu_irq_src ack_irq; 242 struct amdgpu_irq_src rcv_irq; 243 struct work_struct flr_work; 244 struct amdgpu_mm_table mm_table; 245 const struct amdgpu_virt_ops *ops; 246 struct amdgpu_vf_error_buffer vf_errors; 247 struct amdgpu_virt_fw_reserve fw_reserve; 248 uint32_t gim_feature; 249 uint32_t reg_access_mode; 250 int req_init_data_ver; 251 bool tdr_debug; 252 struct amdgpu_virt_ras_err_handler_data *virt_eh_data; 253 bool ras_init_done; 254 uint32_t reg_access; 255 256 /* vf2pf message */ 257 struct delayed_work vf2pf_work; 258 uint32_t vf2pf_update_interval_ms; 259 260 /* multimedia bandwidth config */ 261 bool is_mm_bw_enabled; 262 uint32_t decode_max_dimension_pixels; 263 uint32_t decode_max_frame_pixels; 264 uint32_t encode_max_dimension_pixels; 265 uint32_t encode_max_frame_pixels; 266 267 /* the ucode id to signal the autoload */ 268 uint32_t autoload_ucode_id; 269 }; 270 271 struct amdgpu_video_codec_info; 272 273 #define amdgpu_sriov_enabled(adev) \ 274 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 275 276 #define amdgpu_sriov_vf(adev) \ 277 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 278 279 #define amdgpu_sriov_bios(adev) \ 280 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 281 282 #define amdgpu_sriov_runtime(adev) \ 283 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 284 285 #define amdgpu_sriov_fullaccess(adev) \ 286 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev))) 287 288 #define amdgpu_sriov_reg_indirect_en(adev) \ 289 (amdgpu_sriov_vf((adev)) && \ 290 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS))) 291 292 #define amdgpu_sriov_reg_indirect_ih(adev) \ 293 (amdgpu_sriov_vf((adev)) && \ 294 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN))) 295 296 #define amdgpu_sriov_reg_indirect_mmhub(adev) \ 297 (amdgpu_sriov_vf((adev)) && \ 298 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN))) 299 300 #define amdgpu_sriov_reg_indirect_gc(adev) \ 301 (amdgpu_sriov_vf((adev)) && \ 302 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN))) 303 304 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \ 305 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev)) 306 307 #define amdgpu_passthrough(adev) \ 308 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 309 310 #define amdgpu_sriov_vf_mmio_access_protection(adev) \ 311 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT) 312 313 static inline bool is_virtual_machine(void) 314 { 315 #if defined(CONFIG_X86) 316 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 317 #elif defined(CONFIG_ARM64) 318 return !is_kernel_in_hyp_mode(); 319 #else 320 return false; 321 #endif 322 } 323 324 #define amdgpu_sriov_is_pp_one_vf(adev) \ 325 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 326 #define amdgpu_sriov_is_debug(adev) \ 327 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug) 328 #define amdgpu_sriov_is_normal(adev) \ 329 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug)) 330 #define amdgpu_sriov_is_av1_support(adev) \ 331 ((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT) 332 #define amdgpu_sriov_is_vcn_rb_decouple(adev) \ 333 ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE) 334 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 335 void amdgpu_virt_init_setting(struct amdgpu_device *adev); 336 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 337 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 338 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 339 void amdgpu_virt_request_init_data(struct amdgpu_device *adev); 340 int amdgpu_virt_wait_reset(struct amdgpu_device *adev); 341 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); 342 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); 343 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev); 344 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); 345 void amdgpu_virt_exchange_data(struct amdgpu_device *adev); 346 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); 347 void amdgpu_detect_virtualization(struct amdgpu_device *adev); 348 349 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); 350 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); 351 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); 352 353 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); 354 355 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 356 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 357 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size); 358 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 359 u32 offset, u32 value, 360 u32 acc_flags, u32 hwip, u32 xcc_id); 361 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 362 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id); 363 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, 364 uint32_t ucode_id); 365 void amdgpu_virt_post_reset(struct amdgpu_device *adev); 366 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev); 367 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 368 u32 acc_flags, u32 hwip, 369 bool write, u32 *rlcg_flag); 370 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id); 371 #endif 372