1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/module.h> 25 26 #ifdef CONFIG_X86 27 #include <asm/hypervisor.h> 28 #endif 29 30 #include <drm/drm_drv.h> 31 #include <xen/xen.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_ras.h" 35 #include "amdgpu_reset.h" 36 #include "vi.h" 37 #include "soc15.h" 38 #include "nv.h" 39 40 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \ 41 do { \ 42 vf2pf_info->ucode_info[ucode].id = ucode; \ 43 vf2pf_info->ucode_info[ucode].version = ver; \ 44 } while (0) 45 46 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) 47 { 48 /* By now all MMIO pages except mailbox are blocked */ 49 /* if blocking is enabled in hypervisor. Choose the */ 50 /* SCRATCH_REG0 to test. */ 51 return RREG32_NO_KIQ(0xc040) == 0xffffffff; 52 } 53 54 void amdgpu_virt_init_setting(struct amdgpu_device *adev) 55 { 56 struct drm_device *ddev = adev_to_drm(adev); 57 58 /* enable virtual display */ 59 if (adev->asic_type != CHIP_ALDEBARAN && 60 adev->asic_type != CHIP_ARCTURUS && 61 ((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) { 62 if (adev->mode_info.num_crtc == 0) 63 adev->mode_info.num_crtc = 1; 64 adev->enable_virtual_display = true; 65 } 66 ddev->driver_features &= ~DRIVER_ATOMIC; 67 adev->cg_flags = 0; 68 adev->pg_flags = 0; 69 70 /* Reduce kcq number to 2 to reduce latency */ 71 if (amdgpu_num_kcq == -1) 72 amdgpu_num_kcq = 2; 73 } 74 75 /** 76 * amdgpu_virt_request_full_gpu() - request full gpu access 77 * @adev: amdgpu device. 78 * @init: is driver init time. 79 * When start to init/fini driver, first need to request full gpu access. 80 * Return: Zero if request success, otherwise will return error. 81 */ 82 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init) 83 { 84 struct amdgpu_virt *virt = &adev->virt; 85 int r; 86 87 if (virt->ops && virt->ops->req_full_gpu) { 88 r = virt->ops->req_full_gpu(adev, init); 89 if (r) 90 return r; 91 92 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 93 } 94 95 return 0; 96 } 97 98 /** 99 * amdgpu_virt_release_full_gpu() - release full gpu access 100 * @adev: amdgpu device. 101 * @init: is driver init time. 102 * When finishing driver init/fini, need to release full gpu access. 103 * Return: Zero if release success, otherwise will returen error. 104 */ 105 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init) 106 { 107 struct amdgpu_virt *virt = &adev->virt; 108 int r; 109 110 if (virt->ops && virt->ops->rel_full_gpu) { 111 r = virt->ops->rel_full_gpu(adev, init); 112 if (r) 113 return r; 114 115 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 116 } 117 return 0; 118 } 119 120 /** 121 * amdgpu_virt_reset_gpu() - reset gpu 122 * @adev: amdgpu device. 123 * Send reset command to GPU hypervisor to reset GPU that VM is using 124 * Return: Zero if reset success, otherwise will return error. 125 */ 126 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev) 127 { 128 struct amdgpu_virt *virt = &adev->virt; 129 int r; 130 131 if (virt->ops && virt->ops->reset_gpu) { 132 r = virt->ops->reset_gpu(adev); 133 if (r) 134 return r; 135 136 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 137 } 138 139 return 0; 140 } 141 142 void amdgpu_virt_request_init_data(struct amdgpu_device *adev) 143 { 144 struct amdgpu_virt *virt = &adev->virt; 145 146 if (virt->ops && virt->ops->req_init_data) 147 virt->ops->req_init_data(adev); 148 149 if (adev->virt.req_init_data_ver > 0) 150 DRM_INFO("host supports REQ_INIT_DATA handshake\n"); 151 else 152 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n"); 153 } 154 155 /** 156 * amdgpu_virt_wait_reset() - wait for reset gpu completed 157 * @adev: amdgpu device. 158 * Wait for GPU reset completed. 159 * Return: Zero if reset success, otherwise will return error. 160 */ 161 int amdgpu_virt_wait_reset(struct amdgpu_device *adev) 162 { 163 struct amdgpu_virt *virt = &adev->virt; 164 165 if (!virt->ops || !virt->ops->wait_reset) 166 return -EINVAL; 167 168 return virt->ops->wait_reset(adev); 169 } 170 171 /** 172 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table 173 * @adev: amdgpu device. 174 * MM table is used by UVD and VCE for its initialization 175 * Return: Zero if allocate success. 176 */ 177 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev) 178 { 179 int r; 180 181 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) 182 return 0; 183 184 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 185 AMDGPU_GEM_DOMAIN_VRAM | 186 AMDGPU_GEM_DOMAIN_GTT, 187 &adev->virt.mm_table.bo, 188 &adev->virt.mm_table.gpu_addr, 189 (void *)&adev->virt.mm_table.cpu_addr); 190 if (r) { 191 DRM_ERROR("failed to alloc mm table and error = %d.\n", r); 192 return r; 193 } 194 195 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); 196 DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n", 197 adev->virt.mm_table.gpu_addr, 198 adev->virt.mm_table.cpu_addr); 199 return 0; 200 } 201 202 /** 203 * amdgpu_virt_free_mm_table() - free mm table memory 204 * @adev: amdgpu device. 205 * Free MM table memory 206 */ 207 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev) 208 { 209 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) 210 return; 211 212 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo, 213 &adev->virt.mm_table.gpu_addr, 214 (void *)&adev->virt.mm_table.cpu_addr); 215 adev->virt.mm_table.gpu_addr = 0; 216 } 217 218 219 unsigned int amd_sriov_msg_checksum(void *obj, 220 unsigned long obj_size, 221 unsigned int key, 222 unsigned int checksum) 223 { 224 unsigned int ret = key; 225 unsigned long i = 0; 226 unsigned char *pos; 227 228 pos = (char *)obj; 229 /* calculate checksum */ 230 for (i = 0; i < obj_size; ++i) 231 ret += *(pos + i); 232 /* minus the checksum itself */ 233 pos = (char *)&checksum; 234 for (i = 0; i < sizeof(checksum); ++i) 235 ret -= *(pos + i); 236 return ret; 237 } 238 239 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev) 240 { 241 struct amdgpu_virt *virt = &adev->virt; 242 struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data; 243 /* GPU will be marked bad on host if bp count more then 10, 244 * so alloc 512 is enough. 245 */ 246 unsigned int align_space = 512; 247 void *bps = NULL; 248 struct amdgpu_bo **bps_bo = NULL; 249 250 *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL); 251 if (!*data) 252 goto data_failure; 253 254 bps = kmalloc_array(align_space, sizeof(*(*data)->bps), GFP_KERNEL); 255 if (!bps) 256 goto bps_failure; 257 258 bps_bo = kmalloc_array(align_space, sizeof(*(*data)->bps_bo), GFP_KERNEL); 259 if (!bps_bo) 260 goto bps_bo_failure; 261 262 (*data)->bps = bps; 263 (*data)->bps_bo = bps_bo; 264 (*data)->count = 0; 265 (*data)->last_reserved = 0; 266 267 virt->ras_init_done = true; 268 269 return 0; 270 271 bps_bo_failure: 272 kfree(bps); 273 bps_failure: 274 kfree(*data); 275 data_failure: 276 return -ENOMEM; 277 } 278 279 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev) 280 { 281 struct amdgpu_virt *virt = &adev->virt; 282 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 283 struct amdgpu_bo *bo; 284 int i; 285 286 if (!data) 287 return; 288 289 for (i = data->last_reserved - 1; i >= 0; i--) { 290 bo = data->bps_bo[i]; 291 if (bo) { 292 amdgpu_bo_free_kernel(&bo, NULL, NULL); 293 data->bps_bo[i] = bo; 294 } 295 data->last_reserved = i; 296 } 297 } 298 299 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev) 300 { 301 struct amdgpu_virt *virt = &adev->virt; 302 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 303 304 virt->ras_init_done = false; 305 306 if (!data) 307 return; 308 309 amdgpu_virt_ras_release_bp(adev); 310 311 kfree(data->bps); 312 kfree(data->bps_bo); 313 kfree(data); 314 virt->virt_eh_data = NULL; 315 } 316 317 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev, 318 struct eeprom_table_record *bps, int pages) 319 { 320 struct amdgpu_virt *virt = &adev->virt; 321 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 322 323 if (!data) 324 return; 325 326 memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); 327 data->count += pages; 328 } 329 330 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev) 331 { 332 struct amdgpu_virt *virt = &adev->virt; 333 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 334 struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; 335 struct ttm_resource_manager *man = &mgr->manager; 336 struct amdgpu_bo *bo = NULL; 337 uint64_t bp; 338 int i; 339 340 if (!data) 341 return; 342 343 for (i = data->last_reserved; i < data->count; i++) { 344 bp = data->bps[i].retired_page; 345 346 /* There are two cases of reserve error should be ignored: 347 * 1) a ras bad page has been allocated (used by someone); 348 * 2) a ras bad page has been reserved (duplicate error injection 349 * for one page); 350 */ 351 if (ttm_resource_manager_used(man)) { 352 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr, 353 bp << AMDGPU_GPU_PAGE_SHIFT, 354 AMDGPU_GPU_PAGE_SIZE); 355 data->bps_bo[i] = NULL; 356 } else { 357 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, 358 AMDGPU_GPU_PAGE_SIZE, 359 &bo, NULL)) 360 DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp); 361 data->bps_bo[i] = bo; 362 } 363 data->last_reserved = i + 1; 364 bo = NULL; 365 } 366 } 367 368 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev, 369 uint64_t retired_page) 370 { 371 struct amdgpu_virt *virt = &adev->virt; 372 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 373 int i; 374 375 if (!data) 376 return true; 377 378 for (i = 0; i < data->count; i++) 379 if (retired_page == data->bps[i].retired_page) 380 return true; 381 382 return false; 383 } 384 385 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev, 386 uint64_t bp_block_offset, uint32_t bp_block_size) 387 { 388 struct eeprom_table_record bp; 389 uint64_t retired_page; 390 uint32_t bp_idx, bp_cnt; 391 void *vram_usage_va = NULL; 392 393 if (adev->mman.fw_vram_usage_va) 394 vram_usage_va = adev->mman.fw_vram_usage_va; 395 else 396 vram_usage_va = adev->mman.drv_vram_usage_va; 397 398 memset(&bp, 0, sizeof(bp)); 399 400 if (bp_block_size) { 401 bp_cnt = bp_block_size / sizeof(uint64_t); 402 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) { 403 retired_page = *(uint64_t *)(vram_usage_va + 404 bp_block_offset + bp_idx * sizeof(uint64_t)); 405 bp.retired_page = retired_page; 406 407 if (amdgpu_virt_ras_check_bad_page(adev, retired_page)) 408 continue; 409 410 amdgpu_virt_ras_add_bps(adev, &bp, 1); 411 412 amdgpu_virt_ras_reserve_bps(adev); 413 } 414 } 415 } 416 417 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) 418 { 419 struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf; 420 uint32_t checksum; 421 uint32_t checkval; 422 423 uint32_t i; 424 uint32_t tmp; 425 426 if (adev->virt.fw_reserve.p_pf2vf == NULL) 427 return -EINVAL; 428 429 if (pf2vf_info->size > 1024) { 430 dev_err(adev->dev, "invalid pf2vf message size: 0x%x\n", pf2vf_info->size); 431 return -EINVAL; 432 } 433 434 switch (pf2vf_info->version) { 435 case 1: 436 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum; 437 checkval = amd_sriov_msg_checksum( 438 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 439 adev->virt.fw_reserve.checksum_key, checksum); 440 if (checksum != checkval) { 441 dev_err(adev->dev, 442 "invalid pf2vf message: header checksum=0x%x calculated checksum=0x%x\n", 443 checksum, checkval); 444 return -EINVAL; 445 } 446 447 adev->virt.gim_feature = 448 ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags; 449 break; 450 case 2: 451 /* TODO: missing key, need to add it later */ 452 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum; 453 checkval = amd_sriov_msg_checksum( 454 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 455 0, checksum); 456 if (checksum != checkval) { 457 dev_err(adev->dev, 458 "invalid pf2vf message: header checksum=0x%x calculated checksum=0x%x\n", 459 checksum, checkval); 460 return -EINVAL; 461 } 462 463 adev->virt.vf2pf_update_interval_ms = 464 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms; 465 adev->virt.gim_feature = 466 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all; 467 adev->virt.reg_access = 468 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all; 469 470 adev->virt.decode_max_dimension_pixels = 0; 471 adev->virt.decode_max_frame_pixels = 0; 472 adev->virt.encode_max_dimension_pixels = 0; 473 adev->virt.encode_max_frame_pixels = 0; 474 adev->virt.is_mm_bw_enabled = false; 475 for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) { 476 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels; 477 adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels); 478 479 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels; 480 adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels); 481 482 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels; 483 adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels); 484 485 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels; 486 adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels); 487 } 488 if ((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0)) 489 adev->virt.is_mm_bw_enabled = true; 490 491 adev->unique_id = 492 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid; 493 break; 494 default: 495 dev_err(adev->dev, "invalid pf2vf version: 0x%x\n", pf2vf_info->version); 496 return -EINVAL; 497 } 498 499 /* correct too large or too little interval value */ 500 if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000) 501 adev->virt.vf2pf_update_interval_ms = 2000; 502 503 return 0; 504 } 505 506 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev) 507 { 508 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 509 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 510 511 if (adev->virt.fw_reserve.p_vf2pf == NULL) 512 return; 513 514 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version); 515 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version); 516 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version); 517 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); 518 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); 519 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); 520 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); 521 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); 522 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); 523 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); 524 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); 525 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); 526 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version); 527 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD, 528 adev->psp.asd_context.bin_desc.fw_version); 529 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS, 530 adev->psp.ras_context.context.bin_desc.fw_version); 531 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI, 532 adev->psp.xgmi_context.context.bin_desc.fw_version); 533 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version); 534 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version); 535 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version); 536 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version); 537 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version); 538 } 539 540 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) 541 { 542 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 543 544 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 545 546 if (adev->virt.fw_reserve.p_vf2pf == NULL) 547 return -EINVAL; 548 549 memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info)); 550 551 vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info); 552 vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER; 553 554 #ifdef MODULE 555 if (THIS_MODULE->version != NULL) 556 strcpy(vf2pf_info->driver_version, THIS_MODULE->version); 557 else 558 #endif 559 strcpy(vf2pf_info->driver_version, "N/A"); 560 561 vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all 562 vf2pf_info->driver_cert = 0; 563 vf2pf_info->os_info.all = 0; 564 565 vf2pf_info->fb_usage = 566 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20; 567 vf2pf_info->fb_vis_usage = 568 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20; 569 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20; 570 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20; 571 572 amdgpu_virt_populate_vf2pf_ucode_info(adev); 573 574 /* TODO: read dynamic info */ 575 vf2pf_info->gfx_usage = 0; 576 vf2pf_info->compute_usage = 0; 577 vf2pf_info->encode_usage = 0; 578 vf2pf_info->decode_usage = 0; 579 580 vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr; 581 vf2pf_info->mes_info_addr = (uint64_t)adev->mes.resource_1_gpu_addr; 582 583 if (adev->mes.resource_1) { 584 vf2pf_info->mes_info_size = adev->mes.resource_1->tbo.base.size; 585 } 586 vf2pf_info->checksum = 587 amd_sriov_msg_checksum( 588 vf2pf_info, sizeof(*vf2pf_info), 0, 0); 589 590 return 0; 591 } 592 593 static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work) 594 { 595 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work); 596 int ret; 597 598 ret = amdgpu_virt_read_pf2vf_data(adev); 599 if (ret) { 600 adev->virt.vf2pf_update_retry_cnt++; 601 if ((adev->virt.vf2pf_update_retry_cnt >= AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT) && 602 amdgpu_sriov_runtime(adev)) { 603 amdgpu_ras_set_fed(adev, true); 604 if (amdgpu_reset_domain_schedule(adev->reset_domain, 605 &adev->virt.flr_work)) 606 return; 607 else 608 dev_err(adev->dev, "Failed to queue work! at %s", __func__); 609 } 610 611 goto out; 612 } 613 614 adev->virt.vf2pf_update_retry_cnt = 0; 615 amdgpu_virt_write_vf2pf_data(adev); 616 617 out: 618 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); 619 } 620 621 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev) 622 { 623 if (adev->virt.vf2pf_update_interval_ms != 0) { 624 DRM_INFO("clean up the vf2pf work item\n"); 625 cancel_delayed_work_sync(&adev->virt.vf2pf_work); 626 adev->virt.vf2pf_update_interval_ms = 0; 627 } 628 } 629 630 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) 631 { 632 adev->virt.fw_reserve.p_pf2vf = NULL; 633 adev->virt.fw_reserve.p_vf2pf = NULL; 634 adev->virt.vf2pf_update_interval_ms = 0; 635 adev->virt.vf2pf_update_retry_cnt = 0; 636 637 if (adev->mman.fw_vram_usage_va && adev->mman.drv_vram_usage_va) { 638 DRM_WARN("Currently fw_vram and drv_vram should not have values at the same time!"); 639 } else if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { 640 /* go through this logic in ip_init and reset to init workqueue*/ 641 amdgpu_virt_exchange_data(adev); 642 643 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item); 644 schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms)); 645 } else if (adev->bios != NULL) { 646 /* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/ 647 adev->virt.fw_reserve.p_pf2vf = 648 (struct amd_sriov_msg_pf2vf_info_header *) 649 (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 650 651 amdgpu_virt_read_pf2vf_data(adev); 652 } 653 } 654 655 656 void amdgpu_virt_exchange_data(struct amdgpu_device *adev) 657 { 658 uint64_t bp_block_offset = 0; 659 uint32_t bp_block_size = 0; 660 struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL; 661 662 if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { 663 if (adev->mman.fw_vram_usage_va) { 664 adev->virt.fw_reserve.p_pf2vf = 665 (struct amd_sriov_msg_pf2vf_info_header *) 666 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 667 adev->virt.fw_reserve.p_vf2pf = 668 (struct amd_sriov_msg_vf2pf_info_header *) 669 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 670 } else if (adev->mman.drv_vram_usage_va) { 671 adev->virt.fw_reserve.p_pf2vf = 672 (struct amd_sriov_msg_pf2vf_info_header *) 673 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 674 adev->virt.fw_reserve.p_vf2pf = 675 (struct amd_sriov_msg_vf2pf_info_header *) 676 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 677 } 678 679 amdgpu_virt_read_pf2vf_data(adev); 680 amdgpu_virt_write_vf2pf_data(adev); 681 682 /* bad page handling for version 2 */ 683 if (adev->virt.fw_reserve.p_pf2vf->version == 2) { 684 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf; 685 686 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) | 687 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000); 688 bp_block_size = pf2vf_v2->bp_block_size; 689 690 if (bp_block_size && !adev->virt.ras_init_done) 691 amdgpu_virt_init_ras_err_handler_data(adev); 692 693 if (adev->virt.ras_init_done) 694 amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size); 695 } 696 } 697 } 698 699 void amdgpu_detect_virtualization(struct amdgpu_device *adev) 700 { 701 uint32_t reg; 702 703 switch (adev->asic_type) { 704 case CHIP_TONGA: 705 case CHIP_FIJI: 706 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); 707 break; 708 case CHIP_VEGA10: 709 case CHIP_VEGA20: 710 case CHIP_NAVI10: 711 case CHIP_NAVI12: 712 case CHIP_SIENNA_CICHLID: 713 case CHIP_ARCTURUS: 714 case CHIP_ALDEBARAN: 715 case CHIP_IP_DISCOVERY: 716 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER); 717 break; 718 default: /* other chip doesn't support SRIOV */ 719 reg = 0; 720 break; 721 } 722 723 if (reg & 1) 724 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 725 726 if (reg & 0x80000000) 727 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 728 729 if (!reg) { 730 /* passthrough mode exclus sriov mod */ 731 if (is_virtual_machine() && !xen_initial_domain()) 732 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 733 } 734 735 /* we have the ability to check now */ 736 if (amdgpu_sriov_vf(adev)) { 737 switch (adev->asic_type) { 738 case CHIP_TONGA: 739 case CHIP_FIJI: 740 vi_set_virt_ops(adev); 741 break; 742 case CHIP_VEGA10: 743 soc15_set_virt_ops(adev); 744 #ifdef CONFIG_X86 745 /* not send GPU_INIT_DATA with MS_HYPERV*/ 746 if (!hypervisor_is_type(X86_HYPER_MS_HYPERV)) 747 #endif 748 /* send a dummy GPU_INIT_DATA request to host on vega10 */ 749 amdgpu_virt_request_init_data(adev); 750 break; 751 case CHIP_VEGA20: 752 case CHIP_ARCTURUS: 753 case CHIP_ALDEBARAN: 754 soc15_set_virt_ops(adev); 755 break; 756 case CHIP_NAVI10: 757 case CHIP_NAVI12: 758 case CHIP_SIENNA_CICHLID: 759 case CHIP_IP_DISCOVERY: 760 nv_set_virt_ops(adev); 761 /* try send GPU_INIT_DATA request to host */ 762 amdgpu_virt_request_init_data(adev); 763 break; 764 default: /* other chip doesn't support SRIOV */ 765 DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type); 766 break; 767 } 768 } 769 } 770 771 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev) 772 { 773 return amdgpu_sriov_is_debug(adev) ? true : false; 774 } 775 776 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev) 777 { 778 return amdgpu_sriov_is_normal(adev) ? true : false; 779 } 780 781 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev) 782 { 783 if (!amdgpu_sriov_vf(adev) || 784 amdgpu_virt_access_debugfs_is_kiq(adev)) 785 return 0; 786 787 if (amdgpu_virt_access_debugfs_is_mmio(adev)) 788 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 789 else 790 return -EPERM; 791 792 return 0; 793 } 794 795 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev) 796 { 797 if (amdgpu_sriov_vf(adev)) 798 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 799 } 800 801 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev) 802 { 803 enum amdgpu_sriov_vf_mode mode; 804 805 if (amdgpu_sriov_vf(adev)) { 806 if (amdgpu_sriov_is_pp_one_vf(adev)) 807 mode = SRIOV_VF_MODE_ONE_VF; 808 else 809 mode = SRIOV_VF_MODE_MULTI_VF; 810 } else { 811 mode = SRIOV_VF_MODE_BARE_METAL; 812 } 813 814 return mode; 815 } 816 817 void amdgpu_virt_post_reset(struct amdgpu_device *adev) 818 { 819 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3)) { 820 /* force set to GFXOFF state after reset, 821 * to avoid some invalid operation before GC enable 822 */ 823 adev->gfx.is_poweron = false; 824 } 825 } 826 827 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id) 828 { 829 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 830 case IP_VERSION(13, 0, 0): 831 /* no vf autoload, white list */ 832 if (ucode_id == AMDGPU_UCODE_ID_VCN1 || 833 ucode_id == AMDGPU_UCODE_ID_VCN) 834 return false; 835 else 836 return true; 837 case IP_VERSION(11, 0, 9): 838 case IP_VERSION(11, 0, 7): 839 /* black list for CHIP_NAVI12 and CHIP_SIENNA_CICHLID */ 840 if (ucode_id == AMDGPU_UCODE_ID_RLC_G 841 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 842 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 843 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 844 || ucode_id == AMDGPU_UCODE_ID_SMC) 845 return true; 846 else 847 return false; 848 case IP_VERSION(13, 0, 10): 849 /* white list */ 850 if (ucode_id == AMDGPU_UCODE_ID_CAP 851 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP 852 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME 853 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC 854 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK 855 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK 856 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK 857 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK 858 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK 859 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK 860 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK 861 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK 862 || ucode_id == AMDGPU_UCODE_ID_CP_MES 863 || ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA 864 || ucode_id == AMDGPU_UCODE_ID_CP_MES1 865 || ucode_id == AMDGPU_UCODE_ID_CP_MES1_DATA 866 || ucode_id == AMDGPU_UCODE_ID_VCN1 867 || ucode_id == AMDGPU_UCODE_ID_VCN) 868 return false; 869 else 870 return true; 871 default: 872 /* lagacy black list */ 873 if (ucode_id == AMDGPU_UCODE_ID_SDMA0 874 || ucode_id == AMDGPU_UCODE_ID_SDMA1 875 || ucode_id == AMDGPU_UCODE_ID_SDMA2 876 || ucode_id == AMDGPU_UCODE_ID_SDMA3 877 || ucode_id == AMDGPU_UCODE_ID_SDMA4 878 || ucode_id == AMDGPU_UCODE_ID_SDMA5 879 || ucode_id == AMDGPU_UCODE_ID_SDMA6 880 || ucode_id == AMDGPU_UCODE_ID_SDMA7 881 || ucode_id == AMDGPU_UCODE_ID_RLC_G 882 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 883 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 884 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 885 || ucode_id == AMDGPU_UCODE_ID_SMC) 886 return true; 887 else 888 return false; 889 } 890 } 891 892 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 893 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 894 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size) 895 { 896 uint32_t i; 897 898 if (!adev->virt.is_mm_bw_enabled) 899 return; 900 901 if (encode) { 902 for (i = 0; i < encode_array_size; i++) { 903 encode[i].max_width = adev->virt.encode_max_dimension_pixels; 904 encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels; 905 if (encode[i].max_width > 0) 906 encode[i].max_height = encode[i].max_pixels_per_frame / encode[i].max_width; 907 else 908 encode[i].max_height = 0; 909 } 910 } 911 912 if (decode) { 913 for (i = 0; i < decode_array_size; i++) { 914 decode[i].max_width = adev->virt.decode_max_dimension_pixels; 915 decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels; 916 if (decode[i].max_width > 0) 917 decode[i].max_height = decode[i].max_pixels_per_frame / decode[i].max_width; 918 else 919 decode[i].max_height = 0; 920 } 921 } 922 } 923 924 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 925 u32 acc_flags, u32 hwip, 926 bool write, u32 *rlcg_flag) 927 { 928 bool ret = false; 929 930 switch (hwip) { 931 case GC_HWIP: 932 if (amdgpu_sriov_reg_indirect_gc(adev)) { 933 *rlcg_flag = 934 write ? AMDGPU_RLCG_GC_WRITE : AMDGPU_RLCG_GC_READ; 935 ret = true; 936 /* only in new version, AMDGPU_REGS_NO_KIQ and 937 * AMDGPU_REGS_RLC are enabled simultaneously */ 938 } else if ((acc_flags & AMDGPU_REGS_RLC) && 939 !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) { 940 *rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY; 941 ret = true; 942 } 943 break; 944 case MMHUB_HWIP: 945 if (amdgpu_sriov_reg_indirect_mmhub(adev) && 946 (acc_flags & AMDGPU_REGS_RLC) && write) { 947 *rlcg_flag = AMDGPU_RLCG_MMHUB_WRITE; 948 ret = true; 949 } 950 break; 951 default: 952 break; 953 } 954 return ret; 955 } 956 957 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id) 958 { 959 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 960 uint32_t timeout = 50000; 961 uint32_t i, tmp; 962 uint32_t ret = 0; 963 void *scratch_reg0; 964 void *scratch_reg1; 965 void *scratch_reg2; 966 void *scratch_reg3; 967 void *spare_int; 968 969 if (!adev->gfx.rlc.rlcg_reg_access_supported) { 970 dev_err(adev->dev, 971 "indirect registers access through rlcg is not available\n"); 972 return 0; 973 } 974 975 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { 976 dev_err(adev->dev, "invalid xcc\n"); 977 return 0; 978 } 979 980 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; 981 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0; 982 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1; 983 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; 984 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3; 985 if (reg_access_ctrl->spare_int) 986 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int; 987 988 if (offset == reg_access_ctrl->grbm_cntl) { 989 /* if the target reg offset is grbm_cntl, write to scratch_reg2 */ 990 writel(v, scratch_reg2); 991 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY) 992 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 993 } else if (offset == reg_access_ctrl->grbm_idx) { 994 /* if the target reg offset is grbm_idx, write to scratch_reg3 */ 995 writel(v, scratch_reg3); 996 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY) 997 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 998 } else { 999 /* 1000 * SCRATCH_REG0 = read/write value 1001 * SCRATCH_REG1[30:28] = command 1002 * SCRATCH_REG1[19:0] = address in dword 1003 * SCRATCH_REG1[27:24] = Error reporting 1004 */ 1005 writel(v, scratch_reg0); 1006 writel((offset | flag), scratch_reg1); 1007 if (reg_access_ctrl->spare_int) 1008 writel(1, spare_int); 1009 1010 for (i = 0; i < timeout; i++) { 1011 tmp = readl(scratch_reg1); 1012 if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK)) 1013 break; 1014 udelay(10); 1015 } 1016 1017 tmp = readl(scratch_reg1); 1018 if (i >= timeout || (tmp & AMDGPU_RLCG_SCRATCH1_ERROR_MASK) != 0) { 1019 if (amdgpu_sriov_rlcg_error_report_enabled(adev)) { 1020 if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) { 1021 dev_err(adev->dev, 1022 "vfgate is disabled, rlcg failed to program reg: 0x%05x\n", offset); 1023 } else if (tmp & AMDGPU_RLCG_WRONG_OPERATION_TYPE) { 1024 dev_err(adev->dev, 1025 "wrong operation type, rlcg failed to program reg: 0x%05x\n", offset); 1026 } else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) { 1027 dev_err(adev->dev, 1028 "register is not in range, rlcg failed to program reg: 0x%05x\n", offset); 1029 } else { 1030 dev_err(adev->dev, 1031 "unknown error type, rlcg failed to program reg: 0x%05x\n", offset); 1032 } 1033 } else { 1034 dev_err(adev->dev, 1035 "timeout: rlcg faled to program reg: 0x%05x\n", offset); 1036 } 1037 } 1038 } 1039 1040 ret = readl(scratch_reg0); 1041 return ret; 1042 } 1043 1044 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 1045 u32 offset, u32 value, 1046 u32 acc_flags, u32 hwip, u32 xcc_id) 1047 { 1048 u32 rlcg_flag; 1049 1050 if (!amdgpu_sriov_runtime(adev) && 1051 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) { 1052 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag, xcc_id); 1053 return; 1054 } 1055 1056 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1057 WREG32_NO_KIQ(offset, value); 1058 else 1059 WREG32(offset, value); 1060 } 1061 1062 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 1063 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id) 1064 { 1065 u32 rlcg_flag; 1066 1067 if (!amdgpu_sriov_runtime(adev) && 1068 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag)) 1069 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag, xcc_id); 1070 1071 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1072 return RREG32_NO_KIQ(offset); 1073 else 1074 return RREG32(offset); 1075 } 1076 1077 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev) 1078 { 1079 bool xnack_mode = true; 1080 1081 if (amdgpu_sriov_vf(adev) && 1082 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 1083 xnack_mode = false; 1084 1085 return xnack_mode; 1086 } 1087