1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/module.h> 25 26 #ifdef CONFIG_X86 27 #include <asm/hypervisor.h> 28 #endif 29 30 #include <drm/drm_drv.h> 31 #include <xen/xen.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_ras.h" 35 #include "amdgpu_reset.h" 36 #include "amdgpu_dpm.h" 37 #include "vi.h" 38 #include "soc15.h" 39 #include "nv.h" 40 #include "amdgpu_virt_ras_cmd.h" 41 42 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \ 43 do { \ 44 vf2pf_info->ucode_info[ucode].id = ucode; \ 45 vf2pf_info->ucode_info[ucode].version = ver; \ 46 } while (0) 47 48 #define mmRCC_CONFIG_MEMSIZE 0xde3 49 50 const char *amdgpu_virt_dynamic_crit_table_name[] = { 51 "IP DISCOVERY", 52 "VBIOS IMG", 53 "RAS TELEMETRY", 54 "DATA EXCHANGE", 55 "BAD PAGE INFO", 56 "INIT HEADER", 57 "LAST", 58 }; 59 60 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) 61 { 62 /* By now all MMIO pages except mailbox are blocked */ 63 /* if blocking is enabled in hypervisor. Choose the */ 64 /* SCRATCH_REG0 to test. */ 65 return RREG32_NO_KIQ(0xc040) == 0xffffffff; 66 } 67 68 void amdgpu_virt_init_setting(struct amdgpu_device *adev) 69 { 70 struct drm_device *ddev = adev_to_drm(adev); 71 72 /* enable virtual display */ 73 if (adev->asic_type != CHIP_ALDEBARAN && 74 adev->asic_type != CHIP_ARCTURUS && 75 ((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) { 76 if (adev->mode_info.num_crtc == 0) 77 adev->mode_info.num_crtc = 1; 78 adev->enable_virtual_display = true; 79 } 80 ddev->driver_features &= ~DRIVER_ATOMIC; 81 adev->cg_flags = 0; 82 adev->pg_flags = 0; 83 84 /* Reduce kcq number to 2 to reduce latency */ 85 if (amdgpu_num_kcq == -1) 86 amdgpu_num_kcq = 2; 87 } 88 89 /** 90 * amdgpu_virt_request_full_gpu() - request full gpu access 91 * @adev: amdgpu device. 92 * @init: is driver init time. 93 * When start to init/fini driver, first need to request full gpu access. 94 * Return: Zero if request success, otherwise will return error. 95 */ 96 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init) 97 { 98 struct amdgpu_virt *virt = &adev->virt; 99 int r; 100 101 if (virt->ops && virt->ops->req_full_gpu) { 102 r = virt->ops->req_full_gpu(adev, init); 103 if (r) { 104 adev->no_hw_access = true; 105 return r; 106 } 107 108 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 109 } 110 111 return 0; 112 } 113 114 /** 115 * amdgpu_virt_release_full_gpu() - release full gpu access 116 * @adev: amdgpu device. 117 * @init: is driver init time. 118 * When finishing driver init/fini, need to release full gpu access. 119 * Return: Zero if release success, otherwise will returen error. 120 */ 121 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init) 122 { 123 struct amdgpu_virt *virt = &adev->virt; 124 int r; 125 126 if (virt->ops && virt->ops->rel_full_gpu) { 127 r = virt->ops->rel_full_gpu(adev, init); 128 if (r) 129 return r; 130 131 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 132 } 133 return 0; 134 } 135 136 /** 137 * amdgpu_virt_reset_gpu() - reset gpu 138 * @adev: amdgpu device. 139 * Send reset command to GPU hypervisor to reset GPU that VM is using 140 * Return: Zero if reset success, otherwise will return error. 141 */ 142 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev) 143 { 144 struct amdgpu_virt *virt = &adev->virt; 145 int r; 146 147 if (virt->ops && virt->ops->reset_gpu) { 148 r = virt->ops->reset_gpu(adev); 149 if (r) 150 return r; 151 152 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 153 } 154 155 return 0; 156 } 157 158 void amdgpu_virt_request_init_data(struct amdgpu_device *adev) 159 { 160 struct amdgpu_virt *virt = &adev->virt; 161 162 if (virt->ops && virt->ops->req_init_data) 163 virt->ops->req_init_data(adev); 164 165 if (adev->virt.req_init_data_ver > 0) 166 dev_info(adev->dev, "host supports REQ_INIT_DATA handshake of critical_region_version %d\n", 167 adev->virt.req_init_data_ver); 168 else 169 dev_warn(adev->dev, "host doesn't support REQ_INIT_DATA handshake\n"); 170 } 171 172 /** 173 * amdgpu_virt_ready_to_reset() - send ready to reset to host 174 * @adev: amdgpu device. 175 * Send ready to reset message to GPU hypervisor to signal we have stopped GPU 176 * activity and is ready for host FLR 177 */ 178 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev) 179 { 180 struct amdgpu_virt *virt = &adev->virt; 181 182 if (virt->ops && virt->ops->reset_gpu) 183 virt->ops->ready_to_reset(adev); 184 } 185 186 /** 187 * amdgpu_virt_wait_reset() - wait for reset gpu completed 188 * @adev: amdgpu device. 189 * Wait for GPU reset completed. 190 * Return: Zero if reset success, otherwise will return error. 191 */ 192 int amdgpu_virt_wait_reset(struct amdgpu_device *adev) 193 { 194 struct amdgpu_virt *virt = &adev->virt; 195 196 if (!virt->ops || !virt->ops->wait_reset) 197 return -EINVAL; 198 199 return virt->ops->wait_reset(adev); 200 } 201 202 /** 203 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table 204 * @adev: amdgpu device. 205 * MM table is used by UVD and VCE for its initialization 206 * Return: Zero if allocate success. 207 */ 208 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev) 209 { 210 int r; 211 212 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) 213 return 0; 214 215 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 216 AMDGPU_GEM_DOMAIN_VRAM | 217 AMDGPU_GEM_DOMAIN_GTT, 218 &adev->virt.mm_table.bo, 219 &adev->virt.mm_table.gpu_addr, 220 (void *)&adev->virt.mm_table.cpu_addr); 221 if (r) { 222 dev_err(adev->dev, "failed to alloc mm table and error = %d.\n", r); 223 return r; 224 } 225 226 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); 227 dev_info(adev->dev, "MM table gpu addr = 0x%llx, cpu addr = %p.\n", 228 adev->virt.mm_table.gpu_addr, 229 adev->virt.mm_table.cpu_addr); 230 return 0; 231 } 232 233 /** 234 * amdgpu_virt_free_mm_table() - free mm table memory 235 * @adev: amdgpu device. 236 * Free MM table memory 237 */ 238 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev) 239 { 240 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) 241 return; 242 243 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo, 244 &adev->virt.mm_table.gpu_addr, 245 (void *)&adev->virt.mm_table.cpu_addr); 246 adev->virt.mm_table.gpu_addr = 0; 247 } 248 249 /** 250 * amdgpu_virt_rcvd_ras_interrupt() - receive ras interrupt 251 * @adev: amdgpu device. 252 * Check whether host sent RAS error message 253 * Return: true if found, otherwise false 254 */ 255 bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev) 256 { 257 struct amdgpu_virt *virt = &adev->virt; 258 259 if (!virt->ops || !virt->ops->rcvd_ras_intr) 260 return false; 261 262 return virt->ops->rcvd_ras_intr(adev); 263 } 264 265 266 unsigned int amd_sriov_msg_checksum(void *obj, 267 unsigned long obj_size, 268 unsigned int key, 269 unsigned int checksum) 270 { 271 unsigned int ret = key; 272 unsigned long i = 0; 273 unsigned char *pos; 274 275 pos = (char *)obj; 276 /* calculate checksum */ 277 for (i = 0; i < obj_size; ++i) 278 ret += *(pos + i); 279 /* minus the checksum itself */ 280 pos = (char *)&checksum; 281 for (i = 0; i < sizeof(checksum); ++i) 282 ret -= *(pos + i); 283 return ret; 284 } 285 286 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev) 287 { 288 struct amdgpu_virt *virt = &adev->virt; 289 struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data; 290 /* GPU will be marked bad on host if bp count more then 10, 291 * so alloc 512 is enough. 292 */ 293 unsigned int align_space = 512; 294 void *bps = NULL; 295 struct amdgpu_bo **bps_bo = NULL; 296 297 *data = kmalloc_obj(struct amdgpu_virt_ras_err_handler_data); 298 if (!*data) 299 goto data_failure; 300 301 bps = kmalloc_objs(*(*data)->bps, align_space); 302 if (!bps) 303 goto bps_failure; 304 305 bps_bo = kmalloc_objs(*(*data)->bps_bo, align_space); 306 if (!bps_bo) 307 goto bps_bo_failure; 308 309 (*data)->bps = bps; 310 (*data)->bps_bo = bps_bo; 311 (*data)->count = 0; 312 (*data)->last_reserved = 0; 313 314 virt->ras_init_done = true; 315 316 return 0; 317 318 bps_bo_failure: 319 kfree(bps); 320 bps_failure: 321 kfree(*data); 322 data_failure: 323 return -ENOMEM; 324 } 325 326 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev) 327 { 328 struct amdgpu_virt *virt = &adev->virt; 329 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 330 struct amdgpu_bo *bo; 331 int i; 332 333 if (!data) 334 return; 335 336 for (i = data->last_reserved - 1; i >= 0; i--) { 337 bo = data->bps_bo[i]; 338 if (bo) { 339 amdgpu_bo_free_kernel(&bo, NULL, NULL); 340 data->bps_bo[i] = bo; 341 } 342 data->last_reserved = i; 343 } 344 } 345 346 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev) 347 { 348 struct amdgpu_virt *virt = &adev->virt; 349 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 350 351 virt->ras_init_done = false; 352 353 if (!data) 354 return; 355 356 amdgpu_virt_ras_release_bp(adev); 357 358 kfree(data->bps); 359 kfree(data->bps_bo); 360 kfree(data); 361 virt->virt_eh_data = NULL; 362 } 363 364 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev, 365 struct eeprom_table_record *bps, int pages) 366 { 367 struct amdgpu_virt *virt = &adev->virt; 368 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 369 370 if (!data) 371 return; 372 373 memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); 374 data->count += pages; 375 } 376 377 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev) 378 { 379 struct amdgpu_virt *virt = &adev->virt; 380 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 381 struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; 382 struct ttm_resource_manager *man = &mgr->manager; 383 struct amdgpu_bo *bo = NULL; 384 uint64_t bp; 385 int i; 386 387 if (!data) 388 return; 389 390 for (i = data->last_reserved; i < data->count; i++) { 391 bp = data->bps[i].retired_page; 392 393 /* There are two cases of reserve error should be ignored: 394 * 1) a ras bad page has been allocated (used by someone); 395 * 2) a ras bad page has been reserved (duplicate error injection 396 * for one page); 397 */ 398 if (ttm_resource_manager_used(man)) { 399 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr, 400 bp << AMDGPU_GPU_PAGE_SHIFT, 401 AMDGPU_GPU_PAGE_SIZE); 402 data->bps_bo[i] = NULL; 403 } else { 404 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, 405 AMDGPU_GPU_PAGE_SIZE, 406 &bo, NULL)) 407 dev_dbg(adev->dev, 408 "RAS WARN: reserve vram for retired page %llx fail\n", 409 bp); 410 data->bps_bo[i] = bo; 411 } 412 data->last_reserved = i + 1; 413 bo = NULL; 414 } 415 } 416 417 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev, 418 uint64_t retired_page) 419 { 420 struct amdgpu_virt *virt = &adev->virt; 421 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 422 int i; 423 424 if (!data) 425 return true; 426 427 for (i = 0; i < data->count; i++) 428 if (retired_page == data->bps[i].retired_page) 429 return true; 430 431 return false; 432 } 433 434 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev, 435 uint64_t bp_block_offset, uint32_t bp_block_size) 436 { 437 struct eeprom_table_record bp; 438 uint64_t retired_page; 439 uint32_t bp_idx, bp_cnt; 440 void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr; 441 void *vram_usage_va = fw_va ? fw_va : adev->mman.drv_vram_usage_va; 442 443 memset(&bp, 0, sizeof(bp)); 444 445 if (bp_block_size) { 446 bp_cnt = bp_block_size / sizeof(uint64_t); 447 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) { 448 retired_page = *(uint64_t *)(vram_usage_va + 449 bp_block_offset + bp_idx * sizeof(uint64_t)); 450 bp.retired_page = retired_page; 451 452 if (amdgpu_virt_ras_check_bad_page(adev, retired_page)) 453 continue; 454 455 amdgpu_virt_ras_add_bps(adev, &bp, 1); 456 457 amdgpu_virt_ras_reserve_bps(adev); 458 } 459 } 460 } 461 462 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) 463 { 464 struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf; 465 uint32_t checksum; 466 uint32_t checkval; 467 468 uint32_t i; 469 uint32_t tmp; 470 471 if (adev->virt.fw_reserve.p_pf2vf == NULL) 472 return -EINVAL; 473 474 if (pf2vf_info->size > 1024) { 475 dev_err(adev->dev, "invalid pf2vf message size: 0x%x\n", pf2vf_info->size); 476 return -EINVAL; 477 } 478 479 switch (pf2vf_info->version) { 480 case 1: 481 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum; 482 checkval = amd_sriov_msg_checksum( 483 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 484 adev->virt.fw_reserve.checksum_key, checksum); 485 if (checksum != checkval) { 486 dev_err(adev->dev, 487 "invalid pf2vf message: header checksum=0x%x calculated checksum=0x%x\n", 488 checksum, checkval); 489 return -EINVAL; 490 } 491 492 adev->virt.gim_feature = 493 ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags; 494 break; 495 case 2: 496 /* TODO: missing key, need to add it later */ 497 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum; 498 checkval = amd_sriov_msg_checksum( 499 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 500 0, checksum); 501 if (checksum != checkval) { 502 dev_err(adev->dev, 503 "invalid pf2vf message: header checksum=0x%x calculated checksum=0x%x\n", 504 checksum, checkval); 505 return -EINVAL; 506 } 507 508 adev->virt.vf2pf_update_interval_ms = 509 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms; 510 adev->virt.gim_feature = 511 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all; 512 adev->virt.reg_access = 513 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all; 514 515 adev->virt.decode_max_dimension_pixels = 0; 516 adev->virt.decode_max_frame_pixels = 0; 517 adev->virt.encode_max_dimension_pixels = 0; 518 adev->virt.encode_max_frame_pixels = 0; 519 adev->virt.is_mm_bw_enabled = false; 520 for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) { 521 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels; 522 adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels); 523 524 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels; 525 adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels); 526 527 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels; 528 adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels); 529 530 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels; 531 adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels); 532 } 533 if ((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0)) 534 adev->virt.is_mm_bw_enabled = true; 535 536 adev->unique_id = 537 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid; 538 adev->virt.ras_en_caps.all = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->ras_en_caps.all; 539 adev->virt.ras_telemetry_en_caps.all = 540 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->ras_telemetry_en_caps.all; 541 break; 542 default: 543 dev_err(adev->dev, "invalid pf2vf version: 0x%x\n", pf2vf_info->version); 544 return -EINVAL; 545 } 546 547 /* correct too large or too little interval value */ 548 if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000) 549 adev->virt.vf2pf_update_interval_ms = 2000; 550 551 return 0; 552 } 553 554 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev) 555 { 556 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 557 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 558 559 if (adev->virt.fw_reserve.p_vf2pf == NULL) 560 return; 561 562 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version); 563 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version); 564 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version); 565 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); 566 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); 567 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); 568 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); 569 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); 570 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); 571 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); 572 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); 573 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); 574 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version); 575 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD, 576 adev->psp.asd_context.bin_desc.fw_version); 577 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS, 578 adev->psp.ras_context.context.bin_desc.fw_version); 579 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI, 580 adev->psp.xgmi_context.context.bin_desc.fw_version); 581 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version); 582 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version); 583 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version); 584 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version); 585 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version); 586 } 587 588 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) 589 { 590 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 591 592 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 593 594 if (adev->virt.fw_reserve.p_vf2pf == NULL) 595 return -EINVAL; 596 597 memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info)); 598 599 vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info); 600 vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER; 601 602 #ifdef MODULE 603 if (THIS_MODULE->version != NULL) 604 strscpy(vf2pf_info->driver_version, THIS_MODULE->version); 605 else 606 #endif 607 strscpy(vf2pf_info->driver_version, "N/A"); 608 609 vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all 610 vf2pf_info->driver_cert = 0; 611 vf2pf_info->os_info.all = 0; 612 613 vf2pf_info->fb_usage = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? 614 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20 : 0; 615 vf2pf_info->fb_vis_usage = 616 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20; 617 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20; 618 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20; 619 620 amdgpu_virt_populate_vf2pf_ucode_info(adev); 621 622 /* TODO: read dynamic info */ 623 vf2pf_info->gfx_usage = 0; 624 vf2pf_info->compute_usage = 0; 625 vf2pf_info->encode_usage = 0; 626 vf2pf_info->decode_usage = 0; 627 628 vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr; 629 if (amdgpu_sriov_is_mes_info_enable(adev)) { 630 vf2pf_info->mes_info_addr = 631 (uint64_t)(adev->mes.resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE); 632 vf2pf_info->mes_info_size = 633 adev->mes.resource_1[0]->tbo.base.size - AMDGPU_GPU_PAGE_SIZE; 634 } 635 vf2pf_info->checksum = 636 amd_sriov_msg_checksum( 637 vf2pf_info, sizeof(*vf2pf_info), 0, 0); 638 639 return 0; 640 } 641 642 static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work) 643 { 644 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work); 645 int ret; 646 647 ret = amdgpu_virt_read_pf2vf_data(adev); 648 if (ret) { 649 adev->virt.vf2pf_update_retry_cnt++; 650 651 if ((amdgpu_virt_rcvd_ras_interrupt(adev) || 652 adev->virt.vf2pf_update_retry_cnt >= AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT) && 653 amdgpu_sriov_runtime(adev)) { 654 655 amdgpu_ras_set_fed(adev, true); 656 if (amdgpu_reset_domain_schedule(adev->reset_domain, 657 &adev->kfd.reset_work)) 658 return; 659 else 660 dev_err(adev->dev, "Failed to queue work! at %s", __func__); 661 } 662 663 goto out; 664 } 665 666 adev->virt.vf2pf_update_retry_cnt = 0; 667 amdgpu_virt_write_vf2pf_data(adev); 668 669 out: 670 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); 671 } 672 673 static int amdgpu_virt_read_exchange_data_from_mem(struct amdgpu_device *adev, uint32_t *pfvf_data) 674 { 675 uint32_t dataexchange_offset = 676 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset; 677 uint32_t dataexchange_size = 678 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].size_kb << 10; 679 uint64_t pos = 0; 680 681 dev_info(adev->dev, 682 "Got data exchange info from dynamic crit_region_table at offset 0x%x with size of 0x%x bytes.\n", 683 dataexchange_offset, dataexchange_size); 684 685 if (!IS_ALIGNED(dataexchange_offset, 4) || !IS_ALIGNED(dataexchange_size, 4)) { 686 dev_err(adev->dev, "Data exchange data not aligned to 4 bytes\n"); 687 return -EINVAL; 688 } 689 690 pos = (uint64_t)dataexchange_offset; 691 amdgpu_device_vram_access(adev, pos, pfvf_data, 692 dataexchange_size, false); 693 694 return 0; 695 } 696 697 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev) 698 { 699 if (adev->virt.vf2pf_update_interval_ms != 0) { 700 dev_info(adev->dev, "clean up the vf2pf work item\n"); 701 cancel_delayed_work_sync(&adev->virt.vf2pf_work); 702 adev->virt.vf2pf_update_interval_ms = 0; 703 } 704 } 705 706 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) 707 { 708 uint32_t *pfvf_data = NULL; 709 void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr; 710 711 adev->virt.fw_reserve.p_pf2vf = NULL; 712 adev->virt.fw_reserve.p_vf2pf = NULL; 713 adev->virt.vf2pf_update_interval_ms = 0; 714 adev->virt.vf2pf_update_retry_cnt = 0; 715 716 if (fw_va && adev->mman.drv_vram_usage_va) { 717 dev_warn(adev->dev, "Currently fw_vram and drv_vram should not have values at the same time!"); 718 } else if (fw_va || adev->mman.drv_vram_usage_va) { 719 /* go through this logic in ip_init and reset to init workqueue*/ 720 amdgpu_virt_exchange_data(adev); 721 722 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item); 723 schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms)); 724 } else if (adev->bios != NULL) { 725 /* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/ 726 if (adev->virt.req_init_data_ver == GPU_CRIT_REGION_V2) { 727 pfvf_data = 728 kzalloc(adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].size_kb << 10, 729 GFP_KERNEL); 730 if (!pfvf_data) { 731 dev_err(adev->dev, "Failed to allocate memory for pfvf_data\n"); 732 return; 733 } 734 735 if (amdgpu_virt_read_exchange_data_from_mem(adev, pfvf_data)) 736 goto free_pfvf_data; 737 738 adev->virt.fw_reserve.p_pf2vf = 739 (struct amd_sriov_msg_pf2vf_info_header *)pfvf_data; 740 741 amdgpu_virt_read_pf2vf_data(adev); 742 743 free_pfvf_data: 744 kfree(pfvf_data); 745 pfvf_data = NULL; 746 adev->virt.fw_reserve.p_pf2vf = NULL; 747 } else { 748 adev->virt.fw_reserve.p_pf2vf = 749 (struct amd_sriov_msg_pf2vf_info_header *) 750 (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); 751 752 amdgpu_virt_read_pf2vf_data(adev); 753 } 754 } 755 } 756 757 758 void amdgpu_virt_exchange_data(struct amdgpu_device *adev) 759 { 760 uint64_t bp_block_offset = 0; 761 uint32_t bp_block_size = 0; 762 struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL; 763 void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr; 764 765 if (fw_va || adev->mman.drv_vram_usage_va) { 766 if (fw_va) { 767 if (adev->virt.req_init_data_ver == GPU_CRIT_REGION_V2) { 768 adev->virt.fw_reserve.p_pf2vf = 769 (struct amd_sriov_msg_pf2vf_info_header *) 770 (fw_va + 771 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset); 772 adev->virt.fw_reserve.p_vf2pf = 773 (struct amd_sriov_msg_vf2pf_info_header *) 774 (fw_va + 775 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset + 776 (AMD_SRIOV_MSG_SIZE_KB << 10)); 777 adev->virt.fw_reserve.ras_telemetry = 778 (fw_va + 779 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID].offset); 780 } else { 781 adev->virt.fw_reserve.p_pf2vf = 782 (struct amd_sriov_msg_pf2vf_info_header *) 783 (fw_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); 784 adev->virt.fw_reserve.p_vf2pf = 785 (struct amd_sriov_msg_vf2pf_info_header *) 786 (fw_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 << 10)); 787 adev->virt.fw_reserve.ras_telemetry = 788 (fw_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 << 10)); 789 } 790 } else if (adev->mman.drv_vram_usage_va) { 791 adev->virt.fw_reserve.p_pf2vf = 792 (struct amd_sriov_msg_pf2vf_info_header *) 793 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); 794 adev->virt.fw_reserve.p_vf2pf = 795 (struct amd_sriov_msg_vf2pf_info_header *) 796 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 << 10)); 797 adev->virt.fw_reserve.ras_telemetry = 798 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 << 10)); 799 } 800 801 amdgpu_virt_read_pf2vf_data(adev); 802 amdgpu_virt_write_vf2pf_data(adev); 803 804 /* bad page handling for version 2 */ 805 if (adev->virt.fw_reserve.p_pf2vf->version == 2) { 806 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf; 807 808 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) | 809 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000); 810 bp_block_size = pf2vf_v2->bp_block_size; 811 812 if (bp_block_size && !adev->virt.ras_init_done) 813 amdgpu_virt_init_ras_err_handler_data(adev); 814 815 if (adev->virt.ras_init_done) 816 amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size); 817 } 818 } 819 } 820 821 static u32 amdgpu_virt_init_detect_asic(struct amdgpu_device *adev) 822 { 823 uint32_t reg; 824 825 switch (adev->asic_type) { 826 case CHIP_TONGA: 827 case CHIP_FIJI: 828 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); 829 break; 830 case CHIP_VEGA10: 831 case CHIP_VEGA20: 832 case CHIP_NAVI10: 833 case CHIP_NAVI12: 834 case CHIP_SIENNA_CICHLID: 835 case CHIP_ARCTURUS: 836 case CHIP_ALDEBARAN: 837 case CHIP_IP_DISCOVERY: 838 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER); 839 break; 840 default: /* other chip doesn't support SRIOV */ 841 reg = 0; 842 break; 843 } 844 845 if (reg & 1) 846 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 847 848 if (reg & 0x80000000) 849 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 850 851 if (!reg) { 852 /* passthrough mode exclus sriov mod */ 853 if (is_virtual_machine() && !xen_initial_domain()) 854 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 855 } 856 857 return reg; 858 } 859 860 static bool amdgpu_virt_init_req_data(struct amdgpu_device *adev, u32 reg) 861 { 862 bool is_sriov = false; 863 864 /* we have the ability to check now */ 865 if (amdgpu_sriov_vf(adev)) { 866 is_sriov = true; 867 868 switch (adev->asic_type) { 869 case CHIP_TONGA: 870 case CHIP_FIJI: 871 vi_set_virt_ops(adev); 872 break; 873 case CHIP_VEGA10: 874 soc15_set_virt_ops(adev); 875 #ifdef CONFIG_X86 876 /* not send GPU_INIT_DATA with MS_HYPERV*/ 877 if (!hypervisor_is_type(X86_HYPER_MS_HYPERV)) 878 #endif 879 /* send a dummy GPU_INIT_DATA request to host on vega10 */ 880 amdgpu_virt_request_init_data(adev); 881 break; 882 case CHIP_VEGA20: 883 case CHIP_ARCTURUS: 884 case CHIP_ALDEBARAN: 885 soc15_set_virt_ops(adev); 886 break; 887 case CHIP_NAVI10: 888 case CHIP_NAVI12: 889 case CHIP_SIENNA_CICHLID: 890 case CHIP_IP_DISCOVERY: 891 nv_set_virt_ops(adev); 892 /* try send GPU_INIT_DATA request to host */ 893 amdgpu_virt_request_init_data(adev); 894 break; 895 default: /* other chip doesn't support SRIOV */ 896 is_sriov = false; 897 dev_err(adev->dev, "Unknown asic type: %d!\n", adev->asic_type); 898 break; 899 } 900 } 901 902 return is_sriov; 903 } 904 905 static void amdgpu_virt_init_ras(struct amdgpu_device *adev) 906 { 907 ratelimit_state_init(&adev->virt.ras.ras_error_cnt_rs, 5 * HZ, 1); 908 ratelimit_state_init(&adev->virt.ras.ras_cper_dump_rs, 5 * HZ, 1); 909 ratelimit_state_init(&adev->virt.ras.ras_chk_criti_rs, 5 * HZ, 1); 910 911 ratelimit_set_flags(&adev->virt.ras.ras_error_cnt_rs, 912 RATELIMIT_MSG_ON_RELEASE); 913 ratelimit_set_flags(&adev->virt.ras.ras_cper_dump_rs, 914 RATELIMIT_MSG_ON_RELEASE); 915 ratelimit_set_flags(&adev->virt.ras.ras_chk_criti_rs, 916 RATELIMIT_MSG_ON_RELEASE); 917 918 mutex_init(&adev->virt.ras.ras_telemetry_mutex); 919 mutex_init(&adev->virt.access_req_mutex); 920 921 adev->virt.ras.cper_rptr = 0; 922 } 923 924 static uint8_t amdgpu_virt_crit_region_calc_checksum(uint8_t *buf_start, uint8_t *buf_end) 925 { 926 uint32_t sum = 0; 927 928 if (buf_start >= buf_end) 929 return 0; 930 931 for (; buf_start < buf_end; buf_start++) 932 sum += buf_start[0]; 933 934 return 0xffffffff - sum; 935 } 936 937 int amdgpu_virt_init_critical_region(struct amdgpu_device *adev) 938 { 939 struct amd_sriov_msg_init_data_header *init_data_hdr = NULL; 940 u64 init_hdr_offset = adev->virt.init_data_header.offset; 941 u64 init_hdr_size = (u64)adev->virt.init_data_header.size_kb << 10; /* KB → bytes */ 942 u64 vram_size; 943 u64 end; 944 int r = 0; 945 uint8_t checksum = 0; 946 947 /* Skip below init if critical region version != v2 */ 948 if (adev->virt.req_init_data_ver != GPU_CRIT_REGION_V2) 949 return 0; 950 951 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); 952 if (!vram_size || vram_size == U32_MAX) 953 return -EINVAL; 954 vram_size <<= 20; 955 956 if (check_add_overflow(init_hdr_offset, init_hdr_size, &end) || end > vram_size) { 957 dev_err(adev->dev, "init_data_header exceeds VRAM size, exiting\n"); 958 return -EINVAL; 959 } 960 961 /* Allocate for init_data_hdr */ 962 init_data_hdr = kzalloc_obj(struct amd_sriov_msg_init_data_header); 963 if (!init_data_hdr) 964 return -ENOMEM; 965 966 amdgpu_device_vram_access(adev, (uint64_t)init_hdr_offset, (uint32_t *)init_data_hdr, 967 sizeof(struct amd_sriov_msg_init_data_header), false); 968 969 /* Table validation */ 970 if (strncmp(init_data_hdr->signature, 971 AMDGPU_SRIOV_CRIT_DATA_SIGNATURE, 972 AMDGPU_SRIOV_CRIT_DATA_SIG_LEN) != 0) { 973 dev_err(adev->dev, "Invalid init data signature: %.4s\n", 974 init_data_hdr->signature); 975 r = -EINVAL; 976 goto out; 977 } 978 979 checksum = amdgpu_virt_crit_region_calc_checksum( 980 (uint8_t *)&init_data_hdr->initdata_offset, 981 (uint8_t *)init_data_hdr + 982 sizeof(struct amd_sriov_msg_init_data_header)); 983 if (checksum != init_data_hdr->checksum) { 984 dev_err(adev->dev, "Found unmatching checksum from calculation 0x%x and init_data 0x%x\n", 985 checksum, init_data_hdr->checksum); 986 r = -EINVAL; 987 goto out; 988 } 989 990 memset(&adev->virt.crit_regn, 0, sizeof(adev->virt.crit_regn)); 991 memset(adev->virt.crit_regn_tbl, 0, sizeof(adev->virt.crit_regn_tbl)); 992 993 adev->virt.crit_regn.offset = init_data_hdr->initdata_offset; 994 adev->virt.crit_regn.size_kb = init_data_hdr->initdata_size_in_kb; 995 996 /* Validation and initialization for each table entry */ 997 if (IS_SRIOV_CRIT_REGN_ENTRY_VALID(init_data_hdr, AMD_SRIOV_MSG_IPD_TABLE_ID)) { 998 if (!init_data_hdr->ip_discovery_size_in_kb || 999 init_data_hdr->ip_discovery_size_in_kb > DISCOVERY_TMR_SIZE) { 1000 dev_err(adev->dev, "Invalid %s size: 0x%x\n", 1001 amdgpu_virt_dynamic_crit_table_name[AMD_SRIOV_MSG_IPD_TABLE_ID], 1002 init_data_hdr->ip_discovery_size_in_kb); 1003 r = -EINVAL; 1004 goto out; 1005 } 1006 1007 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset = 1008 init_data_hdr->ip_discovery_offset; 1009 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb = 1010 init_data_hdr->ip_discovery_size_in_kb; 1011 } 1012 1013 if (IS_SRIOV_CRIT_REGN_ENTRY_VALID(init_data_hdr, AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID)) { 1014 if (!init_data_hdr->vbios_img_size_in_kb) { 1015 dev_err(adev->dev, "Invalid %s size: 0x%x\n", 1016 amdgpu_virt_dynamic_crit_table_name[AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID], 1017 init_data_hdr->vbios_img_size_in_kb); 1018 r = -EINVAL; 1019 goto out; 1020 } 1021 1022 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID].offset = 1023 init_data_hdr->vbios_img_offset; 1024 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID].size_kb = 1025 init_data_hdr->vbios_img_size_in_kb; 1026 } 1027 1028 if (IS_SRIOV_CRIT_REGN_ENTRY_VALID(init_data_hdr, AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID)) { 1029 if (!init_data_hdr->ras_tele_info_size_in_kb) { 1030 dev_err(adev->dev, "Invalid %s size: 0x%x\n", 1031 amdgpu_virt_dynamic_crit_table_name[AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID], 1032 init_data_hdr->ras_tele_info_size_in_kb); 1033 r = -EINVAL; 1034 goto out; 1035 } 1036 1037 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID].offset = 1038 init_data_hdr->ras_tele_info_offset; 1039 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID].size_kb = 1040 init_data_hdr->ras_tele_info_size_in_kb; 1041 } 1042 1043 if (IS_SRIOV_CRIT_REGN_ENTRY_VALID(init_data_hdr, AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID)) { 1044 if (!init_data_hdr->dataexchange_size_in_kb) { 1045 dev_err(adev->dev, "Invalid %s size: 0x%x\n", 1046 amdgpu_virt_dynamic_crit_table_name[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID], 1047 init_data_hdr->dataexchange_size_in_kb); 1048 r = -EINVAL; 1049 goto out; 1050 } 1051 1052 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset = 1053 init_data_hdr->dataexchange_offset; 1054 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].size_kb = 1055 init_data_hdr->dataexchange_size_in_kb; 1056 } 1057 1058 if (IS_SRIOV_CRIT_REGN_ENTRY_VALID(init_data_hdr, AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID)) { 1059 if (!init_data_hdr->bad_page_size_in_kb) { 1060 dev_err(adev->dev, "Invalid %s size: 0x%x\n", 1061 amdgpu_virt_dynamic_crit_table_name[AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID], 1062 init_data_hdr->bad_page_size_in_kb); 1063 r = -EINVAL; 1064 goto out; 1065 } 1066 1067 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID].offset = 1068 init_data_hdr->bad_page_info_offset; 1069 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID].size_kb = 1070 init_data_hdr->bad_page_size_in_kb; 1071 } 1072 1073 /* Validation for critical region info */ 1074 if (adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb > DISCOVERY_TMR_SIZE) { 1075 dev_err(adev->dev, "Invalid IP discovery size: 0x%x\n", 1076 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb); 1077 r = -EINVAL; 1078 goto out; 1079 } 1080 1081 /* reserved memory starts from crit region base offset with the size of 5MB */ 1082 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_VRAM_USAGE, 1083 adev->virt.crit_regn.offset, 1084 adev->virt.crit_regn.size_kb << 10, true); 1085 dev_info(adev->dev, 1086 "critical region v%d requested to reserve memory start at %08llx with %llu KB.\n", 1087 init_data_hdr->version, 1088 adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].offset, 1089 adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].size >> 10); 1090 1091 adev->virt.is_dynamic_crit_regn_enabled = true; 1092 1093 out: 1094 kfree(init_data_hdr); 1095 init_data_hdr = NULL; 1096 1097 return r; 1098 } 1099 1100 int amdgpu_virt_get_dynamic_data_info(struct amdgpu_device *adev, 1101 int data_id, uint8_t *binary, u32 *size) 1102 { 1103 uint32_t data_offset = 0; 1104 uint32_t data_size = 0; 1105 enum amd_sriov_msg_table_id_enum data_table_id = data_id; 1106 1107 if (data_table_id >= AMD_SRIOV_MSG_MAX_TABLE_ID) 1108 return -EINVAL; 1109 1110 data_offset = adev->virt.crit_regn_tbl[data_table_id].offset; 1111 data_size = adev->virt.crit_regn_tbl[data_table_id].size_kb << 10; 1112 1113 /* Validate on input params */ 1114 if (!binary || !size || *size < (uint64_t)data_size) 1115 return -EINVAL; 1116 1117 /* Proceed to copy the dynamic content */ 1118 amdgpu_device_vram_access(adev, 1119 (uint64_t)data_offset, (uint32_t *)binary, data_size, false); 1120 *size = (uint64_t)data_size; 1121 1122 dev_dbg(adev->dev, 1123 "Got %s info from dynamic crit_region_table at offset 0x%x with size of 0x%x bytes.\n", 1124 amdgpu_virt_dynamic_crit_table_name[data_id], data_offset, data_size); 1125 1126 return 0; 1127 } 1128 1129 void amdgpu_virt_init(struct amdgpu_device *adev) 1130 { 1131 bool is_sriov = false; 1132 uint32_t reg = amdgpu_virt_init_detect_asic(adev); 1133 1134 is_sriov = amdgpu_virt_init_req_data(adev, reg); 1135 1136 if (is_sriov) 1137 amdgpu_virt_init_ras(adev); 1138 } 1139 1140 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev) 1141 { 1142 return amdgpu_sriov_is_debug(adev) ? true : false; 1143 } 1144 1145 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev) 1146 { 1147 return amdgpu_sriov_is_normal(adev) ? true : false; 1148 } 1149 1150 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev) 1151 { 1152 if (!amdgpu_sriov_vf(adev) || 1153 amdgpu_virt_access_debugfs_is_kiq(adev)) 1154 return 0; 1155 1156 if (amdgpu_virt_access_debugfs_is_mmio(adev)) 1157 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 1158 else 1159 return -EPERM; 1160 1161 return 0; 1162 } 1163 1164 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev) 1165 { 1166 if (amdgpu_sriov_vf(adev)) 1167 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 1168 } 1169 1170 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev) 1171 { 1172 enum amdgpu_sriov_vf_mode mode; 1173 1174 if (amdgpu_sriov_vf(adev)) { 1175 if (amdgpu_sriov_is_pp_one_vf(adev)) 1176 mode = SRIOV_VF_MODE_ONE_VF; 1177 else 1178 mode = SRIOV_VF_MODE_MULTI_VF; 1179 } else { 1180 mode = SRIOV_VF_MODE_BARE_METAL; 1181 } 1182 1183 return mode; 1184 } 1185 1186 void amdgpu_virt_pre_reset(struct amdgpu_device *adev) 1187 { 1188 /* stop the data exchange thread */ 1189 amdgpu_virt_fini_data_exchange(adev); 1190 amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_FLR); 1191 } 1192 1193 void amdgpu_virt_post_reset(struct amdgpu_device *adev) 1194 { 1195 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3)) { 1196 /* force set to GFXOFF state after reset, 1197 * to avoid some invalid operation before GC enable 1198 */ 1199 adev->gfx.is_poweron = false; 1200 } 1201 1202 adev->mes.ring[0].sched.ready = false; 1203 } 1204 1205 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id) 1206 { 1207 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 1208 case IP_VERSION(13, 0, 0): 1209 /* no vf autoload, white list */ 1210 if (ucode_id == AMDGPU_UCODE_ID_VCN1 || 1211 ucode_id == AMDGPU_UCODE_ID_VCN) 1212 return false; 1213 else 1214 return true; 1215 case IP_VERSION(11, 0, 9): 1216 case IP_VERSION(11, 0, 7): 1217 /* black list for CHIP_NAVI12 and CHIP_SIENNA_CICHLID */ 1218 if (ucode_id == AMDGPU_UCODE_ID_RLC_G 1219 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 1220 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 1221 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 1222 || ucode_id == AMDGPU_UCODE_ID_SMC) 1223 return true; 1224 else 1225 return false; 1226 case IP_VERSION(13, 0, 10): 1227 /* white list */ 1228 if (ucode_id == AMDGPU_UCODE_ID_CAP 1229 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP 1230 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME 1231 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC 1232 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK 1233 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK 1234 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK 1235 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK 1236 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK 1237 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK 1238 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK 1239 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK 1240 || ucode_id == AMDGPU_UCODE_ID_CP_MES 1241 || ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA 1242 || ucode_id == AMDGPU_UCODE_ID_CP_MES1 1243 || ucode_id == AMDGPU_UCODE_ID_CP_MES1_DATA 1244 || ucode_id == AMDGPU_UCODE_ID_VCN1 1245 || ucode_id == AMDGPU_UCODE_ID_VCN) 1246 return false; 1247 else 1248 return true; 1249 default: 1250 /* lagacy black list */ 1251 if (ucode_id == AMDGPU_UCODE_ID_SDMA0 1252 || ucode_id == AMDGPU_UCODE_ID_SDMA1 1253 || ucode_id == AMDGPU_UCODE_ID_SDMA2 1254 || ucode_id == AMDGPU_UCODE_ID_SDMA3 1255 || ucode_id == AMDGPU_UCODE_ID_SDMA4 1256 || ucode_id == AMDGPU_UCODE_ID_SDMA5 1257 || ucode_id == AMDGPU_UCODE_ID_SDMA6 1258 || ucode_id == AMDGPU_UCODE_ID_SDMA7 1259 || ucode_id == AMDGPU_UCODE_ID_SDMA_RS64 1260 || ucode_id == AMDGPU_UCODE_ID_RLC_G 1261 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 1262 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 1263 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 1264 || ucode_id == AMDGPU_UCODE_ID_SMC) 1265 return true; 1266 else 1267 return false; 1268 } 1269 } 1270 1271 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 1272 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 1273 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size) 1274 { 1275 uint32_t i; 1276 1277 if (!adev->virt.is_mm_bw_enabled) 1278 return; 1279 1280 if (encode) { 1281 for (i = 0; i < encode_array_size; i++) { 1282 encode[i].max_width = adev->virt.encode_max_dimension_pixels; 1283 encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels; 1284 if (encode[i].max_width > 0) 1285 encode[i].max_height = encode[i].max_pixels_per_frame / encode[i].max_width; 1286 else 1287 encode[i].max_height = 0; 1288 } 1289 } 1290 1291 if (decode) { 1292 for (i = 0; i < decode_array_size; i++) { 1293 decode[i].max_width = adev->virt.decode_max_dimension_pixels; 1294 decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels; 1295 if (decode[i].max_width > 0) 1296 decode[i].max_height = decode[i].max_pixels_per_frame / decode[i].max_width; 1297 else 1298 decode[i].max_height = 0; 1299 } 1300 } 1301 } 1302 1303 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 1304 u32 acc_flags, u32 hwip, 1305 bool write, u32 *rlcg_flag) 1306 { 1307 bool ret = false; 1308 1309 switch (hwip) { 1310 case GC_HWIP: 1311 if (amdgpu_sriov_reg_indirect_gc(adev)) { 1312 *rlcg_flag = 1313 write ? AMDGPU_RLCG_GC_WRITE : AMDGPU_RLCG_GC_READ; 1314 ret = true; 1315 /* only in new version, AMDGPU_REGS_NO_KIQ and 1316 * AMDGPU_REGS_RLC are enabled simultaneously */ 1317 } else if ((acc_flags & AMDGPU_REGS_RLC) && 1318 !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) { 1319 *rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY; 1320 ret = true; 1321 } 1322 break; 1323 case MMHUB_HWIP: 1324 if (amdgpu_sriov_reg_indirect_mmhub(adev) && 1325 (acc_flags & AMDGPU_REGS_RLC) && write) { 1326 *rlcg_flag = AMDGPU_RLCG_MMHUB_WRITE; 1327 ret = true; 1328 } 1329 break; 1330 default: 1331 break; 1332 } 1333 return ret; 1334 } 1335 1336 static u32 amdgpu_virt_rlcg_vfi_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id) 1337 { 1338 uint32_t timeout = 100; 1339 uint32_t i; 1340 1341 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1342 void *vfi_cmd; 1343 void *vfi_stat; 1344 void *vfi_addr; 1345 void *vfi_data; 1346 void *vfi_grbm_cntl; 1347 void *vfi_grbm_idx; 1348 uint32_t cmd; 1349 uint32_t stat; 1350 uint32_t addr = offset; 1351 uint32_t data; 1352 uint32_t grbm_cntl_data; 1353 uint32_t grbm_idx_data; 1354 1355 unsigned long flags; 1356 bool is_err = true; 1357 1358 if (!adev->gfx.rlc.rlcg_reg_access_supported) { 1359 dev_err(adev->dev, "VFi interface is not available\n"); 1360 return 0; 1361 } 1362 1363 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { 1364 dev_err(adev->dev, "VFi invalid XCC, xcc_id=0x%x\n", xcc_id); 1365 return 0; 1366 } 1367 1368 if (amdgpu_device_skip_hw_access(adev)) 1369 return 0; 1370 1371 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; 1372 vfi_cmd = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_cmd; 1373 vfi_stat = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_stat; 1374 vfi_addr = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_addr; 1375 vfi_data = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_data; 1376 vfi_grbm_cntl = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_grbm_cntl; 1377 vfi_grbm_idx = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_grbm_idx; 1378 grbm_cntl_data = reg_access_ctrl->vfi_grbm_cntl_data; 1379 grbm_idx_data = reg_access_ctrl->vfi_grbm_idx_data; 1380 1381 if (flag == AMDGPU_RLCG_GC_WRITE) { 1382 data = v; 1383 cmd = AMDGPU_RLCG_VFI_CMD__WR; 1384 1385 // the GRBM_GFX_CNTL and GRBM_GFX_INDEX are protected by mutex outside this call 1386 if (addr == reg_access_ctrl->grbm_cntl) { 1387 reg_access_ctrl->vfi_grbm_cntl_data = data; 1388 return 0; 1389 } else if (addr == reg_access_ctrl->grbm_idx) { 1390 reg_access_ctrl->vfi_grbm_idx_data = data; 1391 return 0; 1392 } 1393 1394 } else if (flag == AMDGPU_RLCG_GC_READ) { 1395 data = 0; 1396 cmd = AMDGPU_RLCG_VFI_CMD__RD; 1397 1398 // the GRBM_GFX_CNTL and GRBM_GFX_INDEX are protected by mutex outside this call 1399 if (addr == reg_access_ctrl->grbm_cntl) 1400 return grbm_cntl_data; 1401 else if (addr == reg_access_ctrl->grbm_idx) 1402 return grbm_idx_data; 1403 1404 } else { 1405 dev_err(adev->dev, "VFi invalid access, flag=0x%x\n", flag); 1406 return 0; 1407 } 1408 1409 spin_lock_irqsave(&adev->virt.rlcg_reg_lock, flags); 1410 1411 writel(addr, vfi_addr); 1412 writel(data, vfi_data); 1413 writel(grbm_cntl_data, vfi_grbm_cntl); 1414 writel(grbm_idx_data, vfi_grbm_idx); 1415 1416 writel(AMDGPU_RLCG_VFI_STAT__BUSY, vfi_stat); 1417 writel(cmd, vfi_cmd); 1418 1419 for (i = 0; i < timeout; i++) { 1420 stat = readl(vfi_stat); 1421 if (stat != AMDGPU_RLCG_VFI_STAT__BUSY) 1422 break; 1423 udelay(10); 1424 } 1425 1426 switch (stat) { 1427 case AMDGPU_RLCG_VFI_STAT__DONE: 1428 is_err = false; 1429 if (cmd == AMDGPU_RLCG_VFI_CMD__RD) 1430 data = readl(vfi_data); 1431 break; 1432 case AMDGPU_RLCG_VFI_STAT__BUSY: 1433 dev_err(adev->dev, "VFi access timeout\n"); 1434 break; 1435 case AMDGPU_RLCG_VFI_STAT__INV_CMD: 1436 dev_err(adev->dev, "VFi invalid command\n"); 1437 break; 1438 case AMDGPU_RLCG_VFI_STAT__INV_ADDR: 1439 dev_err(adev->dev, "VFi invalid address\n"); 1440 break; 1441 case AMDGPU_RLCG_VFI_STAT__ERR: 1442 dev_err(adev->dev, "VFi unknown error\n"); 1443 break; 1444 default: 1445 dev_err(adev->dev, "VFi unknown status code\n"); 1446 break; 1447 } 1448 1449 spin_unlock_irqrestore(&adev->virt.rlcg_reg_lock, flags); 1450 1451 if (is_err) 1452 dev_err(adev->dev, "VFi: [grbm_cntl=0x%x grbm_idx=0x%x] addr=0x%x (byte addr 0x%x), data=0x%x, cmd=0x%x\n", 1453 grbm_cntl_data, grbm_idx_data, 1454 addr, addr * 4, data, cmd); 1455 else 1456 dev_dbg(adev->dev, "VFi: [grbm_cntl=0x%x grbm_idx=0x%x] addr=0x%x (byte addr 0x%x), data=0x%x, cmd=0x%x\n", 1457 grbm_cntl_data, grbm_idx_data, 1458 addr, addr * 4, data, cmd); 1459 1460 return data; 1461 } 1462 1463 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id) 1464 { 1465 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1466 uint32_t timeout = 50000; 1467 uint32_t i, tmp; 1468 uint32_t ret = 0; 1469 void *scratch_reg0; 1470 void *scratch_reg1; 1471 void *scratch_reg2; 1472 void *scratch_reg3; 1473 void *spare_int; 1474 unsigned long flags; 1475 1476 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 1, 0)) 1477 return amdgpu_virt_rlcg_vfi_reg_rw(adev, offset, v, flag, xcc_id); 1478 1479 if (!adev->gfx.rlc.rlcg_reg_access_supported) { 1480 dev_err(adev->dev, 1481 "indirect registers access through rlcg is not available\n"); 1482 return 0; 1483 } 1484 1485 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { 1486 dev_err(adev->dev, "invalid xcc\n"); 1487 return 0; 1488 } 1489 1490 if (amdgpu_device_skip_hw_access(adev)) 1491 return 0; 1492 1493 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; 1494 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0; 1495 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1; 1496 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; 1497 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3; 1498 1499 spin_lock_irqsave(&adev->virt.rlcg_reg_lock, flags); 1500 1501 if (reg_access_ctrl->spare_int) 1502 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int; 1503 1504 if (offset == reg_access_ctrl->grbm_cntl) { 1505 /* if the target reg offset is grbm_cntl, write to scratch_reg2 */ 1506 writel(v, scratch_reg2); 1507 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY) 1508 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 1509 } else if (offset == reg_access_ctrl->grbm_idx) { 1510 /* if the target reg offset is grbm_idx, write to scratch_reg3 */ 1511 writel(v, scratch_reg3); 1512 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY) 1513 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 1514 } else { 1515 /* 1516 * SCRATCH_REG0 = read/write value 1517 * SCRATCH_REG1[30:28] = command 1518 * SCRATCH_REG1[19:0] = address in dword 1519 * SCRATCH_REG1[27:24] = Error reporting 1520 */ 1521 writel(v, scratch_reg0); 1522 writel((offset | flag), scratch_reg1); 1523 if (reg_access_ctrl->spare_int) 1524 writel(1, spare_int); 1525 1526 for (i = 0; i < timeout; i++) { 1527 tmp = readl(scratch_reg1); 1528 if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK)) 1529 break; 1530 udelay(10); 1531 } 1532 1533 tmp = readl(scratch_reg1); 1534 if (i >= timeout || (tmp & AMDGPU_RLCG_SCRATCH1_ERROR_MASK) != 0) { 1535 if (amdgpu_sriov_rlcg_error_report_enabled(adev)) { 1536 if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) { 1537 dev_err(adev->dev, 1538 "vfgate is disabled, rlcg failed to program reg: 0x%05x\n", offset); 1539 } else if (tmp & AMDGPU_RLCG_WRONG_OPERATION_TYPE) { 1540 dev_err(adev->dev, 1541 "wrong operation type, rlcg failed to program reg: 0x%05x\n", offset); 1542 } else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) { 1543 dev_err(adev->dev, 1544 "register is not in range, rlcg failed to program reg: 0x%05x\n", offset); 1545 } else { 1546 dev_err(adev->dev, 1547 "unknown error type, rlcg failed to program reg: 0x%05x\n", offset); 1548 } 1549 } else { 1550 dev_err(adev->dev, 1551 "timeout: rlcg faled to program reg: 0x%05x\n", offset); 1552 } 1553 } 1554 } 1555 1556 ret = readl(scratch_reg0); 1557 1558 spin_unlock_irqrestore(&adev->virt.rlcg_reg_lock, flags); 1559 1560 return ret; 1561 } 1562 1563 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 1564 u32 offset, u32 value, 1565 u32 acc_flags, u32 hwip, u32 xcc_id) 1566 { 1567 u32 rlcg_flag; 1568 1569 if (amdgpu_device_skip_hw_access(adev)) 1570 return; 1571 1572 if (!amdgpu_sriov_runtime(adev) && 1573 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) { 1574 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag, xcc_id); 1575 return; 1576 } 1577 1578 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1579 WREG32_NO_KIQ(offset, value); 1580 else 1581 WREG32(offset, value); 1582 } 1583 1584 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 1585 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id) 1586 { 1587 u32 rlcg_flag; 1588 1589 if (amdgpu_device_skip_hw_access(adev)) 1590 return 0; 1591 1592 if (!amdgpu_sriov_runtime(adev) && 1593 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag)) 1594 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag, xcc_id); 1595 1596 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1597 return RREG32_NO_KIQ(offset); 1598 else 1599 return RREG32(offset); 1600 } 1601 1602 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev) 1603 { 1604 bool xnack_mode = true; 1605 1606 if (amdgpu_sriov_vf(adev) && 1607 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 1608 xnack_mode = false; 1609 1610 return xnack_mode; 1611 } 1612 1613 bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev) 1614 { 1615 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1616 1617 if (!amdgpu_sriov_ras_caps_en(adev)) 1618 return false; 1619 1620 if (adev->virt.ras_en_caps.bits.block_umc) 1621 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__UMC); 1622 if (adev->virt.ras_en_caps.bits.block_sdma) 1623 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SDMA); 1624 if (adev->virt.ras_en_caps.bits.block_gfx) 1625 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__GFX); 1626 if (adev->virt.ras_en_caps.bits.block_mmhub) 1627 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MMHUB); 1628 if (adev->virt.ras_en_caps.bits.block_athub) 1629 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__ATHUB); 1630 if (adev->virt.ras_en_caps.bits.block_pcie_bif) 1631 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__PCIE_BIF); 1632 if (adev->virt.ras_en_caps.bits.block_hdp) 1633 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__HDP); 1634 if (adev->virt.ras_en_caps.bits.block_xgmi_wafl) 1635 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__XGMI_WAFL); 1636 if (adev->virt.ras_en_caps.bits.block_df) 1637 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__DF); 1638 if (adev->virt.ras_en_caps.bits.block_smn) 1639 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SMN); 1640 if (adev->virt.ras_en_caps.bits.block_sem) 1641 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SEM); 1642 if (adev->virt.ras_en_caps.bits.block_mp0) 1643 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MP0); 1644 if (adev->virt.ras_en_caps.bits.block_mp1) 1645 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MP1); 1646 if (adev->virt.ras_en_caps.bits.block_fuse) 1647 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__FUSE); 1648 if (adev->virt.ras_en_caps.bits.block_mca) 1649 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MCA); 1650 if (adev->virt.ras_en_caps.bits.block_vcn) 1651 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__VCN); 1652 if (adev->virt.ras_en_caps.bits.block_jpeg) 1653 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__JPEG); 1654 if (adev->virt.ras_en_caps.bits.block_ih) 1655 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__IH); 1656 if (adev->virt.ras_en_caps.bits.block_mpio) 1657 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MPIO); 1658 1659 if (adev->virt.ras_en_caps.bits.poison_propogation_mode) 1660 con->poison_supported = true; /* Poison is handled by host */ 1661 1662 if (adev->virt.ras_en_caps.bits.uniras_supported) 1663 amdgpu_virt_ras_set_remote_uniras(adev, true); 1664 1665 return true; 1666 } 1667 1668 static inline enum amd_sriov_ras_telemetry_gpu_block 1669 amdgpu_ras_block_to_sriov(struct amdgpu_device *adev, enum amdgpu_ras_block block) { 1670 switch (block) { 1671 case AMDGPU_RAS_BLOCK__UMC: 1672 return RAS_TELEMETRY_GPU_BLOCK_UMC; 1673 case AMDGPU_RAS_BLOCK__SDMA: 1674 return RAS_TELEMETRY_GPU_BLOCK_SDMA; 1675 case AMDGPU_RAS_BLOCK__GFX: 1676 return RAS_TELEMETRY_GPU_BLOCK_GFX; 1677 case AMDGPU_RAS_BLOCK__MMHUB: 1678 return RAS_TELEMETRY_GPU_BLOCK_MMHUB; 1679 case AMDGPU_RAS_BLOCK__ATHUB: 1680 return RAS_TELEMETRY_GPU_BLOCK_ATHUB; 1681 case AMDGPU_RAS_BLOCK__PCIE_BIF: 1682 return RAS_TELEMETRY_GPU_BLOCK_PCIE_BIF; 1683 case AMDGPU_RAS_BLOCK__HDP: 1684 return RAS_TELEMETRY_GPU_BLOCK_HDP; 1685 case AMDGPU_RAS_BLOCK__XGMI_WAFL: 1686 return RAS_TELEMETRY_GPU_BLOCK_XGMI_WAFL; 1687 case AMDGPU_RAS_BLOCK__DF: 1688 return RAS_TELEMETRY_GPU_BLOCK_DF; 1689 case AMDGPU_RAS_BLOCK__SMN: 1690 return RAS_TELEMETRY_GPU_BLOCK_SMN; 1691 case AMDGPU_RAS_BLOCK__SEM: 1692 return RAS_TELEMETRY_GPU_BLOCK_SEM; 1693 case AMDGPU_RAS_BLOCK__MP0: 1694 return RAS_TELEMETRY_GPU_BLOCK_MP0; 1695 case AMDGPU_RAS_BLOCK__MP1: 1696 return RAS_TELEMETRY_GPU_BLOCK_MP1; 1697 case AMDGPU_RAS_BLOCK__FUSE: 1698 return RAS_TELEMETRY_GPU_BLOCK_FUSE; 1699 case AMDGPU_RAS_BLOCK__MCA: 1700 return RAS_TELEMETRY_GPU_BLOCK_MCA; 1701 case AMDGPU_RAS_BLOCK__VCN: 1702 return RAS_TELEMETRY_GPU_BLOCK_VCN; 1703 case AMDGPU_RAS_BLOCK__JPEG: 1704 return RAS_TELEMETRY_GPU_BLOCK_JPEG; 1705 case AMDGPU_RAS_BLOCK__IH: 1706 return RAS_TELEMETRY_GPU_BLOCK_IH; 1707 case AMDGPU_RAS_BLOCK__MPIO: 1708 return RAS_TELEMETRY_GPU_BLOCK_MPIO; 1709 default: 1710 dev_warn(adev->dev, "Unsupported SRIOV RAS telemetry block 0x%x\n", 1711 block); 1712 return RAS_TELEMETRY_GPU_BLOCK_COUNT; 1713 } 1714 } 1715 1716 static int amdgpu_virt_cache_host_error_counts(struct amdgpu_device *adev, 1717 struct amdsriov_ras_telemetry *host_telemetry) 1718 { 1719 struct amd_sriov_ras_telemetry_error_count *tmp = NULL; 1720 uint32_t checksum, used_size; 1721 1722 checksum = host_telemetry->header.checksum; 1723 used_size = host_telemetry->header.used_size; 1724 1725 if (used_size > (AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1 << 10)) 1726 return 0; 1727 1728 tmp = kmemdup(&host_telemetry->body.error_count, used_size, GFP_KERNEL); 1729 if (!tmp) 1730 return -ENOMEM; 1731 1732 if (checksum != amd_sriov_msg_checksum(tmp, used_size, 0, 0)) 1733 goto out; 1734 1735 memcpy(&adev->virt.count_cache, tmp, 1736 min(used_size, sizeof(adev->virt.count_cache))); 1737 out: 1738 kfree(tmp); 1739 1740 return 0; 1741 } 1742 1743 static int amdgpu_virt_req_ras_err_count_internal(struct amdgpu_device *adev, bool force_update) 1744 { 1745 struct amdgpu_virt *virt = &adev->virt; 1746 1747 if (!virt->ops || !virt->ops->req_ras_err_count) 1748 return -EOPNOTSUPP; 1749 1750 /* Host allows 15 ras telemetry requests per 60 seconds. Afterwhich, the Host 1751 * will ignore incoming guest messages. Ratelimit the guest messages to 1752 * prevent guest self DOS. 1753 */ 1754 if (__ratelimit(&virt->ras.ras_error_cnt_rs) || force_update) { 1755 mutex_lock(&virt->ras.ras_telemetry_mutex); 1756 if (!virt->ops->req_ras_err_count(adev)) 1757 amdgpu_virt_cache_host_error_counts(adev, 1758 virt->fw_reserve.ras_telemetry); 1759 mutex_unlock(&virt->ras.ras_telemetry_mutex); 1760 } 1761 1762 return 0; 1763 } 1764 1765 /* Bypass ACA interface and query ECC counts directly from host */ 1766 int amdgpu_virt_req_ras_err_count(struct amdgpu_device *adev, enum amdgpu_ras_block block, 1767 struct ras_err_data *err_data) 1768 { 1769 enum amd_sriov_ras_telemetry_gpu_block sriov_block; 1770 1771 sriov_block = amdgpu_ras_block_to_sriov(adev, block); 1772 1773 if (sriov_block >= RAS_TELEMETRY_GPU_BLOCK_COUNT || 1774 !amdgpu_sriov_ras_telemetry_block_en(adev, sriov_block)) 1775 return -EOPNOTSUPP; 1776 1777 /* Host Access may be lost during reset, just return last cached data. */ 1778 if (down_read_trylock(&adev->reset_domain->sem)) { 1779 amdgpu_virt_req_ras_err_count_internal(adev, false); 1780 up_read(&adev->reset_domain->sem); 1781 } 1782 1783 err_data->ue_count = adev->virt.count_cache.block[sriov_block].ue_count; 1784 err_data->ce_count = adev->virt.count_cache.block[sriov_block].ce_count; 1785 err_data->de_count = adev->virt.count_cache.block[sriov_block].de_count; 1786 1787 return 0; 1788 } 1789 1790 static int 1791 amdgpu_virt_write_cpers_to_ring(struct amdgpu_device *adev, 1792 struct amdsriov_ras_telemetry *host_telemetry, 1793 u32 *more) 1794 { 1795 struct amd_sriov_ras_cper_dump *cper_dump = NULL; 1796 struct cper_hdr *entry = NULL; 1797 struct amdgpu_ring *ring = &adev->cper.ring_buf; 1798 uint32_t checksum, used_size, i; 1799 int ret = 0; 1800 1801 checksum = host_telemetry->header.checksum; 1802 used_size = host_telemetry->header.used_size; 1803 1804 if (used_size > (AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1 << 10)) 1805 return -EINVAL; 1806 1807 cper_dump = kmemdup(&host_telemetry->body.cper_dump, used_size, GFP_KERNEL); 1808 if (!cper_dump) 1809 return -ENOMEM; 1810 1811 if (checksum != amd_sriov_msg_checksum(cper_dump, used_size, 0, 0)) { 1812 ret = -EINVAL; 1813 goto out; 1814 } 1815 1816 *more = cper_dump->more; 1817 1818 if (cper_dump->wptr < adev->virt.ras.cper_rptr) { 1819 dev_warn( 1820 adev->dev, 1821 "guest specified rptr that was too high! guest rptr: 0x%llx, host rptr: 0x%llx\n", 1822 adev->virt.ras.cper_rptr, cper_dump->wptr); 1823 1824 adev->virt.ras.cper_rptr = cper_dump->wptr; 1825 goto out; 1826 } 1827 1828 entry = (struct cper_hdr *)&cper_dump->buf[0]; 1829 1830 for (i = 0; i < cper_dump->count; i++) { 1831 amdgpu_cper_ring_write(ring, entry, entry->record_length); 1832 entry = (struct cper_hdr *)((char *)entry + 1833 entry->record_length); 1834 } 1835 1836 if (cper_dump->overflow_count) 1837 dev_warn(adev->dev, 1838 "host reported CPER overflow of 0x%llx entries!\n", 1839 cper_dump->overflow_count); 1840 1841 adev->virt.ras.cper_rptr = cper_dump->wptr; 1842 out: 1843 kfree(cper_dump); 1844 1845 return ret; 1846 } 1847 1848 static int amdgpu_virt_req_ras_cper_dump_internal(struct amdgpu_device *adev) 1849 { 1850 struct amdgpu_virt *virt = &adev->virt; 1851 int ret = 0; 1852 uint32_t more = 0; 1853 1854 if (!virt->ops || !virt->ops->req_ras_cper_dump) 1855 return -EOPNOTSUPP; 1856 1857 do { 1858 if (!virt->ops->req_ras_cper_dump(adev, virt->ras.cper_rptr)) 1859 ret = amdgpu_virt_write_cpers_to_ring( 1860 adev, virt->fw_reserve.ras_telemetry, &more); 1861 else 1862 ret = 0; 1863 } while (more && !ret); 1864 1865 return ret; 1866 } 1867 1868 int amdgpu_virt_req_ras_cper_dump(struct amdgpu_device *adev, bool force_update) 1869 { 1870 struct amdgpu_virt *virt = &adev->virt; 1871 int ret = 0; 1872 1873 if (!amdgpu_sriov_ras_cper_en(adev)) 1874 return -EOPNOTSUPP; 1875 1876 if ((__ratelimit(&virt->ras.ras_cper_dump_rs) || force_update) && 1877 down_read_trylock(&adev->reset_domain->sem)) { 1878 mutex_lock(&virt->ras.ras_telemetry_mutex); 1879 ret = amdgpu_virt_req_ras_cper_dump_internal(adev); 1880 mutex_unlock(&virt->ras.ras_telemetry_mutex); 1881 up_read(&adev->reset_domain->sem); 1882 } 1883 1884 return ret; 1885 } 1886 1887 int amdgpu_virt_ras_telemetry_post_reset(struct amdgpu_device *adev) 1888 { 1889 unsigned long ue_count, ce_count; 1890 1891 if (amdgpu_sriov_ras_telemetry_en(adev)) { 1892 amdgpu_virt_req_ras_err_count_internal(adev, true); 1893 amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL); 1894 } 1895 1896 return 0; 1897 } 1898 1899 bool amdgpu_virt_ras_telemetry_block_en(struct amdgpu_device *adev, 1900 enum amdgpu_ras_block block) 1901 { 1902 enum amd_sriov_ras_telemetry_gpu_block sriov_block; 1903 1904 sriov_block = amdgpu_ras_block_to_sriov(adev, block); 1905 1906 if (sriov_block >= RAS_TELEMETRY_GPU_BLOCK_COUNT || 1907 !amdgpu_sriov_ras_telemetry_block_en(adev, sriov_block)) 1908 return false; 1909 1910 return true; 1911 } 1912 1913 /* 1914 * amdgpu_virt_request_bad_pages() - request bad pages 1915 * @adev: amdgpu device. 1916 * Send command to GPU hypervisor to write new bad pages into the shared PF2VF region 1917 */ 1918 void amdgpu_virt_request_bad_pages(struct amdgpu_device *adev) 1919 { 1920 struct amdgpu_virt *virt = &adev->virt; 1921 1922 if (virt->ops && virt->ops->req_bad_pages) 1923 virt->ops->req_bad_pages(adev); 1924 } 1925 1926 static int amdgpu_virt_cache_chk_criti_hit(struct amdgpu_device *adev, 1927 struct amdsriov_ras_telemetry *host_telemetry, 1928 bool *hit) 1929 { 1930 struct amd_sriov_ras_chk_criti *tmp = NULL; 1931 uint32_t checksum, used_size; 1932 1933 checksum = host_telemetry->header.checksum; 1934 used_size = host_telemetry->header.used_size; 1935 1936 if (used_size > (AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1 << 10)) 1937 return 0; 1938 1939 tmp = kmemdup(&host_telemetry->body.chk_criti, used_size, GFP_KERNEL); 1940 if (!tmp) 1941 return -ENOMEM; 1942 1943 if (checksum != amd_sriov_msg_checksum(tmp, used_size, 0, 0)) 1944 goto out; 1945 1946 if (hit) 1947 *hit = tmp->hit ? true : false; 1948 1949 out: 1950 kfree(tmp); 1951 1952 return 0; 1953 } 1954 1955 int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, bool *hit) 1956 { 1957 struct amdgpu_virt *virt = &adev->virt; 1958 int r = -EPERM; 1959 1960 if (!virt->ops || !virt->ops->req_ras_chk_criti) 1961 return -EOPNOTSUPP; 1962 1963 /* Host allows 15 ras telemetry requests per 60 seconds. Afterwhich, the Host 1964 * will ignore incoming guest messages. Ratelimit the guest messages to 1965 * prevent guest self DOS. 1966 */ 1967 if (__ratelimit(&virt->ras.ras_chk_criti_rs)) { 1968 mutex_lock(&virt->ras.ras_telemetry_mutex); 1969 if (!virt->ops->req_ras_chk_criti(adev, addr)) 1970 r = amdgpu_virt_cache_chk_criti_hit( 1971 adev, virt->fw_reserve.ras_telemetry, hit); 1972 mutex_unlock(&virt->ras.ras_telemetry_mutex); 1973 } 1974 1975 return r; 1976 } 1977 1978 static int req_remote_ras_cmd(struct amdgpu_device *adev, 1979 u32 param1, u32 param2, u32 param3) 1980 { 1981 struct amdgpu_virt *virt = &adev->virt; 1982 1983 if (virt->ops && virt->ops->req_remote_ras_cmd) 1984 return virt->ops->req_remote_ras_cmd(adev, param1, param2, param3); 1985 return -ENOENT; 1986 } 1987 1988 int amdgpu_virt_send_remote_ras_cmd(struct amdgpu_device *adev, 1989 uint64_t buf, uint32_t buf_len) 1990 { 1991 uint64_t gpa = buf; 1992 int ret = -EIO; 1993 1994 if (down_read_trylock(&adev->reset_domain->sem)) { 1995 ret = req_remote_ras_cmd(adev, 1996 lower_32_bits(gpa), upper_32_bits(gpa), buf_len); 1997 up_read(&adev->reset_domain->sem); 1998 } 1999 2000 return ret; 2001 } 2002