1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/module.h> 25 26 #ifdef CONFIG_X86 27 #include <asm/hypervisor.h> 28 #endif 29 30 #include <drm/drm_drv.h> 31 #include <xen/xen.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_ras.h" 35 #include "amdgpu_reset.h" 36 #include "vi.h" 37 #include "soc15.h" 38 #include "nv.h" 39 40 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \ 41 do { \ 42 vf2pf_info->ucode_info[ucode].id = ucode; \ 43 vf2pf_info->ucode_info[ucode].version = ver; \ 44 } while (0) 45 46 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) 47 { 48 /* By now all MMIO pages except mailbox are blocked */ 49 /* if blocking is enabled in hypervisor. Choose the */ 50 /* SCRATCH_REG0 to test. */ 51 return RREG32_NO_KIQ(0xc040) == 0xffffffff; 52 } 53 54 void amdgpu_virt_init_setting(struct amdgpu_device *adev) 55 { 56 struct drm_device *ddev = adev_to_drm(adev); 57 58 /* enable virtual display */ 59 if (adev->asic_type != CHIP_ALDEBARAN && 60 adev->asic_type != CHIP_ARCTURUS && 61 ((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) { 62 if (adev->mode_info.num_crtc == 0) 63 adev->mode_info.num_crtc = 1; 64 adev->enable_virtual_display = true; 65 } 66 ddev->driver_features &= ~DRIVER_ATOMIC; 67 adev->cg_flags = 0; 68 adev->pg_flags = 0; 69 70 /* Reduce kcq number to 2 to reduce latency */ 71 if (amdgpu_num_kcq == -1) 72 amdgpu_num_kcq = 2; 73 } 74 75 /** 76 * amdgpu_virt_request_full_gpu() - request full gpu access 77 * @adev: amdgpu device. 78 * @init: is driver init time. 79 * When start to init/fini driver, first need to request full gpu access. 80 * Return: Zero if request success, otherwise will return error. 81 */ 82 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init) 83 { 84 struct amdgpu_virt *virt = &adev->virt; 85 int r; 86 87 if (virt->ops && virt->ops->req_full_gpu) { 88 r = virt->ops->req_full_gpu(adev, init); 89 if (r) { 90 adev->no_hw_access = true; 91 return r; 92 } 93 94 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 95 } 96 97 return 0; 98 } 99 100 /** 101 * amdgpu_virt_release_full_gpu() - release full gpu access 102 * @adev: amdgpu device. 103 * @init: is driver init time. 104 * When finishing driver init/fini, need to release full gpu access. 105 * Return: Zero if release success, otherwise will returen error. 106 */ 107 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init) 108 { 109 struct amdgpu_virt *virt = &adev->virt; 110 int r; 111 112 if (virt->ops && virt->ops->rel_full_gpu) { 113 r = virt->ops->rel_full_gpu(adev, init); 114 if (r) 115 return r; 116 117 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 118 } 119 return 0; 120 } 121 122 /** 123 * amdgpu_virt_reset_gpu() - reset gpu 124 * @adev: amdgpu device. 125 * Send reset command to GPU hypervisor to reset GPU that VM is using 126 * Return: Zero if reset success, otherwise will return error. 127 */ 128 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev) 129 { 130 struct amdgpu_virt *virt = &adev->virt; 131 int r; 132 133 if (virt->ops && virt->ops->reset_gpu) { 134 r = virt->ops->reset_gpu(adev); 135 if (r) 136 return r; 137 138 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 139 } 140 141 return 0; 142 } 143 144 void amdgpu_virt_request_init_data(struct amdgpu_device *adev) 145 { 146 struct amdgpu_virt *virt = &adev->virt; 147 148 if (virt->ops && virt->ops->req_init_data) 149 virt->ops->req_init_data(adev); 150 151 if (adev->virt.req_init_data_ver > 0) 152 DRM_INFO("host supports REQ_INIT_DATA handshake\n"); 153 else 154 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n"); 155 } 156 157 /** 158 * amdgpu_virt_ready_to_reset() - send ready to reset to host 159 * @adev: amdgpu device. 160 * Send ready to reset message to GPU hypervisor to signal we have stopped GPU 161 * activity and is ready for host FLR 162 */ 163 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev) 164 { 165 struct amdgpu_virt *virt = &adev->virt; 166 167 if (virt->ops && virt->ops->reset_gpu) 168 virt->ops->ready_to_reset(adev); 169 } 170 171 /** 172 * amdgpu_virt_wait_reset() - wait for reset gpu completed 173 * @adev: amdgpu device. 174 * Wait for GPU reset completed. 175 * Return: Zero if reset success, otherwise will return error. 176 */ 177 int amdgpu_virt_wait_reset(struct amdgpu_device *adev) 178 { 179 struct amdgpu_virt *virt = &adev->virt; 180 181 if (!virt->ops || !virt->ops->wait_reset) 182 return -EINVAL; 183 184 return virt->ops->wait_reset(adev); 185 } 186 187 /** 188 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table 189 * @adev: amdgpu device. 190 * MM table is used by UVD and VCE for its initialization 191 * Return: Zero if allocate success. 192 */ 193 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev) 194 { 195 int r; 196 197 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) 198 return 0; 199 200 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 201 AMDGPU_GEM_DOMAIN_VRAM | 202 AMDGPU_GEM_DOMAIN_GTT, 203 &adev->virt.mm_table.bo, 204 &adev->virt.mm_table.gpu_addr, 205 (void *)&adev->virt.mm_table.cpu_addr); 206 if (r) { 207 DRM_ERROR("failed to alloc mm table and error = %d.\n", r); 208 return r; 209 } 210 211 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); 212 DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n", 213 adev->virt.mm_table.gpu_addr, 214 adev->virt.mm_table.cpu_addr); 215 return 0; 216 } 217 218 /** 219 * amdgpu_virt_free_mm_table() - free mm table memory 220 * @adev: amdgpu device. 221 * Free MM table memory 222 */ 223 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev) 224 { 225 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) 226 return; 227 228 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo, 229 &adev->virt.mm_table.gpu_addr, 230 (void *)&adev->virt.mm_table.cpu_addr); 231 adev->virt.mm_table.gpu_addr = 0; 232 } 233 234 /** 235 * amdgpu_virt_rcvd_ras_interrupt() - receive ras interrupt 236 * @adev: amdgpu device. 237 * Check whether host sent RAS error message 238 * Return: true if found, otherwise false 239 */ 240 bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev) 241 { 242 struct amdgpu_virt *virt = &adev->virt; 243 244 if (!virt->ops || !virt->ops->rcvd_ras_intr) 245 return false; 246 247 return virt->ops->rcvd_ras_intr(adev); 248 } 249 250 251 unsigned int amd_sriov_msg_checksum(void *obj, 252 unsigned long obj_size, 253 unsigned int key, 254 unsigned int checksum) 255 { 256 unsigned int ret = key; 257 unsigned long i = 0; 258 unsigned char *pos; 259 260 pos = (char *)obj; 261 /* calculate checksum */ 262 for (i = 0; i < obj_size; ++i) 263 ret += *(pos + i); 264 /* minus the checksum itself */ 265 pos = (char *)&checksum; 266 for (i = 0; i < sizeof(checksum); ++i) 267 ret -= *(pos + i); 268 return ret; 269 } 270 271 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev) 272 { 273 struct amdgpu_virt *virt = &adev->virt; 274 struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data; 275 /* GPU will be marked bad on host if bp count more then 10, 276 * so alloc 512 is enough. 277 */ 278 unsigned int align_space = 512; 279 void *bps = NULL; 280 struct amdgpu_bo **bps_bo = NULL; 281 282 *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL); 283 if (!*data) 284 goto data_failure; 285 286 bps = kmalloc_array(align_space, sizeof(*(*data)->bps), GFP_KERNEL); 287 if (!bps) 288 goto bps_failure; 289 290 bps_bo = kmalloc_array(align_space, sizeof(*(*data)->bps_bo), GFP_KERNEL); 291 if (!bps_bo) 292 goto bps_bo_failure; 293 294 (*data)->bps = bps; 295 (*data)->bps_bo = bps_bo; 296 (*data)->count = 0; 297 (*data)->last_reserved = 0; 298 299 virt->ras_init_done = true; 300 301 return 0; 302 303 bps_bo_failure: 304 kfree(bps); 305 bps_failure: 306 kfree(*data); 307 data_failure: 308 return -ENOMEM; 309 } 310 311 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev) 312 { 313 struct amdgpu_virt *virt = &adev->virt; 314 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 315 struct amdgpu_bo *bo; 316 int i; 317 318 if (!data) 319 return; 320 321 for (i = data->last_reserved - 1; i >= 0; i--) { 322 bo = data->bps_bo[i]; 323 if (bo) { 324 amdgpu_bo_free_kernel(&bo, NULL, NULL); 325 data->bps_bo[i] = bo; 326 } 327 data->last_reserved = i; 328 } 329 } 330 331 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev) 332 { 333 struct amdgpu_virt *virt = &adev->virt; 334 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 335 336 virt->ras_init_done = false; 337 338 if (!data) 339 return; 340 341 amdgpu_virt_ras_release_bp(adev); 342 343 kfree(data->bps); 344 kfree(data->bps_bo); 345 kfree(data); 346 virt->virt_eh_data = NULL; 347 } 348 349 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev, 350 struct eeprom_table_record *bps, int pages) 351 { 352 struct amdgpu_virt *virt = &adev->virt; 353 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 354 355 if (!data) 356 return; 357 358 memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); 359 data->count += pages; 360 } 361 362 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev) 363 { 364 struct amdgpu_virt *virt = &adev->virt; 365 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 366 struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; 367 struct ttm_resource_manager *man = &mgr->manager; 368 struct amdgpu_bo *bo = NULL; 369 uint64_t bp; 370 int i; 371 372 if (!data) 373 return; 374 375 for (i = data->last_reserved; i < data->count; i++) { 376 bp = data->bps[i].retired_page; 377 378 /* There are two cases of reserve error should be ignored: 379 * 1) a ras bad page has been allocated (used by someone); 380 * 2) a ras bad page has been reserved (duplicate error injection 381 * for one page); 382 */ 383 if (ttm_resource_manager_used(man)) { 384 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr, 385 bp << AMDGPU_GPU_PAGE_SHIFT, 386 AMDGPU_GPU_PAGE_SIZE); 387 data->bps_bo[i] = NULL; 388 } else { 389 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, 390 AMDGPU_GPU_PAGE_SIZE, 391 &bo, NULL)) 392 DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp); 393 data->bps_bo[i] = bo; 394 } 395 data->last_reserved = i + 1; 396 bo = NULL; 397 } 398 } 399 400 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev, 401 uint64_t retired_page) 402 { 403 struct amdgpu_virt *virt = &adev->virt; 404 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 405 int i; 406 407 if (!data) 408 return true; 409 410 for (i = 0; i < data->count; i++) 411 if (retired_page == data->bps[i].retired_page) 412 return true; 413 414 return false; 415 } 416 417 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev, 418 uint64_t bp_block_offset, uint32_t bp_block_size) 419 { 420 struct eeprom_table_record bp; 421 uint64_t retired_page; 422 uint32_t bp_idx, bp_cnt; 423 void *vram_usage_va = NULL; 424 425 if (adev->mman.fw_vram_usage_va) 426 vram_usage_va = adev->mman.fw_vram_usage_va; 427 else 428 vram_usage_va = adev->mman.drv_vram_usage_va; 429 430 memset(&bp, 0, sizeof(bp)); 431 432 if (bp_block_size) { 433 bp_cnt = bp_block_size / sizeof(uint64_t); 434 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) { 435 retired_page = *(uint64_t *)(vram_usage_va + 436 bp_block_offset + bp_idx * sizeof(uint64_t)); 437 bp.retired_page = retired_page; 438 439 if (amdgpu_virt_ras_check_bad_page(adev, retired_page)) 440 continue; 441 442 amdgpu_virt_ras_add_bps(adev, &bp, 1); 443 444 amdgpu_virt_ras_reserve_bps(adev); 445 } 446 } 447 } 448 449 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) 450 { 451 struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf; 452 uint32_t checksum; 453 uint32_t checkval; 454 455 uint32_t i; 456 uint32_t tmp; 457 458 if (adev->virt.fw_reserve.p_pf2vf == NULL) 459 return -EINVAL; 460 461 if (pf2vf_info->size > 1024) { 462 dev_err(adev->dev, "invalid pf2vf message size: 0x%x\n", pf2vf_info->size); 463 return -EINVAL; 464 } 465 466 switch (pf2vf_info->version) { 467 case 1: 468 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum; 469 checkval = amd_sriov_msg_checksum( 470 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 471 adev->virt.fw_reserve.checksum_key, checksum); 472 if (checksum != checkval) { 473 dev_err(adev->dev, 474 "invalid pf2vf message: header checksum=0x%x calculated checksum=0x%x\n", 475 checksum, checkval); 476 return -EINVAL; 477 } 478 479 adev->virt.gim_feature = 480 ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags; 481 break; 482 case 2: 483 /* TODO: missing key, need to add it later */ 484 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum; 485 checkval = amd_sriov_msg_checksum( 486 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 487 0, checksum); 488 if (checksum != checkval) { 489 dev_err(adev->dev, 490 "invalid pf2vf message: header checksum=0x%x calculated checksum=0x%x\n", 491 checksum, checkval); 492 return -EINVAL; 493 } 494 495 adev->virt.vf2pf_update_interval_ms = 496 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms; 497 adev->virt.gim_feature = 498 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all; 499 adev->virt.reg_access = 500 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all; 501 502 adev->virt.decode_max_dimension_pixels = 0; 503 adev->virt.decode_max_frame_pixels = 0; 504 adev->virt.encode_max_dimension_pixels = 0; 505 adev->virt.encode_max_frame_pixels = 0; 506 adev->virt.is_mm_bw_enabled = false; 507 for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) { 508 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels; 509 adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels); 510 511 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels; 512 adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels); 513 514 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels; 515 adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels); 516 517 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels; 518 adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels); 519 } 520 if ((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0)) 521 adev->virt.is_mm_bw_enabled = true; 522 523 adev->unique_id = 524 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid; 525 break; 526 default: 527 dev_err(adev->dev, "invalid pf2vf version: 0x%x\n", pf2vf_info->version); 528 return -EINVAL; 529 } 530 531 /* correct too large or too little interval value */ 532 if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000) 533 adev->virt.vf2pf_update_interval_ms = 2000; 534 535 return 0; 536 } 537 538 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev) 539 { 540 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 541 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 542 543 if (adev->virt.fw_reserve.p_vf2pf == NULL) 544 return; 545 546 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version); 547 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version); 548 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version); 549 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); 550 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); 551 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); 552 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); 553 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); 554 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); 555 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); 556 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); 557 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); 558 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version); 559 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD, 560 adev->psp.asd_context.bin_desc.fw_version); 561 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS, 562 adev->psp.ras_context.context.bin_desc.fw_version); 563 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI, 564 adev->psp.xgmi_context.context.bin_desc.fw_version); 565 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version); 566 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version); 567 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version); 568 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version); 569 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version); 570 } 571 572 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) 573 { 574 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 575 576 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 577 578 if (adev->virt.fw_reserve.p_vf2pf == NULL) 579 return -EINVAL; 580 581 memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info)); 582 583 vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info); 584 vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER; 585 586 #ifdef MODULE 587 if (THIS_MODULE->version != NULL) 588 strcpy(vf2pf_info->driver_version, THIS_MODULE->version); 589 else 590 #endif 591 strcpy(vf2pf_info->driver_version, "N/A"); 592 593 vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all 594 vf2pf_info->driver_cert = 0; 595 vf2pf_info->os_info.all = 0; 596 597 vf2pf_info->fb_usage = 598 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20; 599 vf2pf_info->fb_vis_usage = 600 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20; 601 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20; 602 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20; 603 604 amdgpu_virt_populate_vf2pf_ucode_info(adev); 605 606 /* TODO: read dynamic info */ 607 vf2pf_info->gfx_usage = 0; 608 vf2pf_info->compute_usage = 0; 609 vf2pf_info->encode_usage = 0; 610 vf2pf_info->decode_usage = 0; 611 612 vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr; 613 vf2pf_info->mes_info_addr = (uint64_t)adev->mes.resource_1_gpu_addr; 614 615 if (adev->mes.resource_1) { 616 vf2pf_info->mes_info_size = adev->mes.resource_1->tbo.base.size; 617 } 618 vf2pf_info->checksum = 619 amd_sriov_msg_checksum( 620 vf2pf_info, sizeof(*vf2pf_info), 0, 0); 621 622 return 0; 623 } 624 625 static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work) 626 { 627 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work); 628 int ret; 629 630 ret = amdgpu_virt_read_pf2vf_data(adev); 631 if (ret) { 632 adev->virt.vf2pf_update_retry_cnt++; 633 634 if ((amdgpu_virt_rcvd_ras_interrupt(adev) || 635 adev->virt.vf2pf_update_retry_cnt >= AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT) && 636 amdgpu_sriov_runtime(adev)) { 637 638 amdgpu_ras_set_fed(adev, true); 639 if (amdgpu_reset_domain_schedule(adev->reset_domain, 640 &adev->kfd.reset_work)) 641 return; 642 else 643 dev_err(adev->dev, "Failed to queue work! at %s", __func__); 644 } 645 646 goto out; 647 } 648 649 adev->virt.vf2pf_update_retry_cnt = 0; 650 amdgpu_virt_write_vf2pf_data(adev); 651 652 out: 653 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); 654 } 655 656 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev) 657 { 658 if (adev->virt.vf2pf_update_interval_ms != 0) { 659 DRM_INFO("clean up the vf2pf work item\n"); 660 cancel_delayed_work_sync(&adev->virt.vf2pf_work); 661 adev->virt.vf2pf_update_interval_ms = 0; 662 } 663 } 664 665 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) 666 { 667 adev->virt.fw_reserve.p_pf2vf = NULL; 668 adev->virt.fw_reserve.p_vf2pf = NULL; 669 adev->virt.vf2pf_update_interval_ms = 0; 670 adev->virt.vf2pf_update_retry_cnt = 0; 671 672 if (adev->mman.fw_vram_usage_va && adev->mman.drv_vram_usage_va) { 673 DRM_WARN("Currently fw_vram and drv_vram should not have values at the same time!"); 674 } else if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { 675 /* go through this logic in ip_init and reset to init workqueue*/ 676 amdgpu_virt_exchange_data(adev); 677 678 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item); 679 schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms)); 680 } else if (adev->bios != NULL) { 681 /* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/ 682 adev->virt.fw_reserve.p_pf2vf = 683 (struct amd_sriov_msg_pf2vf_info_header *) 684 (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 685 686 amdgpu_virt_read_pf2vf_data(adev); 687 } 688 } 689 690 691 void amdgpu_virt_exchange_data(struct amdgpu_device *adev) 692 { 693 uint64_t bp_block_offset = 0; 694 uint32_t bp_block_size = 0; 695 struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL; 696 697 if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { 698 if (adev->mman.fw_vram_usage_va) { 699 adev->virt.fw_reserve.p_pf2vf = 700 (struct amd_sriov_msg_pf2vf_info_header *) 701 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 702 adev->virt.fw_reserve.p_vf2pf = 703 (struct amd_sriov_msg_vf2pf_info_header *) 704 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 705 } else if (adev->mman.drv_vram_usage_va) { 706 adev->virt.fw_reserve.p_pf2vf = 707 (struct amd_sriov_msg_pf2vf_info_header *) 708 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 709 adev->virt.fw_reserve.p_vf2pf = 710 (struct amd_sriov_msg_vf2pf_info_header *) 711 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 712 } 713 714 amdgpu_virt_read_pf2vf_data(adev); 715 amdgpu_virt_write_vf2pf_data(adev); 716 717 /* bad page handling for version 2 */ 718 if (adev->virt.fw_reserve.p_pf2vf->version == 2) { 719 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf; 720 721 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) | 722 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000); 723 bp_block_size = pf2vf_v2->bp_block_size; 724 725 if (bp_block_size && !adev->virt.ras_init_done) 726 amdgpu_virt_init_ras_err_handler_data(adev); 727 728 if (adev->virt.ras_init_done) 729 amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size); 730 } 731 } 732 } 733 734 void amdgpu_detect_virtualization(struct amdgpu_device *adev) 735 { 736 uint32_t reg; 737 738 switch (adev->asic_type) { 739 case CHIP_TONGA: 740 case CHIP_FIJI: 741 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); 742 break; 743 case CHIP_VEGA10: 744 case CHIP_VEGA20: 745 case CHIP_NAVI10: 746 case CHIP_NAVI12: 747 case CHIP_SIENNA_CICHLID: 748 case CHIP_ARCTURUS: 749 case CHIP_ALDEBARAN: 750 case CHIP_IP_DISCOVERY: 751 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER); 752 break; 753 default: /* other chip doesn't support SRIOV */ 754 reg = 0; 755 break; 756 } 757 758 if (reg & 1) 759 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 760 761 if (reg & 0x80000000) 762 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 763 764 if (!reg) { 765 /* passthrough mode exclus sriov mod */ 766 if (is_virtual_machine() && !xen_initial_domain()) 767 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 768 } 769 770 /* we have the ability to check now */ 771 if (amdgpu_sriov_vf(adev)) { 772 switch (adev->asic_type) { 773 case CHIP_TONGA: 774 case CHIP_FIJI: 775 vi_set_virt_ops(adev); 776 break; 777 case CHIP_VEGA10: 778 soc15_set_virt_ops(adev); 779 #ifdef CONFIG_X86 780 /* not send GPU_INIT_DATA with MS_HYPERV*/ 781 if (!hypervisor_is_type(X86_HYPER_MS_HYPERV)) 782 #endif 783 /* send a dummy GPU_INIT_DATA request to host on vega10 */ 784 amdgpu_virt_request_init_data(adev); 785 break; 786 case CHIP_VEGA20: 787 case CHIP_ARCTURUS: 788 case CHIP_ALDEBARAN: 789 soc15_set_virt_ops(adev); 790 break; 791 case CHIP_NAVI10: 792 case CHIP_NAVI12: 793 case CHIP_SIENNA_CICHLID: 794 case CHIP_IP_DISCOVERY: 795 nv_set_virt_ops(adev); 796 /* try send GPU_INIT_DATA request to host */ 797 amdgpu_virt_request_init_data(adev); 798 break; 799 default: /* other chip doesn't support SRIOV */ 800 DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type); 801 break; 802 } 803 } 804 } 805 806 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev) 807 { 808 return amdgpu_sriov_is_debug(adev) ? true : false; 809 } 810 811 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev) 812 { 813 return amdgpu_sriov_is_normal(adev) ? true : false; 814 } 815 816 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev) 817 { 818 if (!amdgpu_sriov_vf(adev) || 819 amdgpu_virt_access_debugfs_is_kiq(adev)) 820 return 0; 821 822 if (amdgpu_virt_access_debugfs_is_mmio(adev)) 823 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 824 else 825 return -EPERM; 826 827 return 0; 828 } 829 830 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev) 831 { 832 if (amdgpu_sriov_vf(adev)) 833 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 834 } 835 836 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev) 837 { 838 enum amdgpu_sriov_vf_mode mode; 839 840 if (amdgpu_sriov_vf(adev)) { 841 if (amdgpu_sriov_is_pp_one_vf(adev)) 842 mode = SRIOV_VF_MODE_ONE_VF; 843 else 844 mode = SRIOV_VF_MODE_MULTI_VF; 845 } else { 846 mode = SRIOV_VF_MODE_BARE_METAL; 847 } 848 849 return mode; 850 } 851 852 void amdgpu_virt_post_reset(struct amdgpu_device *adev) 853 { 854 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3)) { 855 /* force set to GFXOFF state after reset, 856 * to avoid some invalid operation before GC enable 857 */ 858 adev->gfx.is_poweron = false; 859 } 860 861 adev->mes.ring[0].sched.ready = false; 862 } 863 864 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id) 865 { 866 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 867 case IP_VERSION(13, 0, 0): 868 /* no vf autoload, white list */ 869 if (ucode_id == AMDGPU_UCODE_ID_VCN1 || 870 ucode_id == AMDGPU_UCODE_ID_VCN) 871 return false; 872 else 873 return true; 874 case IP_VERSION(11, 0, 9): 875 case IP_VERSION(11, 0, 7): 876 /* black list for CHIP_NAVI12 and CHIP_SIENNA_CICHLID */ 877 if (ucode_id == AMDGPU_UCODE_ID_RLC_G 878 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 879 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 880 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 881 || ucode_id == AMDGPU_UCODE_ID_SMC) 882 return true; 883 else 884 return false; 885 case IP_VERSION(13, 0, 10): 886 /* white list */ 887 if (ucode_id == AMDGPU_UCODE_ID_CAP 888 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP 889 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME 890 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC 891 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK 892 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK 893 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK 894 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK 895 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK 896 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK 897 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK 898 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK 899 || ucode_id == AMDGPU_UCODE_ID_CP_MES 900 || ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA 901 || ucode_id == AMDGPU_UCODE_ID_CP_MES1 902 || ucode_id == AMDGPU_UCODE_ID_CP_MES1_DATA 903 || ucode_id == AMDGPU_UCODE_ID_VCN1 904 || ucode_id == AMDGPU_UCODE_ID_VCN) 905 return false; 906 else 907 return true; 908 default: 909 /* lagacy black list */ 910 if (ucode_id == AMDGPU_UCODE_ID_SDMA0 911 || ucode_id == AMDGPU_UCODE_ID_SDMA1 912 || ucode_id == AMDGPU_UCODE_ID_SDMA2 913 || ucode_id == AMDGPU_UCODE_ID_SDMA3 914 || ucode_id == AMDGPU_UCODE_ID_SDMA4 915 || ucode_id == AMDGPU_UCODE_ID_SDMA5 916 || ucode_id == AMDGPU_UCODE_ID_SDMA6 917 || ucode_id == AMDGPU_UCODE_ID_SDMA7 918 || ucode_id == AMDGPU_UCODE_ID_RLC_G 919 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 920 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 921 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 922 || ucode_id == AMDGPU_UCODE_ID_SMC) 923 return true; 924 else 925 return false; 926 } 927 } 928 929 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 930 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 931 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size) 932 { 933 uint32_t i; 934 935 if (!adev->virt.is_mm_bw_enabled) 936 return; 937 938 if (encode) { 939 for (i = 0; i < encode_array_size; i++) { 940 encode[i].max_width = adev->virt.encode_max_dimension_pixels; 941 encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels; 942 if (encode[i].max_width > 0) 943 encode[i].max_height = encode[i].max_pixels_per_frame / encode[i].max_width; 944 else 945 encode[i].max_height = 0; 946 } 947 } 948 949 if (decode) { 950 for (i = 0; i < decode_array_size; i++) { 951 decode[i].max_width = adev->virt.decode_max_dimension_pixels; 952 decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels; 953 if (decode[i].max_width > 0) 954 decode[i].max_height = decode[i].max_pixels_per_frame / decode[i].max_width; 955 else 956 decode[i].max_height = 0; 957 } 958 } 959 } 960 961 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 962 u32 acc_flags, u32 hwip, 963 bool write, u32 *rlcg_flag) 964 { 965 bool ret = false; 966 967 switch (hwip) { 968 case GC_HWIP: 969 if (amdgpu_sriov_reg_indirect_gc(adev)) { 970 *rlcg_flag = 971 write ? AMDGPU_RLCG_GC_WRITE : AMDGPU_RLCG_GC_READ; 972 ret = true; 973 /* only in new version, AMDGPU_REGS_NO_KIQ and 974 * AMDGPU_REGS_RLC are enabled simultaneously */ 975 } else if ((acc_flags & AMDGPU_REGS_RLC) && 976 !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) { 977 *rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY; 978 ret = true; 979 } 980 break; 981 case MMHUB_HWIP: 982 if (amdgpu_sriov_reg_indirect_mmhub(adev) && 983 (acc_flags & AMDGPU_REGS_RLC) && write) { 984 *rlcg_flag = AMDGPU_RLCG_MMHUB_WRITE; 985 ret = true; 986 } 987 break; 988 default: 989 break; 990 } 991 return ret; 992 } 993 994 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id) 995 { 996 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 997 uint32_t timeout = 50000; 998 uint32_t i, tmp; 999 uint32_t ret = 0; 1000 void *scratch_reg0; 1001 void *scratch_reg1; 1002 void *scratch_reg2; 1003 void *scratch_reg3; 1004 void *spare_int; 1005 1006 if (!adev->gfx.rlc.rlcg_reg_access_supported) { 1007 dev_err(adev->dev, 1008 "indirect registers access through rlcg is not available\n"); 1009 return 0; 1010 } 1011 1012 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { 1013 dev_err(adev->dev, "invalid xcc\n"); 1014 return 0; 1015 } 1016 1017 if (amdgpu_device_skip_hw_access(adev)) 1018 return 0; 1019 1020 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; 1021 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0; 1022 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1; 1023 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; 1024 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3; 1025 1026 mutex_lock(&adev->virt.rlcg_reg_lock); 1027 1028 if (reg_access_ctrl->spare_int) 1029 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int; 1030 1031 if (offset == reg_access_ctrl->grbm_cntl) { 1032 /* if the target reg offset is grbm_cntl, write to scratch_reg2 */ 1033 writel(v, scratch_reg2); 1034 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY) 1035 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 1036 } else if (offset == reg_access_ctrl->grbm_idx) { 1037 /* if the target reg offset is grbm_idx, write to scratch_reg3 */ 1038 writel(v, scratch_reg3); 1039 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY) 1040 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 1041 } else { 1042 /* 1043 * SCRATCH_REG0 = read/write value 1044 * SCRATCH_REG1[30:28] = command 1045 * SCRATCH_REG1[19:0] = address in dword 1046 * SCRATCH_REG1[27:24] = Error reporting 1047 */ 1048 writel(v, scratch_reg0); 1049 writel((offset | flag), scratch_reg1); 1050 if (reg_access_ctrl->spare_int) 1051 writel(1, spare_int); 1052 1053 for (i = 0; i < timeout; i++) { 1054 tmp = readl(scratch_reg1); 1055 if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK)) 1056 break; 1057 udelay(10); 1058 } 1059 1060 tmp = readl(scratch_reg1); 1061 if (i >= timeout || (tmp & AMDGPU_RLCG_SCRATCH1_ERROR_MASK) != 0) { 1062 if (amdgpu_sriov_rlcg_error_report_enabled(adev)) { 1063 if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) { 1064 dev_err(adev->dev, 1065 "vfgate is disabled, rlcg failed to program reg: 0x%05x\n", offset); 1066 } else if (tmp & AMDGPU_RLCG_WRONG_OPERATION_TYPE) { 1067 dev_err(adev->dev, 1068 "wrong operation type, rlcg failed to program reg: 0x%05x\n", offset); 1069 } else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) { 1070 dev_err(adev->dev, 1071 "register is not in range, rlcg failed to program reg: 0x%05x\n", offset); 1072 } else { 1073 dev_err(adev->dev, 1074 "unknown error type, rlcg failed to program reg: 0x%05x\n", offset); 1075 } 1076 } else { 1077 dev_err(adev->dev, 1078 "timeout: rlcg faled to program reg: 0x%05x\n", offset); 1079 } 1080 } 1081 } 1082 1083 ret = readl(scratch_reg0); 1084 1085 mutex_unlock(&adev->virt.rlcg_reg_lock); 1086 1087 return ret; 1088 } 1089 1090 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 1091 u32 offset, u32 value, 1092 u32 acc_flags, u32 hwip, u32 xcc_id) 1093 { 1094 u32 rlcg_flag; 1095 1096 if (amdgpu_device_skip_hw_access(adev)) 1097 return; 1098 1099 if (!amdgpu_sriov_runtime(adev) && 1100 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) { 1101 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag, xcc_id); 1102 return; 1103 } 1104 1105 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1106 WREG32_NO_KIQ(offset, value); 1107 else 1108 WREG32(offset, value); 1109 } 1110 1111 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 1112 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id) 1113 { 1114 u32 rlcg_flag; 1115 1116 if (amdgpu_device_skip_hw_access(adev)) 1117 return 0; 1118 1119 if (!amdgpu_sriov_runtime(adev) && 1120 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag)) 1121 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag, xcc_id); 1122 1123 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1124 return RREG32_NO_KIQ(offset); 1125 else 1126 return RREG32(offset); 1127 } 1128 1129 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev) 1130 { 1131 bool xnack_mode = true; 1132 1133 if (amdgpu_sriov_vf(adev) && 1134 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 1135 xnack_mode = false; 1136 1137 return xnack_mode; 1138 } 1139