1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/module.h> 25 26 #ifdef CONFIG_X86 27 #include <asm/hypervisor.h> 28 #endif 29 30 #include <drm/drm_drv.h> 31 #include <xen/xen.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_ras.h" 35 #include "vi.h" 36 #include "soc15.h" 37 #include "nv.h" 38 39 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \ 40 do { \ 41 vf2pf_info->ucode_info[ucode].id = ucode; \ 42 vf2pf_info->ucode_info[ucode].version = ver; \ 43 } while (0) 44 45 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) 46 { 47 /* By now all MMIO pages except mailbox are blocked */ 48 /* if blocking is enabled in hypervisor. Choose the */ 49 /* SCRATCH_REG0 to test. */ 50 return RREG32_NO_KIQ(0xc040) == 0xffffffff; 51 } 52 53 void amdgpu_virt_init_setting(struct amdgpu_device *adev) 54 { 55 struct drm_device *ddev = adev_to_drm(adev); 56 57 /* enable virtual display */ 58 if (adev->asic_type != CHIP_ALDEBARAN && 59 adev->asic_type != CHIP_ARCTURUS && 60 ((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) { 61 if (adev->mode_info.num_crtc == 0) 62 adev->mode_info.num_crtc = 1; 63 adev->enable_virtual_display = true; 64 } 65 ddev->driver_features &= ~DRIVER_ATOMIC; 66 adev->cg_flags = 0; 67 adev->pg_flags = 0; 68 69 /* Reduce kcq number to 2 to reduce latency */ 70 if (amdgpu_num_kcq == -1) 71 amdgpu_num_kcq = 2; 72 } 73 74 /** 75 * amdgpu_virt_request_full_gpu() - request full gpu access 76 * @adev: amdgpu device. 77 * @init: is driver init time. 78 * When start to init/fini driver, first need to request full gpu access. 79 * Return: Zero if request success, otherwise will return error. 80 */ 81 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init) 82 { 83 struct amdgpu_virt *virt = &adev->virt; 84 int r; 85 86 if (virt->ops && virt->ops->req_full_gpu) { 87 r = virt->ops->req_full_gpu(adev, init); 88 if (r) 89 return r; 90 91 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 92 } 93 94 return 0; 95 } 96 97 /** 98 * amdgpu_virt_release_full_gpu() - release full gpu access 99 * @adev: amdgpu device. 100 * @init: is driver init time. 101 * When finishing driver init/fini, need to release full gpu access. 102 * Return: Zero if release success, otherwise will returen error. 103 */ 104 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init) 105 { 106 struct amdgpu_virt *virt = &adev->virt; 107 int r; 108 109 if (virt->ops && virt->ops->rel_full_gpu) { 110 r = virt->ops->rel_full_gpu(adev, init); 111 if (r) 112 return r; 113 114 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 115 } 116 return 0; 117 } 118 119 /** 120 * amdgpu_virt_reset_gpu() - reset gpu 121 * @adev: amdgpu device. 122 * Send reset command to GPU hypervisor to reset GPU that VM is using 123 * Return: Zero if reset success, otherwise will return error. 124 */ 125 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev) 126 { 127 struct amdgpu_virt *virt = &adev->virt; 128 int r; 129 130 if (virt->ops && virt->ops->reset_gpu) { 131 r = virt->ops->reset_gpu(adev); 132 if (r) 133 return r; 134 135 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 136 } 137 138 return 0; 139 } 140 141 void amdgpu_virt_request_init_data(struct amdgpu_device *adev) 142 { 143 struct amdgpu_virt *virt = &adev->virt; 144 145 if (virt->ops && virt->ops->req_init_data) 146 virt->ops->req_init_data(adev); 147 148 if (adev->virt.req_init_data_ver > 0) 149 DRM_INFO("host supports REQ_INIT_DATA handshake\n"); 150 else 151 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n"); 152 } 153 154 /** 155 * amdgpu_virt_wait_reset() - wait for reset gpu completed 156 * @adev: amdgpu device. 157 * Wait for GPU reset completed. 158 * Return: Zero if reset success, otherwise will return error. 159 */ 160 int amdgpu_virt_wait_reset(struct amdgpu_device *adev) 161 { 162 struct amdgpu_virt *virt = &adev->virt; 163 164 if (!virt->ops || !virt->ops->wait_reset) 165 return -EINVAL; 166 167 return virt->ops->wait_reset(adev); 168 } 169 170 /** 171 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table 172 * @adev: amdgpu device. 173 * MM table is used by UVD and VCE for its initialization 174 * Return: Zero if allocate success. 175 */ 176 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev) 177 { 178 int r; 179 180 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) 181 return 0; 182 183 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 184 AMDGPU_GEM_DOMAIN_VRAM | 185 AMDGPU_GEM_DOMAIN_GTT, 186 &adev->virt.mm_table.bo, 187 &adev->virt.mm_table.gpu_addr, 188 (void *)&adev->virt.mm_table.cpu_addr); 189 if (r) { 190 DRM_ERROR("failed to alloc mm table and error = %d.\n", r); 191 return r; 192 } 193 194 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); 195 DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n", 196 adev->virt.mm_table.gpu_addr, 197 adev->virt.mm_table.cpu_addr); 198 return 0; 199 } 200 201 /** 202 * amdgpu_virt_free_mm_table() - free mm table memory 203 * @adev: amdgpu device. 204 * Free MM table memory 205 */ 206 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev) 207 { 208 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) 209 return; 210 211 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo, 212 &adev->virt.mm_table.gpu_addr, 213 (void *)&adev->virt.mm_table.cpu_addr); 214 adev->virt.mm_table.gpu_addr = 0; 215 } 216 217 218 unsigned int amd_sriov_msg_checksum(void *obj, 219 unsigned long obj_size, 220 unsigned int key, 221 unsigned int checksum) 222 { 223 unsigned int ret = key; 224 unsigned long i = 0; 225 unsigned char *pos; 226 227 pos = (char *)obj; 228 /* calculate checksum */ 229 for (i = 0; i < obj_size; ++i) 230 ret += *(pos + i); 231 /* minus the checksum itself */ 232 pos = (char *)&checksum; 233 for (i = 0; i < sizeof(checksum); ++i) 234 ret -= *(pos + i); 235 return ret; 236 } 237 238 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev) 239 { 240 struct amdgpu_virt *virt = &adev->virt; 241 struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data; 242 /* GPU will be marked bad on host if bp count more then 10, 243 * so alloc 512 is enough. 244 */ 245 unsigned int align_space = 512; 246 void *bps = NULL; 247 struct amdgpu_bo **bps_bo = NULL; 248 249 *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL); 250 if (!*data) 251 goto data_failure; 252 253 bps = kmalloc_array(align_space, sizeof((*data)->bps), GFP_KERNEL); 254 if (!bps) 255 goto bps_failure; 256 257 bps_bo = kmalloc_array(align_space, sizeof((*data)->bps_bo), GFP_KERNEL); 258 if (!bps_bo) 259 goto bps_bo_failure; 260 261 (*data)->bps = bps; 262 (*data)->bps_bo = bps_bo; 263 (*data)->count = 0; 264 (*data)->last_reserved = 0; 265 266 virt->ras_init_done = true; 267 268 return 0; 269 270 bps_bo_failure: 271 kfree(bps); 272 bps_failure: 273 kfree(*data); 274 data_failure: 275 return -ENOMEM; 276 } 277 278 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev) 279 { 280 struct amdgpu_virt *virt = &adev->virt; 281 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 282 struct amdgpu_bo *bo; 283 int i; 284 285 if (!data) 286 return; 287 288 for (i = data->last_reserved - 1; i >= 0; i--) { 289 bo = data->bps_bo[i]; 290 amdgpu_bo_free_kernel(&bo, NULL, NULL); 291 data->bps_bo[i] = bo; 292 data->last_reserved = i; 293 } 294 } 295 296 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev) 297 { 298 struct amdgpu_virt *virt = &adev->virt; 299 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 300 301 virt->ras_init_done = false; 302 303 if (!data) 304 return; 305 306 amdgpu_virt_ras_release_bp(adev); 307 308 kfree(data->bps); 309 kfree(data->bps_bo); 310 kfree(data); 311 virt->virt_eh_data = NULL; 312 } 313 314 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev, 315 struct eeprom_table_record *bps, int pages) 316 { 317 struct amdgpu_virt *virt = &adev->virt; 318 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 319 320 if (!data) 321 return; 322 323 memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); 324 data->count += pages; 325 } 326 327 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev) 328 { 329 struct amdgpu_virt *virt = &adev->virt; 330 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 331 struct amdgpu_bo *bo = NULL; 332 uint64_t bp; 333 int i; 334 335 if (!data) 336 return; 337 338 for (i = data->last_reserved; i < data->count; i++) { 339 bp = data->bps[i].retired_page; 340 341 /* There are two cases of reserve error should be ignored: 342 * 1) a ras bad page has been allocated (used by someone); 343 * 2) a ras bad page has been reserved (duplicate error injection 344 * for one page); 345 */ 346 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, 347 AMDGPU_GPU_PAGE_SIZE, 348 &bo, NULL)) 349 DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp); 350 351 data->bps_bo[i] = bo; 352 data->last_reserved = i + 1; 353 bo = NULL; 354 } 355 } 356 357 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev, 358 uint64_t retired_page) 359 { 360 struct amdgpu_virt *virt = &adev->virt; 361 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 362 int i; 363 364 if (!data) 365 return true; 366 367 for (i = 0; i < data->count; i++) 368 if (retired_page == data->bps[i].retired_page) 369 return true; 370 371 return false; 372 } 373 374 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev, 375 uint64_t bp_block_offset, uint32_t bp_block_size) 376 { 377 struct eeprom_table_record bp; 378 uint64_t retired_page; 379 uint32_t bp_idx, bp_cnt; 380 void *vram_usage_va = NULL; 381 382 if (adev->mman.fw_vram_usage_va) 383 vram_usage_va = adev->mman.fw_vram_usage_va; 384 else 385 vram_usage_va = adev->mman.drv_vram_usage_va; 386 387 if (bp_block_size) { 388 bp_cnt = bp_block_size / sizeof(uint64_t); 389 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) { 390 retired_page = *(uint64_t *)(vram_usage_va + 391 bp_block_offset + bp_idx * sizeof(uint64_t)); 392 bp.retired_page = retired_page; 393 394 if (amdgpu_virt_ras_check_bad_page(adev, retired_page)) 395 continue; 396 397 amdgpu_virt_ras_add_bps(adev, &bp, 1); 398 399 amdgpu_virt_ras_reserve_bps(adev); 400 } 401 } 402 } 403 404 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) 405 { 406 struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf; 407 uint32_t checksum; 408 uint32_t checkval; 409 410 uint32_t i; 411 uint32_t tmp; 412 413 if (adev->virt.fw_reserve.p_pf2vf == NULL) 414 return -EINVAL; 415 416 if (pf2vf_info->size > 1024) { 417 DRM_ERROR("invalid pf2vf message size\n"); 418 return -EINVAL; 419 } 420 421 switch (pf2vf_info->version) { 422 case 1: 423 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum; 424 checkval = amd_sriov_msg_checksum( 425 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 426 adev->virt.fw_reserve.checksum_key, checksum); 427 if (checksum != checkval) { 428 DRM_ERROR("invalid pf2vf message\n"); 429 return -EINVAL; 430 } 431 432 adev->virt.gim_feature = 433 ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags; 434 break; 435 case 2: 436 /* TODO: missing key, need to add it later */ 437 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum; 438 checkval = amd_sriov_msg_checksum( 439 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 440 0, checksum); 441 if (checksum != checkval) { 442 DRM_ERROR("invalid pf2vf message\n"); 443 return -EINVAL; 444 } 445 446 adev->virt.vf2pf_update_interval_ms = 447 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms; 448 adev->virt.gim_feature = 449 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all; 450 adev->virt.reg_access = 451 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all; 452 453 adev->virt.decode_max_dimension_pixels = 0; 454 adev->virt.decode_max_frame_pixels = 0; 455 adev->virt.encode_max_dimension_pixels = 0; 456 adev->virt.encode_max_frame_pixels = 0; 457 adev->virt.is_mm_bw_enabled = false; 458 for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) { 459 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels; 460 adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels); 461 462 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels; 463 adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels); 464 465 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels; 466 adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels); 467 468 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels; 469 adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels); 470 } 471 if ((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0)) 472 adev->virt.is_mm_bw_enabled = true; 473 474 adev->unique_id = 475 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid; 476 break; 477 default: 478 DRM_ERROR("invalid pf2vf version\n"); 479 return -EINVAL; 480 } 481 482 /* correct too large or too little interval value */ 483 if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000) 484 adev->virt.vf2pf_update_interval_ms = 2000; 485 486 return 0; 487 } 488 489 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev) 490 { 491 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 492 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 493 494 if (adev->virt.fw_reserve.p_vf2pf == NULL) 495 return; 496 497 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version); 498 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version); 499 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version); 500 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); 501 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); 502 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); 503 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); 504 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); 505 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); 506 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); 507 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); 508 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); 509 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version); 510 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD, 511 adev->psp.asd_context.bin_desc.fw_version); 512 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS, 513 adev->psp.ras_context.context.bin_desc.fw_version); 514 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI, 515 adev->psp.xgmi_context.context.bin_desc.fw_version); 516 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version); 517 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version); 518 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version); 519 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version); 520 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version); 521 } 522 523 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) 524 { 525 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 526 527 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 528 529 if (adev->virt.fw_reserve.p_vf2pf == NULL) 530 return -EINVAL; 531 532 memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info)); 533 534 vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info); 535 vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER; 536 537 #ifdef MODULE 538 if (THIS_MODULE->version != NULL) 539 strcpy(vf2pf_info->driver_version, THIS_MODULE->version); 540 else 541 #endif 542 strcpy(vf2pf_info->driver_version, "N/A"); 543 544 vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all 545 vf2pf_info->driver_cert = 0; 546 vf2pf_info->os_info.all = 0; 547 548 vf2pf_info->fb_usage = 549 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20; 550 vf2pf_info->fb_vis_usage = 551 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20; 552 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20; 553 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20; 554 555 amdgpu_virt_populate_vf2pf_ucode_info(adev); 556 557 /* TODO: read dynamic info */ 558 vf2pf_info->gfx_usage = 0; 559 vf2pf_info->compute_usage = 0; 560 vf2pf_info->encode_usage = 0; 561 vf2pf_info->decode_usage = 0; 562 563 vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr; 564 vf2pf_info->checksum = 565 amd_sriov_msg_checksum( 566 vf2pf_info, vf2pf_info->header.size, 0, 0); 567 568 return 0; 569 } 570 571 static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work) 572 { 573 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work); 574 int ret; 575 576 ret = amdgpu_virt_read_pf2vf_data(adev); 577 if (ret) 578 goto out; 579 amdgpu_virt_write_vf2pf_data(adev); 580 581 out: 582 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); 583 } 584 585 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev) 586 { 587 if (adev->virt.vf2pf_update_interval_ms != 0) { 588 DRM_INFO("clean up the vf2pf work item\n"); 589 cancel_delayed_work_sync(&adev->virt.vf2pf_work); 590 adev->virt.vf2pf_update_interval_ms = 0; 591 } 592 } 593 594 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) 595 { 596 adev->virt.fw_reserve.p_pf2vf = NULL; 597 adev->virt.fw_reserve.p_vf2pf = NULL; 598 adev->virt.vf2pf_update_interval_ms = 0; 599 600 if (adev->mman.fw_vram_usage_va && adev->mman.drv_vram_usage_va) { 601 DRM_WARN("Currently fw_vram and drv_vram should not have values at the same time!"); 602 } else if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { 603 /* go through this logic in ip_init and reset to init workqueue*/ 604 amdgpu_virt_exchange_data(adev); 605 606 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item); 607 schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms)); 608 } else if (adev->bios != NULL) { 609 /* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/ 610 adev->virt.fw_reserve.p_pf2vf = 611 (struct amd_sriov_msg_pf2vf_info_header *) 612 (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 613 614 amdgpu_virt_read_pf2vf_data(adev); 615 } 616 } 617 618 619 void amdgpu_virt_exchange_data(struct amdgpu_device *adev) 620 { 621 uint64_t bp_block_offset = 0; 622 uint32_t bp_block_size = 0; 623 struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL; 624 625 if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { 626 if (adev->mman.fw_vram_usage_va) { 627 adev->virt.fw_reserve.p_pf2vf = 628 (struct amd_sriov_msg_pf2vf_info_header *) 629 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 630 adev->virt.fw_reserve.p_vf2pf = 631 (struct amd_sriov_msg_vf2pf_info_header *) 632 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 633 } else if (adev->mman.drv_vram_usage_va) { 634 adev->virt.fw_reserve.p_pf2vf = 635 (struct amd_sriov_msg_pf2vf_info_header *) 636 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 637 adev->virt.fw_reserve.p_vf2pf = 638 (struct amd_sriov_msg_vf2pf_info_header *) 639 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 640 } 641 642 amdgpu_virt_read_pf2vf_data(adev); 643 amdgpu_virt_write_vf2pf_data(adev); 644 645 /* bad page handling for version 2 */ 646 if (adev->virt.fw_reserve.p_pf2vf->version == 2) { 647 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf; 648 649 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) | 650 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000); 651 bp_block_size = pf2vf_v2->bp_block_size; 652 653 if (bp_block_size && !adev->virt.ras_init_done) 654 amdgpu_virt_init_ras_err_handler_data(adev); 655 656 if (adev->virt.ras_init_done) 657 amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size); 658 } 659 } 660 } 661 662 void amdgpu_detect_virtualization(struct amdgpu_device *adev) 663 { 664 uint32_t reg; 665 666 switch (adev->asic_type) { 667 case CHIP_TONGA: 668 case CHIP_FIJI: 669 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); 670 break; 671 case CHIP_VEGA10: 672 case CHIP_VEGA20: 673 case CHIP_NAVI10: 674 case CHIP_NAVI12: 675 case CHIP_SIENNA_CICHLID: 676 case CHIP_ARCTURUS: 677 case CHIP_ALDEBARAN: 678 case CHIP_IP_DISCOVERY: 679 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER); 680 break; 681 default: /* other chip doesn't support SRIOV */ 682 reg = 0; 683 break; 684 } 685 686 if (reg & 1) 687 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 688 689 if (reg & 0x80000000) 690 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 691 692 if (!reg) { 693 /* passthrough mode exclus sriov mod */ 694 if (is_virtual_machine() && !xen_initial_domain()) 695 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 696 } 697 698 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) 699 /* VF MMIO access (except mailbox range) from CPU 700 * will be blocked during sriov runtime 701 */ 702 adev->virt.caps |= AMDGPU_VF_MMIO_ACCESS_PROTECT; 703 704 /* we have the ability to check now */ 705 if (amdgpu_sriov_vf(adev)) { 706 switch (adev->asic_type) { 707 case CHIP_TONGA: 708 case CHIP_FIJI: 709 vi_set_virt_ops(adev); 710 break; 711 case CHIP_VEGA10: 712 soc15_set_virt_ops(adev); 713 #ifdef CONFIG_X86 714 /* not send GPU_INIT_DATA with MS_HYPERV*/ 715 if (!hypervisor_is_type(X86_HYPER_MS_HYPERV)) 716 #endif 717 /* send a dummy GPU_INIT_DATA request to host on vega10 */ 718 amdgpu_virt_request_init_data(adev); 719 break; 720 case CHIP_VEGA20: 721 case CHIP_ARCTURUS: 722 case CHIP_ALDEBARAN: 723 soc15_set_virt_ops(adev); 724 break; 725 case CHIP_NAVI10: 726 case CHIP_NAVI12: 727 case CHIP_SIENNA_CICHLID: 728 case CHIP_IP_DISCOVERY: 729 nv_set_virt_ops(adev); 730 /* try send GPU_INIT_DATA request to host */ 731 amdgpu_virt_request_init_data(adev); 732 break; 733 default: /* other chip doesn't support SRIOV */ 734 DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type); 735 break; 736 } 737 } 738 } 739 740 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev) 741 { 742 return amdgpu_sriov_is_debug(adev) ? true : false; 743 } 744 745 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev) 746 { 747 return amdgpu_sriov_is_normal(adev) ? true : false; 748 } 749 750 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev) 751 { 752 if (!amdgpu_sriov_vf(adev) || 753 amdgpu_virt_access_debugfs_is_kiq(adev)) 754 return 0; 755 756 if (amdgpu_virt_access_debugfs_is_mmio(adev)) 757 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 758 else 759 return -EPERM; 760 761 return 0; 762 } 763 764 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev) 765 { 766 if (amdgpu_sriov_vf(adev)) 767 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 768 } 769 770 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev) 771 { 772 enum amdgpu_sriov_vf_mode mode; 773 774 if (amdgpu_sriov_vf(adev)) { 775 if (amdgpu_sriov_is_pp_one_vf(adev)) 776 mode = SRIOV_VF_MODE_ONE_VF; 777 else 778 mode = SRIOV_VF_MODE_MULTI_VF; 779 } else { 780 mode = SRIOV_VF_MODE_BARE_METAL; 781 } 782 783 return mode; 784 } 785 786 void amdgpu_virt_post_reset(struct amdgpu_device *adev) 787 { 788 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3)) { 789 /* force set to GFXOFF state after reset, 790 * to avoid some invalid operation before GC enable 791 */ 792 adev->gfx.is_poweron = false; 793 } 794 } 795 796 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id) 797 { 798 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 799 case IP_VERSION(13, 0, 0): 800 /* no vf autoload, white list */ 801 if (ucode_id == AMDGPU_UCODE_ID_VCN1 || 802 ucode_id == AMDGPU_UCODE_ID_VCN) 803 return false; 804 else 805 return true; 806 case IP_VERSION(11, 0, 9): 807 case IP_VERSION(11, 0, 7): 808 /* black list for CHIP_NAVI12 and CHIP_SIENNA_CICHLID */ 809 if (ucode_id == AMDGPU_UCODE_ID_RLC_G 810 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 811 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 812 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 813 || ucode_id == AMDGPU_UCODE_ID_SMC) 814 return true; 815 else 816 return false; 817 case IP_VERSION(13, 0, 10): 818 /* white list */ 819 if (ucode_id == AMDGPU_UCODE_ID_CAP 820 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP 821 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME 822 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC 823 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK 824 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK 825 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK 826 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK 827 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK 828 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK 829 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK 830 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK 831 || ucode_id == AMDGPU_UCODE_ID_CP_MES 832 || ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA 833 || ucode_id == AMDGPU_UCODE_ID_CP_MES1 834 || ucode_id == AMDGPU_UCODE_ID_CP_MES1_DATA 835 || ucode_id == AMDGPU_UCODE_ID_VCN1 836 || ucode_id == AMDGPU_UCODE_ID_VCN) 837 return false; 838 else 839 return true; 840 default: 841 /* lagacy black list */ 842 if (ucode_id == AMDGPU_UCODE_ID_SDMA0 843 || ucode_id == AMDGPU_UCODE_ID_SDMA1 844 || ucode_id == AMDGPU_UCODE_ID_SDMA2 845 || ucode_id == AMDGPU_UCODE_ID_SDMA3 846 || ucode_id == AMDGPU_UCODE_ID_SDMA4 847 || ucode_id == AMDGPU_UCODE_ID_SDMA5 848 || ucode_id == AMDGPU_UCODE_ID_SDMA6 849 || ucode_id == AMDGPU_UCODE_ID_SDMA7 850 || ucode_id == AMDGPU_UCODE_ID_RLC_G 851 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 852 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 853 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 854 || ucode_id == AMDGPU_UCODE_ID_SMC) 855 return true; 856 else 857 return false; 858 } 859 } 860 861 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 862 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 863 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size) 864 { 865 uint32_t i; 866 867 if (!adev->virt.is_mm_bw_enabled) 868 return; 869 870 if (encode) { 871 for (i = 0; i < encode_array_size; i++) { 872 encode[i].max_width = adev->virt.encode_max_dimension_pixels; 873 encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels; 874 if (encode[i].max_width > 0) 875 encode[i].max_height = encode[i].max_pixels_per_frame / encode[i].max_width; 876 else 877 encode[i].max_height = 0; 878 } 879 } 880 881 if (decode) { 882 for (i = 0; i < decode_array_size; i++) { 883 decode[i].max_width = adev->virt.decode_max_dimension_pixels; 884 decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels; 885 if (decode[i].max_width > 0) 886 decode[i].max_height = decode[i].max_pixels_per_frame / decode[i].max_width; 887 else 888 decode[i].max_height = 0; 889 } 890 } 891 } 892 893 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 894 u32 acc_flags, u32 hwip, 895 bool write, u32 *rlcg_flag) 896 { 897 bool ret = false; 898 899 switch (hwip) { 900 case GC_HWIP: 901 if (amdgpu_sriov_reg_indirect_gc(adev)) { 902 *rlcg_flag = 903 write ? AMDGPU_RLCG_GC_WRITE : AMDGPU_RLCG_GC_READ; 904 ret = true; 905 /* only in new version, AMDGPU_REGS_NO_KIQ and 906 * AMDGPU_REGS_RLC are enabled simultaneously */ 907 } else if ((acc_flags & AMDGPU_REGS_RLC) && 908 !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) { 909 *rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY; 910 ret = true; 911 } 912 break; 913 case MMHUB_HWIP: 914 if (amdgpu_sriov_reg_indirect_mmhub(adev) && 915 (acc_flags & AMDGPU_REGS_RLC) && write) { 916 *rlcg_flag = AMDGPU_RLCG_MMHUB_WRITE; 917 ret = true; 918 } 919 break; 920 default: 921 break; 922 } 923 return ret; 924 } 925 926 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id) 927 { 928 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 929 uint32_t timeout = 50000; 930 uint32_t i, tmp; 931 uint32_t ret = 0; 932 void *scratch_reg0; 933 void *scratch_reg1; 934 void *scratch_reg2; 935 void *scratch_reg3; 936 void *spare_int; 937 938 if (!adev->gfx.rlc.rlcg_reg_access_supported) { 939 dev_err(adev->dev, 940 "indirect registers access through rlcg is not available\n"); 941 return 0; 942 } 943 944 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { 945 dev_err(adev->dev, "invalid xcc\n"); 946 return 0; 947 } 948 949 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; 950 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0; 951 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1; 952 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; 953 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3; 954 if (reg_access_ctrl->spare_int) 955 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int; 956 957 if (offset == reg_access_ctrl->grbm_cntl) { 958 /* if the target reg offset is grbm_cntl, write to scratch_reg2 */ 959 writel(v, scratch_reg2); 960 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY) 961 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 962 } else if (offset == reg_access_ctrl->grbm_idx) { 963 /* if the target reg offset is grbm_idx, write to scratch_reg3 */ 964 writel(v, scratch_reg3); 965 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY) 966 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 967 } else { 968 /* 969 * SCRATCH_REG0 = read/write value 970 * SCRATCH_REG1[30:28] = command 971 * SCRATCH_REG1[19:0] = address in dword 972 * SCRATCH_REG1[26:24] = Error reporting 973 */ 974 writel(v, scratch_reg0); 975 writel((offset | flag), scratch_reg1); 976 if (reg_access_ctrl->spare_int) 977 writel(1, spare_int); 978 979 for (i = 0; i < timeout; i++) { 980 tmp = readl(scratch_reg1); 981 if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK)) 982 break; 983 udelay(10); 984 } 985 986 if (i >= timeout) { 987 if (amdgpu_sriov_rlcg_error_report_enabled(adev)) { 988 if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) { 989 dev_err(adev->dev, 990 "vfgate is disabled, rlcg failed to program reg: 0x%05x\n", offset); 991 } else if (tmp & AMDGPU_RLCG_WRONG_OPERATION_TYPE) { 992 dev_err(adev->dev, 993 "wrong operation type, rlcg failed to program reg: 0x%05x\n", offset); 994 } else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) { 995 dev_err(adev->dev, 996 "register is not in range, rlcg failed to program reg: 0x%05x\n", offset); 997 } else { 998 dev_err(adev->dev, 999 "unknown error type, rlcg failed to program reg: 0x%05x\n", offset); 1000 } 1001 } else { 1002 dev_err(adev->dev, 1003 "timeout: rlcg faled to program reg: 0x%05x\n", offset); 1004 } 1005 } 1006 } 1007 1008 ret = readl(scratch_reg0); 1009 return ret; 1010 } 1011 1012 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 1013 u32 offset, u32 value, 1014 u32 acc_flags, u32 hwip, u32 xcc_id) 1015 { 1016 u32 rlcg_flag; 1017 1018 if (!amdgpu_sriov_runtime(adev) && 1019 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) { 1020 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag, xcc_id); 1021 return; 1022 } 1023 1024 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1025 WREG32_NO_KIQ(offset, value); 1026 else 1027 WREG32(offset, value); 1028 } 1029 1030 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 1031 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id) 1032 { 1033 u32 rlcg_flag; 1034 1035 if (!amdgpu_sriov_runtime(adev) && 1036 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag)) 1037 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag, xcc_id); 1038 1039 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1040 return RREG32_NO_KIQ(offset); 1041 else 1042 return RREG32(offset); 1043 } 1044 1045 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev) 1046 { 1047 bool xnack_mode = true; 1048 1049 if (amdgpu_sriov_vf(adev) && 1050 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 1051 xnack_mode = false; 1052 1053 return xnack_mode; 1054 } 1055