1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/module.h> 25 26 #ifdef CONFIG_X86 27 #include <asm/hypervisor.h> 28 #endif 29 30 #include <drm/drm_drv.h> 31 #include <xen/xen.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_ras.h" 35 #include "amdgpu_reset.h" 36 #include "vi.h" 37 #include "soc15.h" 38 #include "nv.h" 39 40 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \ 41 do { \ 42 vf2pf_info->ucode_info[ucode].id = ucode; \ 43 vf2pf_info->ucode_info[ucode].version = ver; \ 44 } while (0) 45 46 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) 47 { 48 /* By now all MMIO pages except mailbox are blocked */ 49 /* if blocking is enabled in hypervisor. Choose the */ 50 /* SCRATCH_REG0 to test. */ 51 return RREG32_NO_KIQ(0xc040) == 0xffffffff; 52 } 53 54 void amdgpu_virt_init_setting(struct amdgpu_device *adev) 55 { 56 struct drm_device *ddev = adev_to_drm(adev); 57 58 /* enable virtual display */ 59 if (adev->asic_type != CHIP_ALDEBARAN && 60 adev->asic_type != CHIP_ARCTURUS && 61 ((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) { 62 if (adev->mode_info.num_crtc == 0) 63 adev->mode_info.num_crtc = 1; 64 adev->enable_virtual_display = true; 65 } 66 ddev->driver_features &= ~DRIVER_ATOMIC; 67 adev->cg_flags = 0; 68 adev->pg_flags = 0; 69 70 /* Reduce kcq number to 2 to reduce latency */ 71 if (amdgpu_num_kcq == -1) 72 amdgpu_num_kcq = 2; 73 } 74 75 /** 76 * amdgpu_virt_request_full_gpu() - request full gpu access 77 * @adev: amdgpu device. 78 * @init: is driver init time. 79 * When start to init/fini driver, first need to request full gpu access. 80 * Return: Zero if request success, otherwise will return error. 81 */ 82 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init) 83 { 84 struct amdgpu_virt *virt = &adev->virt; 85 int r; 86 87 if (virt->ops && virt->ops->req_full_gpu) { 88 r = virt->ops->req_full_gpu(adev, init); 89 if (r) 90 return r; 91 92 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 93 } 94 95 return 0; 96 } 97 98 /** 99 * amdgpu_virt_release_full_gpu() - release full gpu access 100 * @adev: amdgpu device. 101 * @init: is driver init time. 102 * When finishing driver init/fini, need to release full gpu access. 103 * Return: Zero if release success, otherwise will returen error. 104 */ 105 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init) 106 { 107 struct amdgpu_virt *virt = &adev->virt; 108 int r; 109 110 if (virt->ops && virt->ops->rel_full_gpu) { 111 r = virt->ops->rel_full_gpu(adev, init); 112 if (r) 113 return r; 114 115 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 116 } 117 return 0; 118 } 119 120 /** 121 * amdgpu_virt_reset_gpu() - reset gpu 122 * @adev: amdgpu device. 123 * Send reset command to GPU hypervisor to reset GPU that VM is using 124 * Return: Zero if reset success, otherwise will return error. 125 */ 126 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev) 127 { 128 struct amdgpu_virt *virt = &adev->virt; 129 int r; 130 131 if (virt->ops && virt->ops->reset_gpu) { 132 r = virt->ops->reset_gpu(adev); 133 if (r) 134 return r; 135 136 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 137 } 138 139 return 0; 140 } 141 142 void amdgpu_virt_request_init_data(struct amdgpu_device *adev) 143 { 144 struct amdgpu_virt *virt = &adev->virt; 145 146 if (virt->ops && virt->ops->req_init_data) 147 virt->ops->req_init_data(adev); 148 149 if (adev->virt.req_init_data_ver > 0) 150 DRM_INFO("host supports REQ_INIT_DATA handshake\n"); 151 else 152 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n"); 153 } 154 155 /** 156 * amdgpu_virt_ready_to_reset() - send ready to reset to host 157 * @adev: amdgpu device. 158 * Send ready to reset message to GPU hypervisor to signal we have stopped GPU 159 * activity and is ready for host FLR 160 */ 161 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev) 162 { 163 struct amdgpu_virt *virt = &adev->virt; 164 165 if (virt->ops && virt->ops->reset_gpu) 166 virt->ops->ready_to_reset(adev); 167 } 168 169 /** 170 * amdgpu_virt_wait_reset() - wait for reset gpu completed 171 * @adev: amdgpu device. 172 * Wait for GPU reset completed. 173 * Return: Zero if reset success, otherwise will return error. 174 */ 175 int amdgpu_virt_wait_reset(struct amdgpu_device *adev) 176 { 177 struct amdgpu_virt *virt = &adev->virt; 178 179 if (!virt->ops || !virt->ops->wait_reset) 180 return -EINVAL; 181 182 return virt->ops->wait_reset(adev); 183 } 184 185 /** 186 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table 187 * @adev: amdgpu device. 188 * MM table is used by UVD and VCE for its initialization 189 * Return: Zero if allocate success. 190 */ 191 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev) 192 { 193 int r; 194 195 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) 196 return 0; 197 198 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 199 AMDGPU_GEM_DOMAIN_VRAM | 200 AMDGPU_GEM_DOMAIN_GTT, 201 &adev->virt.mm_table.bo, 202 &adev->virt.mm_table.gpu_addr, 203 (void *)&adev->virt.mm_table.cpu_addr); 204 if (r) { 205 DRM_ERROR("failed to alloc mm table and error = %d.\n", r); 206 return r; 207 } 208 209 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); 210 DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n", 211 adev->virt.mm_table.gpu_addr, 212 adev->virt.mm_table.cpu_addr); 213 return 0; 214 } 215 216 /** 217 * amdgpu_virt_free_mm_table() - free mm table memory 218 * @adev: amdgpu device. 219 * Free MM table memory 220 */ 221 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev) 222 { 223 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) 224 return; 225 226 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo, 227 &adev->virt.mm_table.gpu_addr, 228 (void *)&adev->virt.mm_table.cpu_addr); 229 adev->virt.mm_table.gpu_addr = 0; 230 } 231 232 233 unsigned int amd_sriov_msg_checksum(void *obj, 234 unsigned long obj_size, 235 unsigned int key, 236 unsigned int checksum) 237 { 238 unsigned int ret = key; 239 unsigned long i = 0; 240 unsigned char *pos; 241 242 pos = (char *)obj; 243 /* calculate checksum */ 244 for (i = 0; i < obj_size; ++i) 245 ret += *(pos + i); 246 /* minus the checksum itself */ 247 pos = (char *)&checksum; 248 for (i = 0; i < sizeof(checksum); ++i) 249 ret -= *(pos + i); 250 return ret; 251 } 252 253 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev) 254 { 255 struct amdgpu_virt *virt = &adev->virt; 256 struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data; 257 /* GPU will be marked bad on host if bp count more then 10, 258 * so alloc 512 is enough. 259 */ 260 unsigned int align_space = 512; 261 void *bps = NULL; 262 struct amdgpu_bo **bps_bo = NULL; 263 264 *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL); 265 if (!*data) 266 goto data_failure; 267 268 bps = kmalloc_array(align_space, sizeof(*(*data)->bps), GFP_KERNEL); 269 if (!bps) 270 goto bps_failure; 271 272 bps_bo = kmalloc_array(align_space, sizeof(*(*data)->bps_bo), GFP_KERNEL); 273 if (!bps_bo) 274 goto bps_bo_failure; 275 276 (*data)->bps = bps; 277 (*data)->bps_bo = bps_bo; 278 (*data)->count = 0; 279 (*data)->last_reserved = 0; 280 281 virt->ras_init_done = true; 282 283 return 0; 284 285 bps_bo_failure: 286 kfree(bps); 287 bps_failure: 288 kfree(*data); 289 data_failure: 290 return -ENOMEM; 291 } 292 293 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev) 294 { 295 struct amdgpu_virt *virt = &adev->virt; 296 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 297 struct amdgpu_bo *bo; 298 int i; 299 300 if (!data) 301 return; 302 303 for (i = data->last_reserved - 1; i >= 0; i--) { 304 bo = data->bps_bo[i]; 305 if (bo) { 306 amdgpu_bo_free_kernel(&bo, NULL, NULL); 307 data->bps_bo[i] = bo; 308 } 309 data->last_reserved = i; 310 } 311 } 312 313 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev) 314 { 315 struct amdgpu_virt *virt = &adev->virt; 316 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 317 318 virt->ras_init_done = false; 319 320 if (!data) 321 return; 322 323 amdgpu_virt_ras_release_bp(adev); 324 325 kfree(data->bps); 326 kfree(data->bps_bo); 327 kfree(data); 328 virt->virt_eh_data = NULL; 329 } 330 331 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev, 332 struct eeprom_table_record *bps, int pages) 333 { 334 struct amdgpu_virt *virt = &adev->virt; 335 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 336 337 if (!data) 338 return; 339 340 memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); 341 data->count += pages; 342 } 343 344 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev) 345 { 346 struct amdgpu_virt *virt = &adev->virt; 347 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 348 struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; 349 struct ttm_resource_manager *man = &mgr->manager; 350 struct amdgpu_bo *bo = NULL; 351 uint64_t bp; 352 int i; 353 354 if (!data) 355 return; 356 357 for (i = data->last_reserved; i < data->count; i++) { 358 bp = data->bps[i].retired_page; 359 360 /* There are two cases of reserve error should be ignored: 361 * 1) a ras bad page has been allocated (used by someone); 362 * 2) a ras bad page has been reserved (duplicate error injection 363 * for one page); 364 */ 365 if (ttm_resource_manager_used(man)) { 366 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr, 367 bp << AMDGPU_GPU_PAGE_SHIFT, 368 AMDGPU_GPU_PAGE_SIZE); 369 data->bps_bo[i] = NULL; 370 } else { 371 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, 372 AMDGPU_GPU_PAGE_SIZE, 373 &bo, NULL)) 374 DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp); 375 data->bps_bo[i] = bo; 376 } 377 data->last_reserved = i + 1; 378 bo = NULL; 379 } 380 } 381 382 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev, 383 uint64_t retired_page) 384 { 385 struct amdgpu_virt *virt = &adev->virt; 386 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 387 int i; 388 389 if (!data) 390 return true; 391 392 for (i = 0; i < data->count; i++) 393 if (retired_page == data->bps[i].retired_page) 394 return true; 395 396 return false; 397 } 398 399 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev, 400 uint64_t bp_block_offset, uint32_t bp_block_size) 401 { 402 struct eeprom_table_record bp; 403 uint64_t retired_page; 404 uint32_t bp_idx, bp_cnt; 405 void *vram_usage_va = NULL; 406 407 if (adev->mman.fw_vram_usage_va) 408 vram_usage_va = adev->mman.fw_vram_usage_va; 409 else 410 vram_usage_va = adev->mman.drv_vram_usage_va; 411 412 memset(&bp, 0, sizeof(bp)); 413 414 if (bp_block_size) { 415 bp_cnt = bp_block_size / sizeof(uint64_t); 416 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) { 417 retired_page = *(uint64_t *)(vram_usage_va + 418 bp_block_offset + bp_idx * sizeof(uint64_t)); 419 bp.retired_page = retired_page; 420 421 if (amdgpu_virt_ras_check_bad_page(adev, retired_page)) 422 continue; 423 424 amdgpu_virt_ras_add_bps(adev, &bp, 1); 425 426 amdgpu_virt_ras_reserve_bps(adev); 427 } 428 } 429 } 430 431 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) 432 { 433 struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf; 434 uint32_t checksum; 435 uint32_t checkval; 436 437 uint32_t i; 438 uint32_t tmp; 439 440 if (adev->virt.fw_reserve.p_pf2vf == NULL) 441 return -EINVAL; 442 443 if (pf2vf_info->size > 1024) { 444 dev_err(adev->dev, "invalid pf2vf message size: 0x%x\n", pf2vf_info->size); 445 return -EINVAL; 446 } 447 448 switch (pf2vf_info->version) { 449 case 1: 450 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum; 451 checkval = amd_sriov_msg_checksum( 452 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 453 adev->virt.fw_reserve.checksum_key, checksum); 454 if (checksum != checkval) { 455 dev_err(adev->dev, 456 "invalid pf2vf message: header checksum=0x%x calculated checksum=0x%x\n", 457 checksum, checkval); 458 return -EINVAL; 459 } 460 461 adev->virt.gim_feature = 462 ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags; 463 break; 464 case 2: 465 /* TODO: missing key, need to add it later */ 466 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum; 467 checkval = amd_sriov_msg_checksum( 468 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 469 0, checksum); 470 if (checksum != checkval) { 471 dev_err(adev->dev, 472 "invalid pf2vf message: header checksum=0x%x calculated checksum=0x%x\n", 473 checksum, checkval); 474 return -EINVAL; 475 } 476 477 adev->virt.vf2pf_update_interval_ms = 478 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms; 479 adev->virt.gim_feature = 480 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all; 481 adev->virt.reg_access = 482 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all; 483 484 adev->virt.decode_max_dimension_pixels = 0; 485 adev->virt.decode_max_frame_pixels = 0; 486 adev->virt.encode_max_dimension_pixels = 0; 487 adev->virt.encode_max_frame_pixels = 0; 488 adev->virt.is_mm_bw_enabled = false; 489 for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) { 490 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels; 491 adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels); 492 493 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels; 494 adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels); 495 496 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels; 497 adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels); 498 499 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels; 500 adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels); 501 } 502 if ((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0)) 503 adev->virt.is_mm_bw_enabled = true; 504 505 adev->unique_id = 506 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid; 507 break; 508 default: 509 dev_err(adev->dev, "invalid pf2vf version: 0x%x\n", pf2vf_info->version); 510 return -EINVAL; 511 } 512 513 /* correct too large or too little interval value */ 514 if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000) 515 adev->virt.vf2pf_update_interval_ms = 2000; 516 517 return 0; 518 } 519 520 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev) 521 { 522 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 523 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 524 525 if (adev->virt.fw_reserve.p_vf2pf == NULL) 526 return; 527 528 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version); 529 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version); 530 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version); 531 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); 532 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); 533 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); 534 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); 535 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); 536 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); 537 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); 538 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); 539 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); 540 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version); 541 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD, 542 adev->psp.asd_context.bin_desc.fw_version); 543 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS, 544 adev->psp.ras_context.context.bin_desc.fw_version); 545 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI, 546 adev->psp.xgmi_context.context.bin_desc.fw_version); 547 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version); 548 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version); 549 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version); 550 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version); 551 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version); 552 } 553 554 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) 555 { 556 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 557 558 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 559 560 if (adev->virt.fw_reserve.p_vf2pf == NULL) 561 return -EINVAL; 562 563 memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info)); 564 565 vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info); 566 vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER; 567 568 #ifdef MODULE 569 if (THIS_MODULE->version != NULL) 570 strcpy(vf2pf_info->driver_version, THIS_MODULE->version); 571 else 572 #endif 573 strcpy(vf2pf_info->driver_version, "N/A"); 574 575 vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all 576 vf2pf_info->driver_cert = 0; 577 vf2pf_info->os_info.all = 0; 578 579 vf2pf_info->fb_usage = 580 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20; 581 vf2pf_info->fb_vis_usage = 582 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20; 583 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20; 584 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20; 585 586 amdgpu_virt_populate_vf2pf_ucode_info(adev); 587 588 /* TODO: read dynamic info */ 589 vf2pf_info->gfx_usage = 0; 590 vf2pf_info->compute_usage = 0; 591 vf2pf_info->encode_usage = 0; 592 vf2pf_info->decode_usage = 0; 593 594 vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr; 595 vf2pf_info->mes_info_addr = (uint64_t)adev->mes.resource_1_gpu_addr; 596 597 if (adev->mes.resource_1) { 598 vf2pf_info->mes_info_size = adev->mes.resource_1->tbo.base.size; 599 } 600 vf2pf_info->checksum = 601 amd_sriov_msg_checksum( 602 vf2pf_info, sizeof(*vf2pf_info), 0, 0); 603 604 return 0; 605 } 606 607 static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work) 608 { 609 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work); 610 int ret; 611 612 ret = amdgpu_virt_read_pf2vf_data(adev); 613 if (ret) { 614 adev->virt.vf2pf_update_retry_cnt++; 615 if ((adev->virt.vf2pf_update_retry_cnt >= AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT) && 616 amdgpu_sriov_runtime(adev)) { 617 amdgpu_ras_set_fed(adev, true); 618 if (amdgpu_reset_domain_schedule(adev->reset_domain, 619 &adev->kfd.reset_work)) 620 return; 621 else 622 dev_err(adev->dev, "Failed to queue work! at %s", __func__); 623 } 624 625 goto out; 626 } 627 628 adev->virt.vf2pf_update_retry_cnt = 0; 629 amdgpu_virt_write_vf2pf_data(adev); 630 631 out: 632 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); 633 } 634 635 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev) 636 { 637 if (adev->virt.vf2pf_update_interval_ms != 0) { 638 DRM_INFO("clean up the vf2pf work item\n"); 639 cancel_delayed_work_sync(&adev->virt.vf2pf_work); 640 adev->virt.vf2pf_update_interval_ms = 0; 641 } 642 } 643 644 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) 645 { 646 adev->virt.fw_reserve.p_pf2vf = NULL; 647 adev->virt.fw_reserve.p_vf2pf = NULL; 648 adev->virt.vf2pf_update_interval_ms = 0; 649 adev->virt.vf2pf_update_retry_cnt = 0; 650 651 if (adev->mman.fw_vram_usage_va && adev->mman.drv_vram_usage_va) { 652 DRM_WARN("Currently fw_vram and drv_vram should not have values at the same time!"); 653 } else if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { 654 /* go through this logic in ip_init and reset to init workqueue*/ 655 amdgpu_virt_exchange_data(adev); 656 657 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item); 658 schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms)); 659 } else if (adev->bios != NULL) { 660 /* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/ 661 adev->virt.fw_reserve.p_pf2vf = 662 (struct amd_sriov_msg_pf2vf_info_header *) 663 (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 664 665 amdgpu_virt_read_pf2vf_data(adev); 666 } 667 } 668 669 670 void amdgpu_virt_exchange_data(struct amdgpu_device *adev) 671 { 672 uint64_t bp_block_offset = 0; 673 uint32_t bp_block_size = 0; 674 struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL; 675 676 if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { 677 if (adev->mman.fw_vram_usage_va) { 678 adev->virt.fw_reserve.p_pf2vf = 679 (struct amd_sriov_msg_pf2vf_info_header *) 680 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 681 adev->virt.fw_reserve.p_vf2pf = 682 (struct amd_sriov_msg_vf2pf_info_header *) 683 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 684 } else if (adev->mman.drv_vram_usage_va) { 685 adev->virt.fw_reserve.p_pf2vf = 686 (struct amd_sriov_msg_pf2vf_info_header *) 687 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 688 adev->virt.fw_reserve.p_vf2pf = 689 (struct amd_sriov_msg_vf2pf_info_header *) 690 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 691 } 692 693 amdgpu_virt_read_pf2vf_data(adev); 694 amdgpu_virt_write_vf2pf_data(adev); 695 696 /* bad page handling for version 2 */ 697 if (adev->virt.fw_reserve.p_pf2vf->version == 2) { 698 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf; 699 700 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) | 701 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000); 702 bp_block_size = pf2vf_v2->bp_block_size; 703 704 if (bp_block_size && !adev->virt.ras_init_done) 705 amdgpu_virt_init_ras_err_handler_data(adev); 706 707 if (adev->virt.ras_init_done) 708 amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size); 709 } 710 } 711 } 712 713 void amdgpu_detect_virtualization(struct amdgpu_device *adev) 714 { 715 uint32_t reg; 716 717 switch (adev->asic_type) { 718 case CHIP_TONGA: 719 case CHIP_FIJI: 720 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); 721 break; 722 case CHIP_VEGA10: 723 case CHIP_VEGA20: 724 case CHIP_NAVI10: 725 case CHIP_NAVI12: 726 case CHIP_SIENNA_CICHLID: 727 case CHIP_ARCTURUS: 728 case CHIP_ALDEBARAN: 729 case CHIP_IP_DISCOVERY: 730 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER); 731 break; 732 default: /* other chip doesn't support SRIOV */ 733 reg = 0; 734 break; 735 } 736 737 if (reg & 1) 738 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 739 740 if (reg & 0x80000000) 741 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 742 743 if (!reg) { 744 /* passthrough mode exclus sriov mod */ 745 if (is_virtual_machine() && !xen_initial_domain()) 746 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 747 } 748 749 /* we have the ability to check now */ 750 if (amdgpu_sriov_vf(adev)) { 751 switch (adev->asic_type) { 752 case CHIP_TONGA: 753 case CHIP_FIJI: 754 vi_set_virt_ops(adev); 755 break; 756 case CHIP_VEGA10: 757 soc15_set_virt_ops(adev); 758 #ifdef CONFIG_X86 759 /* not send GPU_INIT_DATA with MS_HYPERV*/ 760 if (!hypervisor_is_type(X86_HYPER_MS_HYPERV)) 761 #endif 762 /* send a dummy GPU_INIT_DATA request to host on vega10 */ 763 amdgpu_virt_request_init_data(adev); 764 break; 765 case CHIP_VEGA20: 766 case CHIP_ARCTURUS: 767 case CHIP_ALDEBARAN: 768 soc15_set_virt_ops(adev); 769 break; 770 case CHIP_NAVI10: 771 case CHIP_NAVI12: 772 case CHIP_SIENNA_CICHLID: 773 case CHIP_IP_DISCOVERY: 774 nv_set_virt_ops(adev); 775 /* try send GPU_INIT_DATA request to host */ 776 amdgpu_virt_request_init_data(adev); 777 break; 778 default: /* other chip doesn't support SRIOV */ 779 DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type); 780 break; 781 } 782 } 783 } 784 785 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev) 786 { 787 return amdgpu_sriov_is_debug(adev) ? true : false; 788 } 789 790 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev) 791 { 792 return amdgpu_sriov_is_normal(adev) ? true : false; 793 } 794 795 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev) 796 { 797 if (!amdgpu_sriov_vf(adev) || 798 amdgpu_virt_access_debugfs_is_kiq(adev)) 799 return 0; 800 801 if (amdgpu_virt_access_debugfs_is_mmio(adev)) 802 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 803 else 804 return -EPERM; 805 806 return 0; 807 } 808 809 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev) 810 { 811 if (amdgpu_sriov_vf(adev)) 812 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 813 } 814 815 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev) 816 { 817 enum amdgpu_sriov_vf_mode mode; 818 819 if (amdgpu_sriov_vf(adev)) { 820 if (amdgpu_sriov_is_pp_one_vf(adev)) 821 mode = SRIOV_VF_MODE_ONE_VF; 822 else 823 mode = SRIOV_VF_MODE_MULTI_VF; 824 } else { 825 mode = SRIOV_VF_MODE_BARE_METAL; 826 } 827 828 return mode; 829 } 830 831 void amdgpu_virt_post_reset(struct amdgpu_device *adev) 832 { 833 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3)) { 834 /* force set to GFXOFF state after reset, 835 * to avoid some invalid operation before GC enable 836 */ 837 adev->gfx.is_poweron = false; 838 } 839 840 adev->mes.ring.sched.ready = false; 841 } 842 843 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id) 844 { 845 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 846 case IP_VERSION(13, 0, 0): 847 /* no vf autoload, white list */ 848 if (ucode_id == AMDGPU_UCODE_ID_VCN1 || 849 ucode_id == AMDGPU_UCODE_ID_VCN) 850 return false; 851 else 852 return true; 853 case IP_VERSION(11, 0, 9): 854 case IP_VERSION(11, 0, 7): 855 /* black list for CHIP_NAVI12 and CHIP_SIENNA_CICHLID */ 856 if (ucode_id == AMDGPU_UCODE_ID_RLC_G 857 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 858 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 859 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 860 || ucode_id == AMDGPU_UCODE_ID_SMC) 861 return true; 862 else 863 return false; 864 case IP_VERSION(13, 0, 10): 865 /* white list */ 866 if (ucode_id == AMDGPU_UCODE_ID_CAP 867 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP 868 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME 869 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC 870 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK 871 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK 872 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK 873 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK 874 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK 875 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK 876 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK 877 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK 878 || ucode_id == AMDGPU_UCODE_ID_CP_MES 879 || ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA 880 || ucode_id == AMDGPU_UCODE_ID_CP_MES1 881 || ucode_id == AMDGPU_UCODE_ID_CP_MES1_DATA 882 || ucode_id == AMDGPU_UCODE_ID_VCN1 883 || ucode_id == AMDGPU_UCODE_ID_VCN) 884 return false; 885 else 886 return true; 887 default: 888 /* lagacy black list */ 889 if (ucode_id == AMDGPU_UCODE_ID_SDMA0 890 || ucode_id == AMDGPU_UCODE_ID_SDMA1 891 || ucode_id == AMDGPU_UCODE_ID_SDMA2 892 || ucode_id == AMDGPU_UCODE_ID_SDMA3 893 || ucode_id == AMDGPU_UCODE_ID_SDMA4 894 || ucode_id == AMDGPU_UCODE_ID_SDMA5 895 || ucode_id == AMDGPU_UCODE_ID_SDMA6 896 || ucode_id == AMDGPU_UCODE_ID_SDMA7 897 || ucode_id == AMDGPU_UCODE_ID_RLC_G 898 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 899 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 900 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 901 || ucode_id == AMDGPU_UCODE_ID_SMC) 902 return true; 903 else 904 return false; 905 } 906 } 907 908 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 909 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 910 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size) 911 { 912 uint32_t i; 913 914 if (!adev->virt.is_mm_bw_enabled) 915 return; 916 917 if (encode) { 918 for (i = 0; i < encode_array_size; i++) { 919 encode[i].max_width = adev->virt.encode_max_dimension_pixels; 920 encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels; 921 if (encode[i].max_width > 0) 922 encode[i].max_height = encode[i].max_pixels_per_frame / encode[i].max_width; 923 else 924 encode[i].max_height = 0; 925 } 926 } 927 928 if (decode) { 929 for (i = 0; i < decode_array_size; i++) { 930 decode[i].max_width = adev->virt.decode_max_dimension_pixels; 931 decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels; 932 if (decode[i].max_width > 0) 933 decode[i].max_height = decode[i].max_pixels_per_frame / decode[i].max_width; 934 else 935 decode[i].max_height = 0; 936 } 937 } 938 } 939 940 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 941 u32 acc_flags, u32 hwip, 942 bool write, u32 *rlcg_flag) 943 { 944 bool ret = false; 945 946 switch (hwip) { 947 case GC_HWIP: 948 if (amdgpu_sriov_reg_indirect_gc(adev)) { 949 *rlcg_flag = 950 write ? AMDGPU_RLCG_GC_WRITE : AMDGPU_RLCG_GC_READ; 951 ret = true; 952 /* only in new version, AMDGPU_REGS_NO_KIQ and 953 * AMDGPU_REGS_RLC are enabled simultaneously */ 954 } else if ((acc_flags & AMDGPU_REGS_RLC) && 955 !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) { 956 *rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY; 957 ret = true; 958 } 959 break; 960 case MMHUB_HWIP: 961 if (amdgpu_sriov_reg_indirect_mmhub(adev) && 962 (acc_flags & AMDGPU_REGS_RLC) && write) { 963 *rlcg_flag = AMDGPU_RLCG_MMHUB_WRITE; 964 ret = true; 965 } 966 break; 967 default: 968 break; 969 } 970 return ret; 971 } 972 973 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id) 974 { 975 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 976 uint32_t timeout = 50000; 977 uint32_t i, tmp; 978 uint32_t ret = 0; 979 void *scratch_reg0; 980 void *scratch_reg1; 981 void *scratch_reg2; 982 void *scratch_reg3; 983 void *spare_int; 984 985 if (!adev->gfx.rlc.rlcg_reg_access_supported) { 986 dev_err(adev->dev, 987 "indirect registers access through rlcg is not available\n"); 988 return 0; 989 } 990 991 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { 992 dev_err(adev->dev, "invalid xcc\n"); 993 return 0; 994 } 995 996 if (amdgpu_device_skip_hw_access(adev)) 997 return 0; 998 999 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; 1000 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0; 1001 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1; 1002 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; 1003 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3; 1004 1005 mutex_lock(&adev->virt.rlcg_reg_lock); 1006 1007 if (reg_access_ctrl->spare_int) 1008 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int; 1009 1010 if (offset == reg_access_ctrl->grbm_cntl) { 1011 /* if the target reg offset is grbm_cntl, write to scratch_reg2 */ 1012 writel(v, scratch_reg2); 1013 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY) 1014 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 1015 } else if (offset == reg_access_ctrl->grbm_idx) { 1016 /* if the target reg offset is grbm_idx, write to scratch_reg3 */ 1017 writel(v, scratch_reg3); 1018 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY) 1019 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 1020 } else { 1021 /* 1022 * SCRATCH_REG0 = read/write value 1023 * SCRATCH_REG1[30:28] = command 1024 * SCRATCH_REG1[19:0] = address in dword 1025 * SCRATCH_REG1[27:24] = Error reporting 1026 */ 1027 writel(v, scratch_reg0); 1028 writel((offset | flag), scratch_reg1); 1029 if (reg_access_ctrl->spare_int) 1030 writel(1, spare_int); 1031 1032 for (i = 0; i < timeout; i++) { 1033 tmp = readl(scratch_reg1); 1034 if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK)) 1035 break; 1036 udelay(10); 1037 } 1038 1039 tmp = readl(scratch_reg1); 1040 if (i >= timeout || (tmp & AMDGPU_RLCG_SCRATCH1_ERROR_MASK) != 0) { 1041 if (amdgpu_sriov_rlcg_error_report_enabled(adev)) { 1042 if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) { 1043 dev_err(adev->dev, 1044 "vfgate is disabled, rlcg failed to program reg: 0x%05x\n", offset); 1045 } else if (tmp & AMDGPU_RLCG_WRONG_OPERATION_TYPE) { 1046 dev_err(adev->dev, 1047 "wrong operation type, rlcg failed to program reg: 0x%05x\n", offset); 1048 } else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) { 1049 dev_err(adev->dev, 1050 "register is not in range, rlcg failed to program reg: 0x%05x\n", offset); 1051 } else { 1052 dev_err(adev->dev, 1053 "unknown error type, rlcg failed to program reg: 0x%05x\n", offset); 1054 } 1055 } else { 1056 dev_err(adev->dev, 1057 "timeout: rlcg faled to program reg: 0x%05x\n", offset); 1058 } 1059 } 1060 } 1061 1062 ret = readl(scratch_reg0); 1063 1064 mutex_unlock(&adev->virt.rlcg_reg_lock); 1065 1066 return ret; 1067 } 1068 1069 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 1070 u32 offset, u32 value, 1071 u32 acc_flags, u32 hwip, u32 xcc_id) 1072 { 1073 u32 rlcg_flag; 1074 1075 if (amdgpu_device_skip_hw_access(adev)) 1076 return; 1077 1078 if (!amdgpu_sriov_runtime(adev) && 1079 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) { 1080 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag, xcc_id); 1081 return; 1082 } 1083 1084 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1085 WREG32_NO_KIQ(offset, value); 1086 else 1087 WREG32(offset, value); 1088 } 1089 1090 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 1091 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id) 1092 { 1093 u32 rlcg_flag; 1094 1095 if (amdgpu_device_skip_hw_access(adev)) 1096 return 0; 1097 1098 if (!amdgpu_sriov_runtime(adev) && 1099 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag)) 1100 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag, xcc_id); 1101 1102 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1103 return RREG32_NO_KIQ(offset); 1104 else 1105 return RREG32(offset); 1106 } 1107 1108 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev) 1109 { 1110 bool xnack_mode = true; 1111 1112 if (amdgpu_sriov_vf(adev) && 1113 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 1114 xnack_mode = false; 1115 1116 return xnack_mode; 1117 } 1118