1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/module.h> 25 26 #ifdef CONFIG_X86 27 #include <asm/hypervisor.h> 28 #endif 29 30 #include <drm/drm_drv.h> 31 #include <xen/xen.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_ras.h" 35 #include "amdgpu_reset.h" 36 #include "amdgpu_dpm.h" 37 #include "vi.h" 38 #include "soc15.h" 39 #include "nv.h" 40 41 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \ 42 do { \ 43 vf2pf_info->ucode_info[ucode].id = ucode; \ 44 vf2pf_info->ucode_info[ucode].version = ver; \ 45 } while (0) 46 47 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) 48 { 49 /* By now all MMIO pages except mailbox are blocked */ 50 /* if blocking is enabled in hypervisor. Choose the */ 51 /* SCRATCH_REG0 to test. */ 52 return RREG32_NO_KIQ(0xc040) == 0xffffffff; 53 } 54 55 void amdgpu_virt_init_setting(struct amdgpu_device *adev) 56 { 57 struct drm_device *ddev = adev_to_drm(adev); 58 59 /* enable virtual display */ 60 if (adev->asic_type != CHIP_ALDEBARAN && 61 adev->asic_type != CHIP_ARCTURUS && 62 ((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) { 63 if (adev->mode_info.num_crtc == 0) 64 adev->mode_info.num_crtc = 1; 65 adev->enable_virtual_display = true; 66 } 67 ddev->driver_features &= ~DRIVER_ATOMIC; 68 adev->cg_flags = 0; 69 adev->pg_flags = 0; 70 71 /* Reduce kcq number to 2 to reduce latency */ 72 if (amdgpu_num_kcq == -1) 73 amdgpu_num_kcq = 2; 74 } 75 76 /** 77 * amdgpu_virt_request_full_gpu() - request full gpu access 78 * @adev: amdgpu device. 79 * @init: is driver init time. 80 * When start to init/fini driver, first need to request full gpu access. 81 * Return: Zero if request success, otherwise will return error. 82 */ 83 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init) 84 { 85 struct amdgpu_virt *virt = &adev->virt; 86 int r; 87 88 if (virt->ops && virt->ops->req_full_gpu) { 89 r = virt->ops->req_full_gpu(adev, init); 90 if (r) { 91 adev->no_hw_access = true; 92 return r; 93 } 94 95 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 96 } 97 98 return 0; 99 } 100 101 /** 102 * amdgpu_virt_release_full_gpu() - release full gpu access 103 * @adev: amdgpu device. 104 * @init: is driver init time. 105 * When finishing driver init/fini, need to release full gpu access. 106 * Return: Zero if release success, otherwise will returen error. 107 */ 108 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init) 109 { 110 struct amdgpu_virt *virt = &adev->virt; 111 int r; 112 113 if (virt->ops && virt->ops->rel_full_gpu) { 114 r = virt->ops->rel_full_gpu(adev, init); 115 if (r) 116 return r; 117 118 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 119 } 120 return 0; 121 } 122 123 /** 124 * amdgpu_virt_reset_gpu() - reset gpu 125 * @adev: amdgpu device. 126 * Send reset command to GPU hypervisor to reset GPU that VM is using 127 * Return: Zero if reset success, otherwise will return error. 128 */ 129 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev) 130 { 131 struct amdgpu_virt *virt = &adev->virt; 132 int r; 133 134 if (virt->ops && virt->ops->reset_gpu) { 135 r = virt->ops->reset_gpu(adev); 136 if (r) 137 return r; 138 139 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 140 } 141 142 return 0; 143 } 144 145 void amdgpu_virt_request_init_data(struct amdgpu_device *adev) 146 { 147 struct amdgpu_virt *virt = &adev->virt; 148 149 if (virt->ops && virt->ops->req_init_data) 150 virt->ops->req_init_data(adev); 151 152 if (adev->virt.req_init_data_ver > 0) 153 DRM_INFO("host supports REQ_INIT_DATA handshake\n"); 154 else 155 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n"); 156 } 157 158 /** 159 * amdgpu_virt_ready_to_reset() - send ready to reset to host 160 * @adev: amdgpu device. 161 * Send ready to reset message to GPU hypervisor to signal we have stopped GPU 162 * activity and is ready for host FLR 163 */ 164 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev) 165 { 166 struct amdgpu_virt *virt = &adev->virt; 167 168 if (virt->ops && virt->ops->reset_gpu) 169 virt->ops->ready_to_reset(adev); 170 } 171 172 /** 173 * amdgpu_virt_wait_reset() - wait for reset gpu completed 174 * @adev: amdgpu device. 175 * Wait for GPU reset completed. 176 * Return: Zero if reset success, otherwise will return error. 177 */ 178 int amdgpu_virt_wait_reset(struct amdgpu_device *adev) 179 { 180 struct amdgpu_virt *virt = &adev->virt; 181 182 if (!virt->ops || !virt->ops->wait_reset) 183 return -EINVAL; 184 185 return virt->ops->wait_reset(adev); 186 } 187 188 /** 189 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table 190 * @adev: amdgpu device. 191 * MM table is used by UVD and VCE for its initialization 192 * Return: Zero if allocate success. 193 */ 194 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev) 195 { 196 int r; 197 198 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) 199 return 0; 200 201 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 202 AMDGPU_GEM_DOMAIN_VRAM | 203 AMDGPU_GEM_DOMAIN_GTT, 204 &adev->virt.mm_table.bo, 205 &adev->virt.mm_table.gpu_addr, 206 (void *)&adev->virt.mm_table.cpu_addr); 207 if (r) { 208 DRM_ERROR("failed to alloc mm table and error = %d.\n", r); 209 return r; 210 } 211 212 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); 213 DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n", 214 adev->virt.mm_table.gpu_addr, 215 adev->virt.mm_table.cpu_addr); 216 return 0; 217 } 218 219 /** 220 * amdgpu_virt_free_mm_table() - free mm table memory 221 * @adev: amdgpu device. 222 * Free MM table memory 223 */ 224 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev) 225 { 226 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) 227 return; 228 229 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo, 230 &adev->virt.mm_table.gpu_addr, 231 (void *)&adev->virt.mm_table.cpu_addr); 232 adev->virt.mm_table.gpu_addr = 0; 233 } 234 235 /** 236 * amdgpu_virt_rcvd_ras_interrupt() - receive ras interrupt 237 * @adev: amdgpu device. 238 * Check whether host sent RAS error message 239 * Return: true if found, otherwise false 240 */ 241 bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev) 242 { 243 struct amdgpu_virt *virt = &adev->virt; 244 245 if (!virt->ops || !virt->ops->rcvd_ras_intr) 246 return false; 247 248 return virt->ops->rcvd_ras_intr(adev); 249 } 250 251 252 unsigned int amd_sriov_msg_checksum(void *obj, 253 unsigned long obj_size, 254 unsigned int key, 255 unsigned int checksum) 256 { 257 unsigned int ret = key; 258 unsigned long i = 0; 259 unsigned char *pos; 260 261 pos = (char *)obj; 262 /* calculate checksum */ 263 for (i = 0; i < obj_size; ++i) 264 ret += *(pos + i); 265 /* minus the checksum itself */ 266 pos = (char *)&checksum; 267 for (i = 0; i < sizeof(checksum); ++i) 268 ret -= *(pos + i); 269 return ret; 270 } 271 272 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev) 273 { 274 struct amdgpu_virt *virt = &adev->virt; 275 struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data; 276 /* GPU will be marked bad on host if bp count more then 10, 277 * so alloc 512 is enough. 278 */ 279 unsigned int align_space = 512; 280 void *bps = NULL; 281 struct amdgpu_bo **bps_bo = NULL; 282 283 *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL); 284 if (!*data) 285 goto data_failure; 286 287 bps = kmalloc_array(align_space, sizeof(*(*data)->bps), GFP_KERNEL); 288 if (!bps) 289 goto bps_failure; 290 291 bps_bo = kmalloc_array(align_space, sizeof(*(*data)->bps_bo), GFP_KERNEL); 292 if (!bps_bo) 293 goto bps_bo_failure; 294 295 (*data)->bps = bps; 296 (*data)->bps_bo = bps_bo; 297 (*data)->count = 0; 298 (*data)->last_reserved = 0; 299 300 virt->ras_init_done = true; 301 302 return 0; 303 304 bps_bo_failure: 305 kfree(bps); 306 bps_failure: 307 kfree(*data); 308 data_failure: 309 return -ENOMEM; 310 } 311 312 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev) 313 { 314 struct amdgpu_virt *virt = &adev->virt; 315 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 316 struct amdgpu_bo *bo; 317 int i; 318 319 if (!data) 320 return; 321 322 for (i = data->last_reserved - 1; i >= 0; i--) { 323 bo = data->bps_bo[i]; 324 if (bo) { 325 amdgpu_bo_free_kernel(&bo, NULL, NULL); 326 data->bps_bo[i] = bo; 327 } 328 data->last_reserved = i; 329 } 330 } 331 332 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev) 333 { 334 struct amdgpu_virt *virt = &adev->virt; 335 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 336 337 virt->ras_init_done = false; 338 339 if (!data) 340 return; 341 342 amdgpu_virt_ras_release_bp(adev); 343 344 kfree(data->bps); 345 kfree(data->bps_bo); 346 kfree(data); 347 virt->virt_eh_data = NULL; 348 } 349 350 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev, 351 struct eeprom_table_record *bps, int pages) 352 { 353 struct amdgpu_virt *virt = &adev->virt; 354 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 355 356 if (!data) 357 return; 358 359 memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); 360 data->count += pages; 361 } 362 363 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev) 364 { 365 struct amdgpu_virt *virt = &adev->virt; 366 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 367 struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; 368 struct ttm_resource_manager *man = &mgr->manager; 369 struct amdgpu_bo *bo = NULL; 370 uint64_t bp; 371 int i; 372 373 if (!data) 374 return; 375 376 for (i = data->last_reserved; i < data->count; i++) { 377 bp = data->bps[i].retired_page; 378 379 /* There are two cases of reserve error should be ignored: 380 * 1) a ras bad page has been allocated (used by someone); 381 * 2) a ras bad page has been reserved (duplicate error injection 382 * for one page); 383 */ 384 if (ttm_resource_manager_used(man)) { 385 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr, 386 bp << AMDGPU_GPU_PAGE_SHIFT, 387 AMDGPU_GPU_PAGE_SIZE); 388 data->bps_bo[i] = NULL; 389 } else { 390 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, 391 AMDGPU_GPU_PAGE_SIZE, 392 &bo, NULL)) 393 DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp); 394 data->bps_bo[i] = bo; 395 } 396 data->last_reserved = i + 1; 397 bo = NULL; 398 } 399 } 400 401 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev, 402 uint64_t retired_page) 403 { 404 struct amdgpu_virt *virt = &adev->virt; 405 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 406 int i; 407 408 if (!data) 409 return true; 410 411 for (i = 0; i < data->count; i++) 412 if (retired_page == data->bps[i].retired_page) 413 return true; 414 415 return false; 416 } 417 418 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev, 419 uint64_t bp_block_offset, uint32_t bp_block_size) 420 { 421 struct eeprom_table_record bp; 422 uint64_t retired_page; 423 uint32_t bp_idx, bp_cnt; 424 void *vram_usage_va = NULL; 425 426 if (adev->mman.fw_vram_usage_va) 427 vram_usage_va = adev->mman.fw_vram_usage_va; 428 else 429 vram_usage_va = adev->mman.drv_vram_usage_va; 430 431 memset(&bp, 0, sizeof(bp)); 432 433 if (bp_block_size) { 434 bp_cnt = bp_block_size / sizeof(uint64_t); 435 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) { 436 retired_page = *(uint64_t *)(vram_usage_va + 437 bp_block_offset + bp_idx * sizeof(uint64_t)); 438 bp.retired_page = retired_page; 439 440 if (amdgpu_virt_ras_check_bad_page(adev, retired_page)) 441 continue; 442 443 amdgpu_virt_ras_add_bps(adev, &bp, 1); 444 445 amdgpu_virt_ras_reserve_bps(adev); 446 } 447 } 448 } 449 450 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) 451 { 452 struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf; 453 uint32_t checksum; 454 uint32_t checkval; 455 456 uint32_t i; 457 uint32_t tmp; 458 459 if (adev->virt.fw_reserve.p_pf2vf == NULL) 460 return -EINVAL; 461 462 if (pf2vf_info->size > 1024) { 463 dev_err(adev->dev, "invalid pf2vf message size: 0x%x\n", pf2vf_info->size); 464 return -EINVAL; 465 } 466 467 switch (pf2vf_info->version) { 468 case 1: 469 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum; 470 checkval = amd_sriov_msg_checksum( 471 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 472 adev->virt.fw_reserve.checksum_key, checksum); 473 if (checksum != checkval) { 474 dev_err(adev->dev, 475 "invalid pf2vf message: header checksum=0x%x calculated checksum=0x%x\n", 476 checksum, checkval); 477 return -EINVAL; 478 } 479 480 adev->virt.gim_feature = 481 ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags; 482 break; 483 case 2: 484 /* TODO: missing key, need to add it later */ 485 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum; 486 checkval = amd_sriov_msg_checksum( 487 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 488 0, checksum); 489 if (checksum != checkval) { 490 dev_err(adev->dev, 491 "invalid pf2vf message: header checksum=0x%x calculated checksum=0x%x\n", 492 checksum, checkval); 493 return -EINVAL; 494 } 495 496 adev->virt.vf2pf_update_interval_ms = 497 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms; 498 adev->virt.gim_feature = 499 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all; 500 adev->virt.reg_access = 501 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all; 502 503 adev->virt.decode_max_dimension_pixels = 0; 504 adev->virt.decode_max_frame_pixels = 0; 505 adev->virt.encode_max_dimension_pixels = 0; 506 adev->virt.encode_max_frame_pixels = 0; 507 adev->virt.is_mm_bw_enabled = false; 508 for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) { 509 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels; 510 adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels); 511 512 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels; 513 adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels); 514 515 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels; 516 adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels); 517 518 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels; 519 adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels); 520 } 521 if ((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0)) 522 adev->virt.is_mm_bw_enabled = true; 523 524 adev->unique_id = 525 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid; 526 adev->virt.ras_en_caps.all = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->ras_en_caps.all; 527 adev->virt.ras_telemetry_en_caps.all = 528 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->ras_telemetry_en_caps.all; 529 break; 530 default: 531 dev_err(adev->dev, "invalid pf2vf version: 0x%x\n", pf2vf_info->version); 532 return -EINVAL; 533 } 534 535 /* correct too large or too little interval value */ 536 if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000) 537 adev->virt.vf2pf_update_interval_ms = 2000; 538 539 return 0; 540 } 541 542 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev) 543 { 544 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 545 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 546 547 if (adev->virt.fw_reserve.p_vf2pf == NULL) 548 return; 549 550 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version); 551 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version); 552 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version); 553 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); 554 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); 555 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); 556 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); 557 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); 558 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); 559 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); 560 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); 561 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); 562 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version); 563 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD, 564 adev->psp.asd_context.bin_desc.fw_version); 565 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS, 566 adev->psp.ras_context.context.bin_desc.fw_version); 567 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI, 568 adev->psp.xgmi_context.context.bin_desc.fw_version); 569 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version); 570 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version); 571 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version); 572 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version); 573 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version); 574 } 575 576 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) 577 { 578 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 579 580 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 581 582 if (adev->virt.fw_reserve.p_vf2pf == NULL) 583 return -EINVAL; 584 585 memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info)); 586 587 vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info); 588 vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER; 589 590 #ifdef MODULE 591 if (THIS_MODULE->version != NULL) 592 strcpy(vf2pf_info->driver_version, THIS_MODULE->version); 593 else 594 #endif 595 strcpy(vf2pf_info->driver_version, "N/A"); 596 597 vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all 598 vf2pf_info->driver_cert = 0; 599 vf2pf_info->os_info.all = 0; 600 601 vf2pf_info->fb_usage = 602 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20; 603 vf2pf_info->fb_vis_usage = 604 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20; 605 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20; 606 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20; 607 608 amdgpu_virt_populate_vf2pf_ucode_info(adev); 609 610 /* TODO: read dynamic info */ 611 vf2pf_info->gfx_usage = 0; 612 vf2pf_info->compute_usage = 0; 613 vf2pf_info->encode_usage = 0; 614 vf2pf_info->decode_usage = 0; 615 616 vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr; 617 vf2pf_info->mes_info_addr = (uint64_t)adev->mes.resource_1_gpu_addr; 618 619 if (adev->mes.resource_1) { 620 vf2pf_info->mes_info_size = adev->mes.resource_1->tbo.base.size; 621 } 622 vf2pf_info->checksum = 623 amd_sriov_msg_checksum( 624 vf2pf_info, sizeof(*vf2pf_info), 0, 0); 625 626 return 0; 627 } 628 629 static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work) 630 { 631 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work); 632 int ret; 633 634 ret = amdgpu_virt_read_pf2vf_data(adev); 635 if (ret) { 636 adev->virt.vf2pf_update_retry_cnt++; 637 638 if ((amdgpu_virt_rcvd_ras_interrupt(adev) || 639 adev->virt.vf2pf_update_retry_cnt >= AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT) && 640 amdgpu_sriov_runtime(adev)) { 641 642 amdgpu_ras_set_fed(adev, true); 643 if (amdgpu_reset_domain_schedule(adev->reset_domain, 644 &adev->kfd.reset_work)) 645 return; 646 else 647 dev_err(adev->dev, "Failed to queue work! at %s", __func__); 648 } 649 650 goto out; 651 } 652 653 adev->virt.vf2pf_update_retry_cnt = 0; 654 amdgpu_virt_write_vf2pf_data(adev); 655 656 out: 657 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); 658 } 659 660 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev) 661 { 662 if (adev->virt.vf2pf_update_interval_ms != 0) { 663 DRM_INFO("clean up the vf2pf work item\n"); 664 cancel_delayed_work_sync(&adev->virt.vf2pf_work); 665 adev->virt.vf2pf_update_interval_ms = 0; 666 } 667 } 668 669 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) 670 { 671 adev->virt.fw_reserve.p_pf2vf = NULL; 672 adev->virt.fw_reserve.p_vf2pf = NULL; 673 adev->virt.vf2pf_update_interval_ms = 0; 674 adev->virt.vf2pf_update_retry_cnt = 0; 675 676 if (adev->mman.fw_vram_usage_va && adev->mman.drv_vram_usage_va) { 677 DRM_WARN("Currently fw_vram and drv_vram should not have values at the same time!"); 678 } else if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { 679 /* go through this logic in ip_init and reset to init workqueue*/ 680 amdgpu_virt_exchange_data(adev); 681 682 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item); 683 schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms)); 684 } else if (adev->bios != NULL) { 685 /* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/ 686 adev->virt.fw_reserve.p_pf2vf = 687 (struct amd_sriov_msg_pf2vf_info_header *) 688 (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 689 690 amdgpu_virt_read_pf2vf_data(adev); 691 } 692 } 693 694 695 void amdgpu_virt_exchange_data(struct amdgpu_device *adev) 696 { 697 uint64_t bp_block_offset = 0; 698 uint32_t bp_block_size = 0; 699 struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL; 700 701 if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { 702 if (adev->mman.fw_vram_usage_va) { 703 adev->virt.fw_reserve.p_pf2vf = 704 (struct amd_sriov_msg_pf2vf_info_header *) 705 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 706 adev->virt.fw_reserve.p_vf2pf = 707 (struct amd_sriov_msg_vf2pf_info_header *) 708 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 709 adev->virt.fw_reserve.ras_telemetry = 710 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB << 10)); 711 } else if (adev->mman.drv_vram_usage_va) { 712 adev->virt.fw_reserve.p_pf2vf = 713 (struct amd_sriov_msg_pf2vf_info_header *) 714 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 715 adev->virt.fw_reserve.p_vf2pf = 716 (struct amd_sriov_msg_vf2pf_info_header *) 717 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 718 adev->virt.fw_reserve.ras_telemetry = 719 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB << 10)); 720 } 721 722 amdgpu_virt_read_pf2vf_data(adev); 723 amdgpu_virt_write_vf2pf_data(adev); 724 725 /* bad page handling for version 2 */ 726 if (adev->virt.fw_reserve.p_pf2vf->version == 2) { 727 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf; 728 729 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) | 730 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000); 731 bp_block_size = pf2vf_v2->bp_block_size; 732 733 if (bp_block_size && !adev->virt.ras_init_done) 734 amdgpu_virt_init_ras_err_handler_data(adev); 735 736 if (adev->virt.ras_init_done) 737 amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size); 738 } 739 } 740 } 741 742 static u32 amdgpu_virt_init_detect_asic(struct amdgpu_device *adev) 743 { 744 uint32_t reg; 745 746 switch (adev->asic_type) { 747 case CHIP_TONGA: 748 case CHIP_FIJI: 749 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); 750 break; 751 case CHIP_VEGA10: 752 case CHIP_VEGA20: 753 case CHIP_NAVI10: 754 case CHIP_NAVI12: 755 case CHIP_SIENNA_CICHLID: 756 case CHIP_ARCTURUS: 757 case CHIP_ALDEBARAN: 758 case CHIP_IP_DISCOVERY: 759 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER); 760 break; 761 default: /* other chip doesn't support SRIOV */ 762 reg = 0; 763 break; 764 } 765 766 if (reg & 1) 767 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 768 769 if (reg & 0x80000000) 770 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 771 772 if (!reg) { 773 /* passthrough mode exclus sriov mod */ 774 if (is_virtual_machine() && !xen_initial_domain()) 775 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 776 } 777 778 return reg; 779 } 780 781 static bool amdgpu_virt_init_req_data(struct amdgpu_device *adev, u32 reg) 782 { 783 bool is_sriov = false; 784 785 /* we have the ability to check now */ 786 if (amdgpu_sriov_vf(adev)) { 787 is_sriov = true; 788 789 switch (adev->asic_type) { 790 case CHIP_TONGA: 791 case CHIP_FIJI: 792 vi_set_virt_ops(adev); 793 break; 794 case CHIP_VEGA10: 795 soc15_set_virt_ops(adev); 796 #ifdef CONFIG_X86 797 /* not send GPU_INIT_DATA with MS_HYPERV*/ 798 if (!hypervisor_is_type(X86_HYPER_MS_HYPERV)) 799 #endif 800 /* send a dummy GPU_INIT_DATA request to host on vega10 */ 801 amdgpu_virt_request_init_data(adev); 802 break; 803 case CHIP_VEGA20: 804 case CHIP_ARCTURUS: 805 case CHIP_ALDEBARAN: 806 soc15_set_virt_ops(adev); 807 break; 808 case CHIP_NAVI10: 809 case CHIP_NAVI12: 810 case CHIP_SIENNA_CICHLID: 811 case CHIP_IP_DISCOVERY: 812 nv_set_virt_ops(adev); 813 /* try send GPU_INIT_DATA request to host */ 814 amdgpu_virt_request_init_data(adev); 815 break; 816 default: /* other chip doesn't support SRIOV */ 817 is_sriov = false; 818 DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type); 819 break; 820 } 821 } 822 823 return is_sriov; 824 } 825 826 static void amdgpu_virt_init_ras(struct amdgpu_device *adev) 827 { 828 ratelimit_state_init(&adev->virt.ras.ras_error_cnt_rs, 5 * HZ, 1); 829 ratelimit_state_init(&adev->virt.ras.ras_cper_dump_rs, 5 * HZ, 1); 830 831 ratelimit_set_flags(&adev->virt.ras.ras_error_cnt_rs, 832 RATELIMIT_MSG_ON_RELEASE); 833 ratelimit_set_flags(&adev->virt.ras.ras_cper_dump_rs, 834 RATELIMIT_MSG_ON_RELEASE); 835 836 mutex_init(&adev->virt.ras.ras_telemetry_mutex); 837 838 adev->virt.ras.cper_rptr = 0; 839 } 840 841 void amdgpu_virt_init(struct amdgpu_device *adev) 842 { 843 bool is_sriov = false; 844 uint32_t reg = amdgpu_virt_init_detect_asic(adev); 845 846 is_sriov = amdgpu_virt_init_req_data(adev, reg); 847 848 if (is_sriov) 849 amdgpu_virt_init_ras(adev); 850 } 851 852 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev) 853 { 854 return amdgpu_sriov_is_debug(adev) ? true : false; 855 } 856 857 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev) 858 { 859 return amdgpu_sriov_is_normal(adev) ? true : false; 860 } 861 862 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev) 863 { 864 if (!amdgpu_sriov_vf(adev) || 865 amdgpu_virt_access_debugfs_is_kiq(adev)) 866 return 0; 867 868 if (amdgpu_virt_access_debugfs_is_mmio(adev)) 869 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 870 else 871 return -EPERM; 872 873 return 0; 874 } 875 876 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev) 877 { 878 if (amdgpu_sriov_vf(adev)) 879 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 880 } 881 882 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev) 883 { 884 enum amdgpu_sriov_vf_mode mode; 885 886 if (amdgpu_sriov_vf(adev)) { 887 if (amdgpu_sriov_is_pp_one_vf(adev)) 888 mode = SRIOV_VF_MODE_ONE_VF; 889 else 890 mode = SRIOV_VF_MODE_MULTI_VF; 891 } else { 892 mode = SRIOV_VF_MODE_BARE_METAL; 893 } 894 895 return mode; 896 } 897 898 void amdgpu_virt_pre_reset(struct amdgpu_device *adev) 899 { 900 /* stop the data exchange thread */ 901 amdgpu_virt_fini_data_exchange(adev); 902 amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_FLR); 903 } 904 905 void amdgpu_virt_post_reset(struct amdgpu_device *adev) 906 { 907 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3)) { 908 /* force set to GFXOFF state after reset, 909 * to avoid some invalid operation before GC enable 910 */ 911 adev->gfx.is_poweron = false; 912 } 913 914 adev->mes.ring[0].sched.ready = false; 915 } 916 917 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id) 918 { 919 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 920 case IP_VERSION(13, 0, 0): 921 /* no vf autoload, white list */ 922 if (ucode_id == AMDGPU_UCODE_ID_VCN1 || 923 ucode_id == AMDGPU_UCODE_ID_VCN) 924 return false; 925 else 926 return true; 927 case IP_VERSION(11, 0, 9): 928 case IP_VERSION(11, 0, 7): 929 /* black list for CHIP_NAVI12 and CHIP_SIENNA_CICHLID */ 930 if (ucode_id == AMDGPU_UCODE_ID_RLC_G 931 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 932 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 933 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 934 || ucode_id == AMDGPU_UCODE_ID_SMC) 935 return true; 936 else 937 return false; 938 case IP_VERSION(13, 0, 10): 939 /* white list */ 940 if (ucode_id == AMDGPU_UCODE_ID_CAP 941 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP 942 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME 943 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC 944 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK 945 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK 946 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK 947 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK 948 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK 949 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK 950 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK 951 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK 952 || ucode_id == AMDGPU_UCODE_ID_CP_MES 953 || ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA 954 || ucode_id == AMDGPU_UCODE_ID_CP_MES1 955 || ucode_id == AMDGPU_UCODE_ID_CP_MES1_DATA 956 || ucode_id == AMDGPU_UCODE_ID_VCN1 957 || ucode_id == AMDGPU_UCODE_ID_VCN) 958 return false; 959 else 960 return true; 961 default: 962 /* lagacy black list */ 963 if (ucode_id == AMDGPU_UCODE_ID_SDMA0 964 || ucode_id == AMDGPU_UCODE_ID_SDMA1 965 || ucode_id == AMDGPU_UCODE_ID_SDMA2 966 || ucode_id == AMDGPU_UCODE_ID_SDMA3 967 || ucode_id == AMDGPU_UCODE_ID_SDMA4 968 || ucode_id == AMDGPU_UCODE_ID_SDMA5 969 || ucode_id == AMDGPU_UCODE_ID_SDMA6 970 || ucode_id == AMDGPU_UCODE_ID_SDMA7 971 || ucode_id == AMDGPU_UCODE_ID_RLC_G 972 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 973 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 974 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 975 || ucode_id == AMDGPU_UCODE_ID_SMC) 976 return true; 977 else 978 return false; 979 } 980 } 981 982 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 983 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 984 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size) 985 { 986 uint32_t i; 987 988 if (!adev->virt.is_mm_bw_enabled) 989 return; 990 991 if (encode) { 992 for (i = 0; i < encode_array_size; i++) { 993 encode[i].max_width = adev->virt.encode_max_dimension_pixels; 994 encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels; 995 if (encode[i].max_width > 0) 996 encode[i].max_height = encode[i].max_pixels_per_frame / encode[i].max_width; 997 else 998 encode[i].max_height = 0; 999 } 1000 } 1001 1002 if (decode) { 1003 for (i = 0; i < decode_array_size; i++) { 1004 decode[i].max_width = adev->virt.decode_max_dimension_pixels; 1005 decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels; 1006 if (decode[i].max_width > 0) 1007 decode[i].max_height = decode[i].max_pixels_per_frame / decode[i].max_width; 1008 else 1009 decode[i].max_height = 0; 1010 } 1011 } 1012 } 1013 1014 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 1015 u32 acc_flags, u32 hwip, 1016 bool write, u32 *rlcg_flag) 1017 { 1018 bool ret = false; 1019 1020 switch (hwip) { 1021 case GC_HWIP: 1022 if (amdgpu_sriov_reg_indirect_gc(adev)) { 1023 *rlcg_flag = 1024 write ? AMDGPU_RLCG_GC_WRITE : AMDGPU_RLCG_GC_READ; 1025 ret = true; 1026 /* only in new version, AMDGPU_REGS_NO_KIQ and 1027 * AMDGPU_REGS_RLC are enabled simultaneously */ 1028 } else if ((acc_flags & AMDGPU_REGS_RLC) && 1029 !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) { 1030 *rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY; 1031 ret = true; 1032 } 1033 break; 1034 case MMHUB_HWIP: 1035 if (amdgpu_sriov_reg_indirect_mmhub(adev) && 1036 (acc_flags & AMDGPU_REGS_RLC) && write) { 1037 *rlcg_flag = AMDGPU_RLCG_MMHUB_WRITE; 1038 ret = true; 1039 } 1040 break; 1041 default: 1042 break; 1043 } 1044 return ret; 1045 } 1046 1047 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id) 1048 { 1049 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1050 uint32_t timeout = 50000; 1051 uint32_t i, tmp; 1052 uint32_t ret = 0; 1053 void *scratch_reg0; 1054 void *scratch_reg1; 1055 void *scratch_reg2; 1056 void *scratch_reg3; 1057 void *spare_int; 1058 unsigned long flags; 1059 1060 if (!adev->gfx.rlc.rlcg_reg_access_supported) { 1061 dev_err(adev->dev, 1062 "indirect registers access through rlcg is not available\n"); 1063 return 0; 1064 } 1065 1066 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { 1067 dev_err(adev->dev, "invalid xcc\n"); 1068 return 0; 1069 } 1070 1071 if (amdgpu_device_skip_hw_access(adev)) 1072 return 0; 1073 1074 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; 1075 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0; 1076 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1; 1077 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; 1078 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3; 1079 1080 spin_lock_irqsave(&adev->virt.rlcg_reg_lock, flags); 1081 1082 if (reg_access_ctrl->spare_int) 1083 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int; 1084 1085 if (offset == reg_access_ctrl->grbm_cntl) { 1086 /* if the target reg offset is grbm_cntl, write to scratch_reg2 */ 1087 writel(v, scratch_reg2); 1088 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY) 1089 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 1090 } else if (offset == reg_access_ctrl->grbm_idx) { 1091 /* if the target reg offset is grbm_idx, write to scratch_reg3 */ 1092 writel(v, scratch_reg3); 1093 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY) 1094 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 1095 } else { 1096 /* 1097 * SCRATCH_REG0 = read/write value 1098 * SCRATCH_REG1[30:28] = command 1099 * SCRATCH_REG1[19:0] = address in dword 1100 * SCRATCH_REG1[27:24] = Error reporting 1101 */ 1102 writel(v, scratch_reg0); 1103 writel((offset | flag), scratch_reg1); 1104 if (reg_access_ctrl->spare_int) 1105 writel(1, spare_int); 1106 1107 for (i = 0; i < timeout; i++) { 1108 tmp = readl(scratch_reg1); 1109 if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK)) 1110 break; 1111 udelay(10); 1112 } 1113 1114 tmp = readl(scratch_reg1); 1115 if (i >= timeout || (tmp & AMDGPU_RLCG_SCRATCH1_ERROR_MASK) != 0) { 1116 if (amdgpu_sriov_rlcg_error_report_enabled(adev)) { 1117 if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) { 1118 dev_err(adev->dev, 1119 "vfgate is disabled, rlcg failed to program reg: 0x%05x\n", offset); 1120 } else if (tmp & AMDGPU_RLCG_WRONG_OPERATION_TYPE) { 1121 dev_err(adev->dev, 1122 "wrong operation type, rlcg failed to program reg: 0x%05x\n", offset); 1123 } else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) { 1124 dev_err(adev->dev, 1125 "register is not in range, rlcg failed to program reg: 0x%05x\n", offset); 1126 } else { 1127 dev_err(adev->dev, 1128 "unknown error type, rlcg failed to program reg: 0x%05x\n", offset); 1129 } 1130 } else { 1131 dev_err(adev->dev, 1132 "timeout: rlcg faled to program reg: 0x%05x\n", offset); 1133 } 1134 } 1135 } 1136 1137 ret = readl(scratch_reg0); 1138 1139 spin_unlock_irqrestore(&adev->virt.rlcg_reg_lock, flags); 1140 1141 return ret; 1142 } 1143 1144 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 1145 u32 offset, u32 value, 1146 u32 acc_flags, u32 hwip, u32 xcc_id) 1147 { 1148 u32 rlcg_flag; 1149 1150 if (amdgpu_device_skip_hw_access(adev)) 1151 return; 1152 1153 if (!amdgpu_sriov_runtime(adev) && 1154 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) { 1155 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag, xcc_id); 1156 return; 1157 } 1158 1159 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1160 WREG32_NO_KIQ(offset, value); 1161 else 1162 WREG32(offset, value); 1163 } 1164 1165 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 1166 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id) 1167 { 1168 u32 rlcg_flag; 1169 1170 if (amdgpu_device_skip_hw_access(adev)) 1171 return 0; 1172 1173 if (!amdgpu_sriov_runtime(adev) && 1174 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag)) 1175 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag, xcc_id); 1176 1177 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1178 return RREG32_NO_KIQ(offset); 1179 else 1180 return RREG32(offset); 1181 } 1182 1183 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev) 1184 { 1185 bool xnack_mode = true; 1186 1187 if (amdgpu_sriov_vf(adev) && 1188 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 1189 xnack_mode = false; 1190 1191 return xnack_mode; 1192 } 1193 1194 bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev) 1195 { 1196 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1197 1198 if (!amdgpu_sriov_ras_caps_en(adev)) 1199 return false; 1200 1201 if (adev->virt.ras_en_caps.bits.block_umc) 1202 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__UMC); 1203 if (adev->virt.ras_en_caps.bits.block_sdma) 1204 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SDMA); 1205 if (adev->virt.ras_en_caps.bits.block_gfx) 1206 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__GFX); 1207 if (adev->virt.ras_en_caps.bits.block_mmhub) 1208 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MMHUB); 1209 if (adev->virt.ras_en_caps.bits.block_athub) 1210 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__ATHUB); 1211 if (adev->virt.ras_en_caps.bits.block_pcie_bif) 1212 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__PCIE_BIF); 1213 if (adev->virt.ras_en_caps.bits.block_hdp) 1214 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__HDP); 1215 if (adev->virt.ras_en_caps.bits.block_xgmi_wafl) 1216 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__XGMI_WAFL); 1217 if (adev->virt.ras_en_caps.bits.block_df) 1218 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__DF); 1219 if (adev->virt.ras_en_caps.bits.block_smn) 1220 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SMN); 1221 if (adev->virt.ras_en_caps.bits.block_sem) 1222 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SEM); 1223 if (adev->virt.ras_en_caps.bits.block_mp0) 1224 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MP0); 1225 if (adev->virt.ras_en_caps.bits.block_mp1) 1226 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MP1); 1227 if (adev->virt.ras_en_caps.bits.block_fuse) 1228 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__FUSE); 1229 if (adev->virt.ras_en_caps.bits.block_mca) 1230 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MCA); 1231 if (adev->virt.ras_en_caps.bits.block_vcn) 1232 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__VCN); 1233 if (adev->virt.ras_en_caps.bits.block_jpeg) 1234 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__JPEG); 1235 if (adev->virt.ras_en_caps.bits.block_ih) 1236 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__IH); 1237 if (adev->virt.ras_en_caps.bits.block_mpio) 1238 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MPIO); 1239 1240 if (adev->virt.ras_en_caps.bits.poison_propogation_mode) 1241 con->poison_supported = true; /* Poison is handled by host */ 1242 1243 return true; 1244 } 1245 1246 static inline enum amd_sriov_ras_telemetry_gpu_block 1247 amdgpu_ras_block_to_sriov(struct amdgpu_device *adev, enum amdgpu_ras_block block) { 1248 switch (block) { 1249 case AMDGPU_RAS_BLOCK__UMC: 1250 return RAS_TELEMETRY_GPU_BLOCK_UMC; 1251 case AMDGPU_RAS_BLOCK__SDMA: 1252 return RAS_TELEMETRY_GPU_BLOCK_SDMA; 1253 case AMDGPU_RAS_BLOCK__GFX: 1254 return RAS_TELEMETRY_GPU_BLOCK_GFX; 1255 case AMDGPU_RAS_BLOCK__MMHUB: 1256 return RAS_TELEMETRY_GPU_BLOCK_MMHUB; 1257 case AMDGPU_RAS_BLOCK__ATHUB: 1258 return RAS_TELEMETRY_GPU_BLOCK_ATHUB; 1259 case AMDGPU_RAS_BLOCK__PCIE_BIF: 1260 return RAS_TELEMETRY_GPU_BLOCK_PCIE_BIF; 1261 case AMDGPU_RAS_BLOCK__HDP: 1262 return RAS_TELEMETRY_GPU_BLOCK_HDP; 1263 case AMDGPU_RAS_BLOCK__XGMI_WAFL: 1264 return RAS_TELEMETRY_GPU_BLOCK_XGMI_WAFL; 1265 case AMDGPU_RAS_BLOCK__DF: 1266 return RAS_TELEMETRY_GPU_BLOCK_DF; 1267 case AMDGPU_RAS_BLOCK__SMN: 1268 return RAS_TELEMETRY_GPU_BLOCK_SMN; 1269 case AMDGPU_RAS_BLOCK__SEM: 1270 return RAS_TELEMETRY_GPU_BLOCK_SEM; 1271 case AMDGPU_RAS_BLOCK__MP0: 1272 return RAS_TELEMETRY_GPU_BLOCK_MP0; 1273 case AMDGPU_RAS_BLOCK__MP1: 1274 return RAS_TELEMETRY_GPU_BLOCK_MP1; 1275 case AMDGPU_RAS_BLOCK__FUSE: 1276 return RAS_TELEMETRY_GPU_BLOCK_FUSE; 1277 case AMDGPU_RAS_BLOCK__MCA: 1278 return RAS_TELEMETRY_GPU_BLOCK_MCA; 1279 case AMDGPU_RAS_BLOCK__VCN: 1280 return RAS_TELEMETRY_GPU_BLOCK_VCN; 1281 case AMDGPU_RAS_BLOCK__JPEG: 1282 return RAS_TELEMETRY_GPU_BLOCK_JPEG; 1283 case AMDGPU_RAS_BLOCK__IH: 1284 return RAS_TELEMETRY_GPU_BLOCK_IH; 1285 case AMDGPU_RAS_BLOCK__MPIO: 1286 return RAS_TELEMETRY_GPU_BLOCK_MPIO; 1287 default: 1288 DRM_WARN_ONCE("Unsupported SRIOV RAS telemetry block 0x%x\n", 1289 block); 1290 return RAS_TELEMETRY_GPU_BLOCK_COUNT; 1291 } 1292 } 1293 1294 static int amdgpu_virt_cache_host_error_counts(struct amdgpu_device *adev, 1295 struct amdsriov_ras_telemetry *host_telemetry) 1296 { 1297 struct amd_sriov_ras_telemetry_error_count *tmp = NULL; 1298 uint32_t checksum, used_size; 1299 1300 checksum = host_telemetry->header.checksum; 1301 used_size = host_telemetry->header.used_size; 1302 1303 if (used_size > (AMD_SRIOV_RAS_TELEMETRY_SIZE_KB << 10)) 1304 return 0; 1305 1306 tmp = kmemdup(&host_telemetry->body.error_count, used_size, GFP_KERNEL); 1307 if (!tmp) 1308 return -ENOMEM; 1309 1310 if (checksum != amd_sriov_msg_checksum(tmp, used_size, 0, 0)) 1311 goto out; 1312 1313 memcpy(&adev->virt.count_cache, tmp, 1314 min(used_size, sizeof(adev->virt.count_cache))); 1315 out: 1316 kfree(tmp); 1317 1318 return 0; 1319 } 1320 1321 static int amdgpu_virt_req_ras_err_count_internal(struct amdgpu_device *adev, bool force_update) 1322 { 1323 struct amdgpu_virt *virt = &adev->virt; 1324 1325 /* Host allows 15 ras telemetry requests per 60 seconds. Afterwhich, the Host 1326 * will ignore incoming guest messages. Ratelimit the guest messages to 1327 * prevent guest self DOS. 1328 */ 1329 if (__ratelimit(&virt->ras.ras_error_cnt_rs) || force_update) { 1330 mutex_lock(&virt->ras.ras_telemetry_mutex); 1331 if (!virt->ops->req_ras_err_count(adev)) 1332 amdgpu_virt_cache_host_error_counts(adev, 1333 virt->fw_reserve.ras_telemetry); 1334 mutex_unlock(&virt->ras.ras_telemetry_mutex); 1335 } 1336 1337 return 0; 1338 } 1339 1340 /* Bypass ACA interface and query ECC counts directly from host */ 1341 int amdgpu_virt_req_ras_err_count(struct amdgpu_device *adev, enum amdgpu_ras_block block, 1342 struct ras_err_data *err_data) 1343 { 1344 enum amd_sriov_ras_telemetry_gpu_block sriov_block; 1345 1346 sriov_block = amdgpu_ras_block_to_sriov(adev, block); 1347 1348 if (sriov_block >= RAS_TELEMETRY_GPU_BLOCK_COUNT || 1349 !amdgpu_sriov_ras_telemetry_block_en(adev, sriov_block)) 1350 return -EOPNOTSUPP; 1351 1352 /* Host Access may be lost during reset, just return last cached data. */ 1353 if (down_read_trylock(&adev->reset_domain->sem)) { 1354 amdgpu_virt_req_ras_err_count_internal(adev, false); 1355 up_read(&adev->reset_domain->sem); 1356 } 1357 1358 err_data->ue_count = adev->virt.count_cache.block[sriov_block].ue_count; 1359 err_data->ce_count = adev->virt.count_cache.block[sriov_block].ce_count; 1360 err_data->de_count = adev->virt.count_cache.block[sriov_block].de_count; 1361 1362 return 0; 1363 } 1364 1365 static int 1366 amdgpu_virt_write_cpers_to_ring(struct amdgpu_device *adev, 1367 struct amdsriov_ras_telemetry *host_telemetry, 1368 u32 *more) 1369 { 1370 struct amd_sriov_ras_cper_dump *cper_dump = NULL; 1371 struct cper_hdr *entry = NULL; 1372 struct amdgpu_ring *ring = &adev->cper.ring_buf; 1373 uint32_t checksum, used_size, i; 1374 int ret = 0; 1375 1376 checksum = host_telemetry->header.checksum; 1377 used_size = host_telemetry->header.used_size; 1378 1379 if (used_size > (AMD_SRIOV_RAS_TELEMETRY_SIZE_KB << 10)) 1380 return 0; 1381 1382 cper_dump = kmemdup(&host_telemetry->body.cper_dump, used_size, GFP_KERNEL); 1383 if (!cper_dump) 1384 return -ENOMEM; 1385 1386 if (checksum != amd_sriov_msg_checksum(cper_dump, used_size, 0, 0)) 1387 goto out; 1388 1389 *more = cper_dump->more; 1390 1391 if (cper_dump->wptr < adev->virt.ras.cper_rptr) { 1392 dev_warn( 1393 adev->dev, 1394 "guest specified rptr that was too high! guest rptr: 0x%llx, host rptr: 0x%llx\n", 1395 adev->virt.ras.cper_rptr, cper_dump->wptr); 1396 1397 adev->virt.ras.cper_rptr = cper_dump->wptr; 1398 goto out; 1399 } 1400 1401 entry = (struct cper_hdr *)&cper_dump->buf[0]; 1402 1403 for (i = 0; i < cper_dump->count; i++) { 1404 amdgpu_cper_ring_write(ring, entry, entry->record_length); 1405 entry = (struct cper_hdr *)((char *)entry + 1406 entry->record_length); 1407 } 1408 1409 if (cper_dump->overflow_count) 1410 dev_warn(adev->dev, 1411 "host reported CPER overflow of 0x%llx entries!\n", 1412 cper_dump->overflow_count); 1413 1414 adev->virt.ras.cper_rptr = cper_dump->wptr; 1415 out: 1416 kfree(cper_dump); 1417 1418 return ret; 1419 } 1420 1421 static int amdgpu_virt_req_ras_cper_dump_internal(struct amdgpu_device *adev) 1422 { 1423 struct amdgpu_virt *virt = &adev->virt; 1424 int ret = 0; 1425 uint32_t more = 0; 1426 1427 if (!amdgpu_sriov_ras_cper_en(adev)) 1428 return -EOPNOTSUPP; 1429 1430 do { 1431 if (!virt->ops->req_ras_cper_dump(adev, virt->ras.cper_rptr)) 1432 ret = amdgpu_virt_write_cpers_to_ring( 1433 adev, virt->fw_reserve.ras_telemetry, &more); 1434 else 1435 ret = 0; 1436 } while (more); 1437 1438 return ret; 1439 } 1440 1441 int amdgpu_virt_req_ras_cper_dump(struct amdgpu_device *adev, bool force_update) 1442 { 1443 struct amdgpu_virt *virt = &adev->virt; 1444 int ret = 0; 1445 1446 if ((__ratelimit(&virt->ras.ras_cper_dump_rs) || force_update) && 1447 down_read_trylock(&adev->reset_domain->sem)) { 1448 mutex_lock(&virt->ras.ras_telemetry_mutex); 1449 ret = amdgpu_virt_req_ras_cper_dump_internal(adev); 1450 mutex_unlock(&virt->ras.ras_telemetry_mutex); 1451 up_read(&adev->reset_domain->sem); 1452 } 1453 1454 return ret; 1455 } 1456 1457 int amdgpu_virt_ras_telemetry_post_reset(struct amdgpu_device *adev) 1458 { 1459 unsigned long ue_count, ce_count; 1460 1461 if (amdgpu_sriov_ras_telemetry_en(adev)) { 1462 amdgpu_virt_req_ras_err_count_internal(adev, true); 1463 amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL); 1464 } 1465 1466 return 0; 1467 } 1468 1469 bool amdgpu_virt_ras_telemetry_block_en(struct amdgpu_device *adev, 1470 enum amdgpu_ras_block block) 1471 { 1472 enum amd_sriov_ras_telemetry_gpu_block sriov_block; 1473 1474 sriov_block = amdgpu_ras_block_to_sriov(adev, block); 1475 1476 if (sriov_block >= RAS_TELEMETRY_GPU_BLOCK_COUNT || 1477 !amdgpu_sriov_ras_telemetry_block_en(adev, sriov_block)) 1478 return false; 1479 1480 return true; 1481 } 1482