1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/dmi.h> 30 #include <linux/pci.h> 31 #include <linux/debugfs.h> 32 #include <drm/drm_drv.h> 33 34 #include "amdgpu.h" 35 #include "amdgpu_pm.h" 36 #include "amdgpu_vcn.h" 37 #include "soc15d.h" 38 39 /* Firmware Names */ 40 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 41 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 42 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 43 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 44 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 45 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 46 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 47 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 48 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 49 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 50 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 51 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 52 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 53 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 54 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 55 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 56 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin" 57 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin" 58 #define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin" 59 #define FIRMWARE_VCN4_0_3 "amdgpu/vcn_4_0_3.bin" 60 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin" 61 #define FIRMWARE_VCN4_0_5 "amdgpu/vcn_4_0_5.bin" 62 #define FIRMWARE_VCN4_0_6 "amdgpu/vcn_4_0_6.bin" 63 #define FIRMWARE_VCN5_0_0 "amdgpu/vcn_5_0_0.bin" 64 65 MODULE_FIRMWARE(FIRMWARE_RAVEN); 66 MODULE_FIRMWARE(FIRMWARE_PICASSO); 67 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 68 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 69 MODULE_FIRMWARE(FIRMWARE_RENOIR); 70 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 71 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 72 MODULE_FIRMWARE(FIRMWARE_NAVI10); 73 MODULE_FIRMWARE(FIRMWARE_NAVI14); 74 MODULE_FIRMWARE(FIRMWARE_NAVI12); 75 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 76 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 77 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 78 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 79 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 80 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 81 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2); 82 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0); 83 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2); 84 MODULE_FIRMWARE(FIRMWARE_VCN4_0_3); 85 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4); 86 MODULE_FIRMWARE(FIRMWARE_VCN4_0_5); 87 MODULE_FIRMWARE(FIRMWARE_VCN4_0_6); 88 MODULE_FIRMWARE(FIRMWARE_VCN5_0_0); 89 90 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 91 92 int amdgpu_vcn_early_init(struct amdgpu_device *adev) 93 { 94 char ucode_prefix[30]; 95 char fw_name[40]; 96 int r; 97 98 amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix)); 99 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); 100 r = amdgpu_ucode_request(adev, &adev->vcn.fw, fw_name); 101 if (r) 102 amdgpu_ucode_release(&adev->vcn.fw); 103 104 return r; 105 } 106 107 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 108 { 109 unsigned long bo_size; 110 const struct common_firmware_header *hdr; 111 unsigned char fw_check; 112 unsigned int fw_shared_size, log_offset; 113 int i, r; 114 115 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 116 mutex_init(&adev->vcn.vcn_pg_lock); 117 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 118 atomic_set(&adev->vcn.total_submission_cnt, 0); 119 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 120 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 121 122 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 123 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 124 adev->vcn.indirect_sram = true; 125 126 /* 127 * Some Steam Deck's BIOS versions are incompatible with the 128 * indirect SRAM mode, leading to amdgpu being unable to get 129 * properly probed (and even potentially crashing the kernel). 130 * Hence, check for these versions here - notice this is 131 * restricted to Vangogh (Deck's APU). 132 */ 133 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 0, 2)) { 134 const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION); 135 136 if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) || 137 !strncmp("F7A0114", bios_ver, 7))) { 138 adev->vcn.indirect_sram = false; 139 dev_info(adev->dev, 140 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver); 141 } 142 } 143 144 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 145 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 146 147 /* Bit 20-23, it is encode major and non-zero for new naming convention. 148 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 149 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 150 * is zero in old naming convention, this field is always zero so far. 151 * These four bits are used to tell which naming convention is present. 152 */ 153 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 154 if (fw_check) { 155 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 156 157 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 158 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 159 enc_major = fw_check; 160 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 161 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 162 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 163 enc_major, enc_minor, dec_ver, vep, fw_rev); 164 } else { 165 unsigned int version_major, version_minor, family_id; 166 167 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 168 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 169 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 170 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 171 version_major, version_minor, family_id); 172 } 173 174 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 175 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 176 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 177 178 if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) { 179 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); 180 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log); 181 } else { 182 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 183 log_offset = offsetof(struct amdgpu_fw_shared, fw_log); 184 } 185 186 bo_size += fw_shared_size; 187 188 if (amdgpu_vcnfw_log) 189 bo_size += AMDGPU_VCNFW_LOG_SIZE; 190 191 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 192 if (adev->vcn.harvest_config & (1 << i)) 193 continue; 194 195 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 196 AMDGPU_GEM_DOMAIN_VRAM | 197 AMDGPU_GEM_DOMAIN_GTT, 198 &adev->vcn.inst[i].vcpu_bo, 199 &adev->vcn.inst[i].gpu_addr, 200 &adev->vcn.inst[i].cpu_addr); 201 if (r) { 202 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 203 return r; 204 } 205 206 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr + 207 bo_size - fw_shared_size; 208 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr + 209 bo_size - fw_shared_size; 210 211 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size; 212 213 if (amdgpu_vcnfw_log) { 214 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 215 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 216 adev->vcn.inst[i].fw_shared.log_offset = log_offset; 217 } 218 219 if (adev->vcn.indirect_sram) { 220 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 221 AMDGPU_GEM_DOMAIN_VRAM | 222 AMDGPU_GEM_DOMAIN_GTT, 223 &adev->vcn.inst[i].dpg_sram_bo, 224 &adev->vcn.inst[i].dpg_sram_gpu_addr, 225 &adev->vcn.inst[i].dpg_sram_cpu_addr); 226 if (r) { 227 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 228 return r; 229 } 230 } 231 } 232 233 return 0; 234 } 235 236 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 237 { 238 int i, j; 239 240 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 241 if (adev->vcn.harvest_config & (1 << j)) 242 continue; 243 244 amdgpu_bo_free_kernel( 245 &adev->vcn.inst[j].dpg_sram_bo, 246 &adev->vcn.inst[j].dpg_sram_gpu_addr, 247 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 248 249 kvfree(adev->vcn.inst[j].saved_bo); 250 251 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 252 &adev->vcn.inst[j].gpu_addr, 253 (void **)&adev->vcn.inst[j].cpu_addr); 254 255 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 256 257 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 258 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 259 } 260 261 amdgpu_ucode_release(&adev->vcn.fw); 262 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 263 mutex_destroy(&adev->vcn.vcn_pg_lock); 264 265 return 0; 266 } 267 268 /* from vcn4 and above, only unified queue is used */ 269 static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring) 270 { 271 struct amdgpu_device *adev = ring->adev; 272 bool ret = false; 273 274 if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) 275 ret = true; 276 277 return ret; 278 } 279 280 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 281 { 282 bool ret = false; 283 int vcn_config = adev->vcn.vcn_config[vcn_instance]; 284 285 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) 286 ret = true; 287 else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) 288 ret = true; 289 else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) 290 ret = true; 291 292 return ret; 293 } 294 295 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 296 { 297 unsigned int size; 298 void *ptr; 299 int i, idx; 300 301 bool in_ras_intr = amdgpu_ras_intr_triggered(); 302 303 cancel_delayed_work_sync(&adev->vcn.idle_work); 304 305 /* err_event_athub will corrupt VCPU buffer, so we need to 306 * restore fw data and clear buffer in amdgpu_vcn_resume() */ 307 if (in_ras_intr) 308 return 0; 309 310 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 311 if (adev->vcn.harvest_config & (1 << i)) 312 continue; 313 if (adev->vcn.inst[i].vcpu_bo == NULL) 314 return 0; 315 316 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 317 ptr = adev->vcn.inst[i].cpu_addr; 318 319 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 320 if (!adev->vcn.inst[i].saved_bo) 321 return -ENOMEM; 322 323 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 324 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 325 drm_dev_exit(idx); 326 } 327 } 328 return 0; 329 } 330 331 int amdgpu_vcn_resume(struct amdgpu_device *adev) 332 { 333 unsigned int size; 334 void *ptr; 335 int i, idx; 336 337 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 338 if (adev->vcn.harvest_config & (1 << i)) 339 continue; 340 if (adev->vcn.inst[i].vcpu_bo == NULL) 341 return -EINVAL; 342 343 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 344 ptr = adev->vcn.inst[i].cpu_addr; 345 346 if (adev->vcn.inst[i].saved_bo != NULL) { 347 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 348 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 349 drm_dev_exit(idx); 350 } 351 kvfree(adev->vcn.inst[i].saved_bo); 352 adev->vcn.inst[i].saved_bo = NULL; 353 } else { 354 const struct common_firmware_header *hdr; 355 unsigned int offset; 356 357 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 358 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 359 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 360 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 361 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 362 le32_to_cpu(hdr->ucode_size_bytes)); 363 drm_dev_exit(idx); 364 } 365 size -= le32_to_cpu(hdr->ucode_size_bytes); 366 ptr += le32_to_cpu(hdr->ucode_size_bytes); 367 } 368 memset_io(ptr, 0, size); 369 } 370 } 371 return 0; 372 } 373 374 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 375 { 376 struct amdgpu_device *adev = 377 container_of(work, struct amdgpu_device, vcn.idle_work.work); 378 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 379 unsigned int i, j; 380 int r = 0; 381 382 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 383 if (adev->vcn.harvest_config & (1 << j)) 384 continue; 385 386 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 387 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 388 389 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 390 struct dpg_pause_state new_state; 391 392 if (fence[j] || 393 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 394 new_state.fw_based = VCN_DPG_STATE__PAUSE; 395 else 396 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 397 398 adev->vcn.pause_dpg_mode(adev, j, &new_state); 399 } 400 401 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 402 fences += fence[j]; 403 } 404 405 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 406 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 407 AMD_PG_STATE_GATE); 408 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 409 false); 410 if (r) 411 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 412 } else { 413 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 414 } 415 } 416 417 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 418 { 419 struct amdgpu_device *adev = ring->adev; 420 int r = 0; 421 422 atomic_inc(&adev->vcn.total_submission_cnt); 423 424 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 425 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 426 true); 427 if (r) 428 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 429 } 430 431 mutex_lock(&adev->vcn.vcn_pg_lock); 432 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 433 AMD_PG_STATE_UNGATE); 434 435 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 436 struct dpg_pause_state new_state; 437 438 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 439 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 440 new_state.fw_based = VCN_DPG_STATE__PAUSE; 441 } else { 442 unsigned int fences = 0; 443 unsigned int i; 444 445 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 446 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 447 448 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 449 new_state.fw_based = VCN_DPG_STATE__PAUSE; 450 else 451 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 452 } 453 454 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 455 } 456 mutex_unlock(&adev->vcn.vcn_pg_lock); 457 } 458 459 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 460 { 461 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 462 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 463 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 464 465 atomic_dec(&ring->adev->vcn.total_submission_cnt); 466 467 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 468 } 469 470 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 471 { 472 struct amdgpu_device *adev = ring->adev; 473 uint32_t tmp = 0; 474 unsigned int i; 475 int r; 476 477 /* VCN in SRIOV does not support direct register read/write */ 478 if (amdgpu_sriov_vf(adev)) 479 return 0; 480 481 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 482 r = amdgpu_ring_alloc(ring, 3); 483 if (r) 484 return r; 485 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 486 amdgpu_ring_write(ring, 0xDEADBEEF); 487 amdgpu_ring_commit(ring); 488 for (i = 0; i < adev->usec_timeout; i++) { 489 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 490 if (tmp == 0xDEADBEEF) 491 break; 492 udelay(1); 493 } 494 495 if (i >= adev->usec_timeout) 496 r = -ETIMEDOUT; 497 498 return r; 499 } 500 501 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 502 { 503 struct amdgpu_device *adev = ring->adev; 504 uint32_t rptr; 505 unsigned int i; 506 int r; 507 508 if (amdgpu_sriov_vf(adev)) 509 return 0; 510 511 r = amdgpu_ring_alloc(ring, 16); 512 if (r) 513 return r; 514 515 rptr = amdgpu_ring_get_rptr(ring); 516 517 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 518 amdgpu_ring_commit(ring); 519 520 for (i = 0; i < adev->usec_timeout; i++) { 521 if (amdgpu_ring_get_rptr(ring) != rptr) 522 break; 523 udelay(1); 524 } 525 526 if (i >= adev->usec_timeout) 527 r = -ETIMEDOUT; 528 529 return r; 530 } 531 532 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 533 struct amdgpu_ib *ib_msg, 534 struct dma_fence **fence) 535 { 536 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 537 struct amdgpu_device *adev = ring->adev; 538 struct dma_fence *f = NULL; 539 struct amdgpu_job *job; 540 struct amdgpu_ib *ib; 541 int i, r; 542 543 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 544 64, AMDGPU_IB_POOL_DIRECT, 545 &job); 546 if (r) 547 goto err; 548 549 ib = &job->ibs[0]; 550 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 551 ib->ptr[1] = addr; 552 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 553 ib->ptr[3] = addr >> 32; 554 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 555 ib->ptr[5] = 0; 556 for (i = 6; i < 16; i += 2) { 557 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 558 ib->ptr[i+1] = 0; 559 } 560 ib->length_dw = 16; 561 562 r = amdgpu_job_submit_direct(job, ring, &f); 563 if (r) 564 goto err_free; 565 566 amdgpu_ib_free(adev, ib_msg, f); 567 568 if (fence) 569 *fence = dma_fence_get(f); 570 dma_fence_put(f); 571 572 return 0; 573 574 err_free: 575 amdgpu_job_free(job); 576 err: 577 amdgpu_ib_free(adev, ib_msg, f); 578 return r; 579 } 580 581 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 582 struct amdgpu_ib *ib) 583 { 584 struct amdgpu_device *adev = ring->adev; 585 uint32_t *msg; 586 int r, i; 587 588 memset(ib, 0, sizeof(*ib)); 589 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 590 AMDGPU_IB_POOL_DIRECT, 591 ib); 592 if (r) 593 return r; 594 595 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 596 msg[0] = cpu_to_le32(0x00000028); 597 msg[1] = cpu_to_le32(0x00000038); 598 msg[2] = cpu_to_le32(0x00000001); 599 msg[3] = cpu_to_le32(0x00000000); 600 msg[4] = cpu_to_le32(handle); 601 msg[5] = cpu_to_le32(0x00000000); 602 msg[6] = cpu_to_le32(0x00000001); 603 msg[7] = cpu_to_le32(0x00000028); 604 msg[8] = cpu_to_le32(0x00000010); 605 msg[9] = cpu_to_le32(0x00000000); 606 msg[10] = cpu_to_le32(0x00000007); 607 msg[11] = cpu_to_le32(0x00000000); 608 msg[12] = cpu_to_le32(0x00000780); 609 msg[13] = cpu_to_le32(0x00000440); 610 for (i = 14; i < 1024; ++i) 611 msg[i] = cpu_to_le32(0x0); 612 613 return 0; 614 } 615 616 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 617 struct amdgpu_ib *ib) 618 { 619 struct amdgpu_device *adev = ring->adev; 620 uint32_t *msg; 621 int r, i; 622 623 memset(ib, 0, sizeof(*ib)); 624 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 625 AMDGPU_IB_POOL_DIRECT, 626 ib); 627 if (r) 628 return r; 629 630 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 631 msg[0] = cpu_to_le32(0x00000028); 632 msg[1] = cpu_to_le32(0x00000018); 633 msg[2] = cpu_to_le32(0x00000000); 634 msg[3] = cpu_to_le32(0x00000002); 635 msg[4] = cpu_to_le32(handle); 636 msg[5] = cpu_to_le32(0x00000000); 637 for (i = 6; i < 1024; ++i) 638 msg[i] = cpu_to_le32(0x0); 639 640 return 0; 641 } 642 643 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 644 { 645 struct dma_fence *fence = NULL; 646 struct amdgpu_ib ib; 647 long r; 648 649 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 650 if (r) 651 goto error; 652 653 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 654 if (r) 655 goto error; 656 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 657 if (r) 658 goto error; 659 660 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 661 if (r) 662 goto error; 663 664 r = dma_fence_wait_timeout(fence, false, timeout); 665 if (r == 0) 666 r = -ETIMEDOUT; 667 else if (r > 0) 668 r = 0; 669 670 dma_fence_put(fence); 671 error: 672 return r; 673 } 674 675 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, 676 uint32_t ib_pack_in_dw, bool enc) 677 { 678 uint32_t *ib_checksum; 679 680 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */ 681 ib->ptr[ib->length_dw++] = 0x30000002; 682 ib_checksum = &ib->ptr[ib->length_dw++]; 683 ib->ptr[ib->length_dw++] = ib_pack_in_dw; 684 685 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */ 686 ib->ptr[ib->length_dw++] = 0x30000001; 687 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3; 688 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t); 689 690 return ib_checksum; 691 } 692 693 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum, 694 uint32_t ib_pack_in_dw) 695 { 696 uint32_t i; 697 uint32_t checksum = 0; 698 699 for (i = 0; i < ib_pack_in_dw; i++) 700 checksum += *(*ib_checksum + 2 + i); 701 702 **ib_checksum = checksum; 703 } 704 705 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 706 struct amdgpu_ib *ib_msg, 707 struct dma_fence **fence) 708 { 709 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 710 unsigned int ib_size_dw = 64; 711 struct amdgpu_device *adev = ring->adev; 712 struct dma_fence *f = NULL; 713 struct amdgpu_job *job; 714 struct amdgpu_ib *ib; 715 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 716 bool sq = amdgpu_vcn_using_unified_queue(ring); 717 uint32_t *ib_checksum; 718 uint32_t ib_pack_in_dw; 719 int i, r; 720 721 if (sq) 722 ib_size_dw += 8; 723 724 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 725 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 726 &job); 727 if (r) 728 goto err; 729 730 ib = &job->ibs[0]; 731 ib->length_dw = 0; 732 733 /* single queue headers */ 734 if (sq) { 735 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t) 736 + 4 + 2; /* engine info + decoding ib in dw */ 737 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false); 738 } 739 740 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 741 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 742 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 743 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 744 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 745 746 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 747 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 748 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 749 750 for (i = ib->length_dw; i < ib_size_dw; ++i) 751 ib->ptr[i] = 0x0; 752 753 if (sq) 754 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw); 755 756 r = amdgpu_job_submit_direct(job, ring, &f); 757 if (r) 758 goto err_free; 759 760 amdgpu_ib_free(adev, ib_msg, f); 761 762 if (fence) 763 *fence = dma_fence_get(f); 764 dma_fence_put(f); 765 766 return 0; 767 768 err_free: 769 amdgpu_job_free(job); 770 err: 771 amdgpu_ib_free(adev, ib_msg, f); 772 return r; 773 } 774 775 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 776 { 777 struct dma_fence *fence = NULL; 778 struct amdgpu_ib ib; 779 long r; 780 781 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 782 if (r) 783 goto error; 784 785 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 786 if (r) 787 goto error; 788 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 789 if (r) 790 goto error; 791 792 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 793 if (r) 794 goto error; 795 796 r = dma_fence_wait_timeout(fence, false, timeout); 797 if (r == 0) 798 r = -ETIMEDOUT; 799 else if (r > 0) 800 r = 0; 801 802 dma_fence_put(fence); 803 error: 804 return r; 805 } 806 807 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 808 { 809 struct amdgpu_device *adev = ring->adev; 810 uint32_t rptr; 811 unsigned int i; 812 int r; 813 814 if (amdgpu_sriov_vf(adev)) 815 return 0; 816 817 r = amdgpu_ring_alloc(ring, 16); 818 if (r) 819 return r; 820 821 rptr = amdgpu_ring_get_rptr(ring); 822 823 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 824 amdgpu_ring_commit(ring); 825 826 for (i = 0; i < adev->usec_timeout; i++) { 827 if (amdgpu_ring_get_rptr(ring) != rptr) 828 break; 829 udelay(1); 830 } 831 832 if (i >= adev->usec_timeout) 833 r = -ETIMEDOUT; 834 835 return r; 836 } 837 838 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 839 struct amdgpu_ib *ib_msg, 840 struct dma_fence **fence) 841 { 842 unsigned int ib_size_dw = 16; 843 struct amdgpu_job *job; 844 struct amdgpu_ib *ib; 845 struct dma_fence *f = NULL; 846 uint32_t *ib_checksum = NULL; 847 uint64_t addr; 848 bool sq = amdgpu_vcn_using_unified_queue(ring); 849 int i, r; 850 851 if (sq) 852 ib_size_dw += 8; 853 854 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 855 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 856 &job); 857 if (r) 858 return r; 859 860 ib = &job->ibs[0]; 861 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 862 863 ib->length_dw = 0; 864 865 if (sq) 866 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 867 868 ib->ptr[ib->length_dw++] = 0x00000018; 869 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 870 ib->ptr[ib->length_dw++] = handle; 871 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 872 ib->ptr[ib->length_dw++] = addr; 873 ib->ptr[ib->length_dw++] = 0x0000000b; 874 875 ib->ptr[ib->length_dw++] = 0x00000014; 876 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 877 ib->ptr[ib->length_dw++] = 0x0000001c; 878 ib->ptr[ib->length_dw++] = 0x00000000; 879 ib->ptr[ib->length_dw++] = 0x00000000; 880 881 ib->ptr[ib->length_dw++] = 0x00000008; 882 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 883 884 for (i = ib->length_dw; i < ib_size_dw; ++i) 885 ib->ptr[i] = 0x0; 886 887 if (sq) 888 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 889 890 r = amdgpu_job_submit_direct(job, ring, &f); 891 if (r) 892 goto err; 893 894 if (fence) 895 *fence = dma_fence_get(f); 896 dma_fence_put(f); 897 898 return 0; 899 900 err: 901 amdgpu_job_free(job); 902 return r; 903 } 904 905 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 906 struct amdgpu_ib *ib_msg, 907 struct dma_fence **fence) 908 { 909 unsigned int ib_size_dw = 16; 910 struct amdgpu_job *job; 911 struct amdgpu_ib *ib; 912 struct dma_fence *f = NULL; 913 uint32_t *ib_checksum = NULL; 914 uint64_t addr; 915 bool sq = amdgpu_vcn_using_unified_queue(ring); 916 int i, r; 917 918 if (sq) 919 ib_size_dw += 8; 920 921 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 922 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 923 &job); 924 if (r) 925 return r; 926 927 ib = &job->ibs[0]; 928 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 929 930 ib->length_dw = 0; 931 932 if (sq) 933 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 934 935 ib->ptr[ib->length_dw++] = 0x00000018; 936 ib->ptr[ib->length_dw++] = 0x00000001; 937 ib->ptr[ib->length_dw++] = handle; 938 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 939 ib->ptr[ib->length_dw++] = addr; 940 ib->ptr[ib->length_dw++] = 0x0000000b; 941 942 ib->ptr[ib->length_dw++] = 0x00000014; 943 ib->ptr[ib->length_dw++] = 0x00000002; 944 ib->ptr[ib->length_dw++] = 0x0000001c; 945 ib->ptr[ib->length_dw++] = 0x00000000; 946 ib->ptr[ib->length_dw++] = 0x00000000; 947 948 ib->ptr[ib->length_dw++] = 0x00000008; 949 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 950 951 for (i = ib->length_dw; i < ib_size_dw; ++i) 952 ib->ptr[i] = 0x0; 953 954 if (sq) 955 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 956 957 r = amdgpu_job_submit_direct(job, ring, &f); 958 if (r) 959 goto err; 960 961 if (fence) 962 *fence = dma_fence_get(f); 963 dma_fence_put(f); 964 965 return 0; 966 967 err: 968 amdgpu_job_free(job); 969 return r; 970 } 971 972 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 973 { 974 struct amdgpu_device *adev = ring->adev; 975 struct dma_fence *fence = NULL; 976 struct amdgpu_ib ib; 977 long r; 978 979 memset(&ib, 0, sizeof(ib)); 980 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 981 AMDGPU_IB_POOL_DIRECT, 982 &ib); 983 if (r) 984 return r; 985 986 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 987 if (r) 988 goto error; 989 990 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 991 if (r) 992 goto error; 993 994 r = dma_fence_wait_timeout(fence, false, timeout); 995 if (r == 0) 996 r = -ETIMEDOUT; 997 else if (r > 0) 998 r = 0; 999 1000 error: 1001 amdgpu_ib_free(adev, &ib, fence); 1002 dma_fence_put(fence); 1003 1004 return r; 1005 } 1006 1007 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1008 { 1009 struct amdgpu_device *adev = ring->adev; 1010 long r; 1011 1012 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(4, 0, 3)) { 1013 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout); 1014 if (r) 1015 goto error; 1016 } 1017 1018 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout); 1019 1020 error: 1021 return r; 1022 } 1023 1024 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 1025 { 1026 switch (ring) { 1027 case 0: 1028 return AMDGPU_RING_PRIO_0; 1029 case 1: 1030 return AMDGPU_RING_PRIO_1; 1031 case 2: 1032 return AMDGPU_RING_PRIO_2; 1033 default: 1034 return AMDGPU_RING_PRIO_0; 1035 } 1036 } 1037 1038 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev) 1039 { 1040 int i; 1041 unsigned int idx; 1042 1043 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1044 const struct common_firmware_header *hdr; 1045 1046 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 1047 1048 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1049 if (adev->vcn.harvest_config & (1 << i)) 1050 continue; 1051 /* currently only support 2 FW instances */ 1052 if (i >= 2) { 1053 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 1054 break; 1055 } 1056 idx = AMDGPU_UCODE_ID_VCN + i; 1057 adev->firmware.ucode[idx].ucode_id = idx; 1058 adev->firmware.ucode[idx].fw = adev->vcn.fw; 1059 adev->firmware.fw_size += 1060 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 1061 1062 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == 1063 IP_VERSION(4, 0, 3)) 1064 break; 1065 } 1066 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 1067 } 1068 } 1069 1070 /* 1071 * debugfs for mapping vcn firmware log buffer. 1072 */ 1073 #if defined(CONFIG_DEBUG_FS) 1074 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf, 1075 size_t size, loff_t *pos) 1076 { 1077 struct amdgpu_vcn_inst *vcn; 1078 void *log_buf; 1079 volatile struct amdgpu_vcn_fwlog *plog; 1080 unsigned int read_pos, write_pos, available, i, read_bytes = 0; 1081 unsigned int read_num[2] = {0}; 1082 1083 vcn = file_inode(f)->i_private; 1084 if (!vcn) 1085 return -ENODEV; 1086 1087 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log) 1088 return -EFAULT; 1089 1090 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1091 1092 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf; 1093 read_pos = plog->rptr; 1094 write_pos = plog->wptr; 1095 1096 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE) 1097 return -EFAULT; 1098 1099 if (!size || (read_pos == write_pos)) 1100 return 0; 1101 1102 if (write_pos > read_pos) { 1103 available = write_pos - read_pos; 1104 read_num[0] = min_t(size_t, size, available); 1105 } else { 1106 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos; 1107 available = read_num[0] + write_pos - plog->header_size; 1108 if (size > available) 1109 read_num[1] = write_pos - plog->header_size; 1110 else if (size > read_num[0]) 1111 read_num[1] = size - read_num[0]; 1112 else 1113 read_num[0] = size; 1114 } 1115 1116 for (i = 0; i < 2; i++) { 1117 if (read_num[i]) { 1118 if (read_pos == AMDGPU_VCNFW_LOG_SIZE) 1119 read_pos = plog->header_size; 1120 if (read_num[i] == copy_to_user((buf + read_bytes), 1121 (log_buf + read_pos), read_num[i])) 1122 return -EFAULT; 1123 1124 read_bytes += read_num[i]; 1125 read_pos += read_num[i]; 1126 } 1127 } 1128 1129 plog->rptr = read_pos; 1130 *pos += read_bytes; 1131 return read_bytes; 1132 } 1133 1134 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = { 1135 .owner = THIS_MODULE, 1136 .read = amdgpu_debugfs_vcn_fwlog_read, 1137 .llseek = default_llseek 1138 }; 1139 #endif 1140 1141 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i, 1142 struct amdgpu_vcn_inst *vcn) 1143 { 1144 #if defined(CONFIG_DEBUG_FS) 1145 struct drm_minor *minor = adev_to_drm(adev)->primary; 1146 struct dentry *root = minor->debugfs_root; 1147 char name[32]; 1148 1149 sprintf(name, "amdgpu_vcn_%d_fwlog", i); 1150 debugfs_create_file_size(name, S_IFREG | 0444, root, vcn, 1151 &amdgpu_debugfs_vcnfwlog_fops, 1152 AMDGPU_VCNFW_LOG_SIZE); 1153 #endif 1154 } 1155 1156 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn) 1157 { 1158 #if defined(CONFIG_DEBUG_FS) 1159 volatile uint32_t *flag = vcn->fw_shared.cpu_addr; 1160 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1161 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size; 1162 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr; 1163 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr 1164 + vcn->fw_shared.log_offset; 1165 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG); 1166 fw_log->is_enabled = 1; 1167 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF); 1168 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32); 1169 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE); 1170 1171 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog); 1172 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE; 1173 log_buf->rptr = log_buf->header_size; 1174 log_buf->wptr = log_buf->header_size; 1175 log_buf->wrapped = 0; 1176 #endif 1177 } 1178 1179 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, 1180 struct amdgpu_irq_src *source, 1181 struct amdgpu_iv_entry *entry) 1182 { 1183 struct ras_common_if *ras_if = adev->vcn.ras_if; 1184 struct ras_dispatch_if ih_data = { 1185 .entry = entry, 1186 }; 1187 1188 if (!ras_if) 1189 return 0; 1190 1191 if (!amdgpu_sriov_vf(adev)) { 1192 ih_data.head = *ras_if; 1193 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 1194 } else { 1195 if (adev->virt.ops && adev->virt.ops->ras_poison_handler) 1196 adev->virt.ops->ras_poison_handler(adev, ras_if->block); 1197 else 1198 dev_warn(adev->dev, 1199 "No ras_poison_handler interface in SRIOV for VCN!\n"); 1200 } 1201 1202 return 0; 1203 } 1204 1205 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1206 { 1207 int r, i; 1208 1209 r = amdgpu_ras_block_late_init(adev, ras_block); 1210 if (r) 1211 return r; 1212 1213 if (amdgpu_ras_is_supported(adev, ras_block->block)) { 1214 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1215 if (adev->vcn.harvest_config & (1 << i) || 1216 !adev->vcn.inst[i].ras_poison_irq.funcs) 1217 continue; 1218 1219 r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0); 1220 if (r) 1221 goto late_fini; 1222 } 1223 } 1224 return 0; 1225 1226 late_fini: 1227 amdgpu_ras_block_late_fini(adev, ras_block); 1228 return r; 1229 } 1230 1231 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev) 1232 { 1233 int err; 1234 struct amdgpu_vcn_ras *ras; 1235 1236 if (!adev->vcn.ras) 1237 return 0; 1238 1239 ras = adev->vcn.ras; 1240 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 1241 if (err) { 1242 dev_err(adev->dev, "Failed to register vcn ras block!\n"); 1243 return err; 1244 } 1245 1246 strcpy(ras->ras_block.ras_comm.name, "vcn"); 1247 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; 1248 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; 1249 adev->vcn.ras_if = &ras->ras_block.ras_comm; 1250 1251 if (!ras->ras_block.ras_late_init) 1252 ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init; 1253 1254 return 0; 1255 } 1256 1257 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, 1258 enum AMDGPU_UCODE_ID ucode_id) 1259 { 1260 struct amdgpu_firmware_info ucode = { 1261 .ucode_id = (ucode_id ? ucode_id : 1262 (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 1263 AMDGPU_UCODE_ID_VCN0_RAM)), 1264 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1265 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1266 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr), 1267 }; 1268 1269 return psp_execute_ip_fw_load(&adev->psp, &ucode); 1270 } 1271