1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <drm/drm_drv.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_pm.h" 34 #include "amdgpu_vcn.h" 35 #include "soc15d.h" 36 37 /* Firmware Names */ 38 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 39 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 40 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 41 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 42 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 43 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 44 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 45 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 46 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 47 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 48 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 49 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 50 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 51 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 52 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 53 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 54 55 MODULE_FIRMWARE(FIRMWARE_RAVEN); 56 MODULE_FIRMWARE(FIRMWARE_PICASSO); 57 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 58 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 59 MODULE_FIRMWARE(FIRMWARE_RENOIR); 60 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 61 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 62 MODULE_FIRMWARE(FIRMWARE_NAVI10); 63 MODULE_FIRMWARE(FIRMWARE_NAVI14); 64 MODULE_FIRMWARE(FIRMWARE_NAVI12); 65 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 66 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 67 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 68 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 69 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 70 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 71 72 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 73 74 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 75 { 76 unsigned long bo_size; 77 const char *fw_name; 78 const struct common_firmware_header *hdr; 79 unsigned char fw_check; 80 int i, r; 81 82 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 83 mutex_init(&adev->vcn.vcn_pg_lock); 84 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 85 atomic_set(&adev->vcn.total_submission_cnt, 0); 86 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 87 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 88 89 switch (adev->ip_versions[UVD_HWIP][0]) { 90 case IP_VERSION(1, 0, 0): 91 case IP_VERSION(1, 0, 1): 92 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 93 fw_name = FIRMWARE_RAVEN2; 94 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 95 fw_name = FIRMWARE_PICASSO; 96 else 97 fw_name = FIRMWARE_RAVEN; 98 break; 99 case IP_VERSION(2, 5, 0): 100 fw_name = FIRMWARE_ARCTURUS; 101 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 102 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 103 adev->vcn.indirect_sram = true; 104 break; 105 case IP_VERSION(2, 2, 0): 106 if (adev->apu_flags & AMD_APU_IS_RENOIR) 107 fw_name = FIRMWARE_RENOIR; 108 else 109 fw_name = FIRMWARE_GREEN_SARDINE; 110 111 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 112 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 113 adev->vcn.indirect_sram = true; 114 break; 115 case IP_VERSION(2, 6, 0): 116 fw_name = FIRMWARE_ALDEBARAN; 117 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 118 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 119 adev->vcn.indirect_sram = true; 120 break; 121 case IP_VERSION(2, 0, 0): 122 fw_name = FIRMWARE_NAVI10; 123 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 124 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 125 adev->vcn.indirect_sram = true; 126 break; 127 case IP_VERSION(2, 0, 2): 128 if (adev->asic_type == CHIP_NAVI12) 129 fw_name = FIRMWARE_NAVI12; 130 else 131 fw_name = FIRMWARE_NAVI14; 132 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 133 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 134 adev->vcn.indirect_sram = true; 135 break; 136 case IP_VERSION(3, 0, 0): 137 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 138 fw_name = FIRMWARE_SIENNA_CICHLID; 139 else 140 fw_name = FIRMWARE_NAVY_FLOUNDER; 141 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 142 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 143 adev->vcn.indirect_sram = true; 144 break; 145 case IP_VERSION(3, 0, 2): 146 fw_name = FIRMWARE_VANGOGH; 147 break; 148 case IP_VERSION(3, 0, 16): 149 fw_name = FIRMWARE_DIMGREY_CAVEFISH; 150 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 151 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 152 adev->vcn.indirect_sram = true; 153 break; 154 case IP_VERSION(3, 0, 33): 155 fw_name = FIRMWARE_BEIGE_GOBY; 156 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 157 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 158 adev->vcn.indirect_sram = true; 159 break; 160 case IP_VERSION(3, 1, 1): 161 fw_name = FIRMWARE_YELLOW_CARP; 162 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 163 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 164 adev->vcn.indirect_sram = true; 165 break; 166 default: 167 return -EINVAL; 168 } 169 170 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); 171 if (r) { 172 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", 173 fw_name); 174 return r; 175 } 176 177 r = amdgpu_ucode_validate(adev->vcn.fw); 178 if (r) { 179 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", 180 fw_name); 181 release_firmware(adev->vcn.fw); 182 adev->vcn.fw = NULL; 183 return r; 184 } 185 186 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 187 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 188 189 /* Bit 20-23, it is encode major and non-zero for new naming convention. 190 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 191 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 192 * is zero in old naming convention, this field is always zero so far. 193 * These four bits are used to tell which naming convention is present. 194 */ 195 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 196 if (fw_check) { 197 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 198 199 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 200 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 201 enc_major = fw_check; 202 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 203 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 204 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 205 enc_major, enc_minor, dec_ver, vep, fw_rev); 206 } else { 207 unsigned int version_major, version_minor, family_id; 208 209 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 210 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 211 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 212 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 213 version_major, version_minor, family_id); 214 } 215 216 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 217 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 218 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 219 bo_size += AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 220 221 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 222 if (adev->vcn.harvest_config & (1 << i)) 223 continue; 224 225 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 226 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo, 227 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr); 228 if (r) { 229 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 230 return r; 231 } 232 233 adev->vcn.inst[i].fw_shared_cpu_addr = adev->vcn.inst[i].cpu_addr + 234 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 235 adev->vcn.inst[i].fw_shared_gpu_addr = adev->vcn.inst[i].gpu_addr + 236 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 237 238 if (adev->vcn.indirect_sram) { 239 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 240 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo, 241 &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr); 242 if (r) { 243 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 244 return r; 245 } 246 } 247 } 248 249 return 0; 250 } 251 252 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 253 { 254 int i, j; 255 256 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 257 if (adev->vcn.harvest_config & (1 << j)) 258 continue; 259 260 if (adev->vcn.indirect_sram) { 261 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo, 262 &adev->vcn.inst[j].dpg_sram_gpu_addr, 263 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 264 } 265 kvfree(adev->vcn.inst[j].saved_bo); 266 267 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 268 &adev->vcn.inst[j].gpu_addr, 269 (void **)&adev->vcn.inst[j].cpu_addr); 270 271 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 272 273 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 274 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 275 } 276 277 release_firmware(adev->vcn.fw); 278 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 279 mutex_destroy(&adev->vcn.vcn_pg_lock); 280 281 return 0; 282 } 283 284 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 285 { 286 bool ret = false; 287 288 int major; 289 int minor; 290 int revision; 291 292 /* if cannot find IP data, then this VCN does not exist */ 293 if (amdgpu_discovery_get_vcn_version(adev, vcn_instance, &major, &minor, &revision) != 0) 294 return true; 295 296 if ((type == VCN_ENCODE_RING) && (revision & VCN_BLOCK_ENCODE_DISABLE_MASK)) { 297 ret = true; 298 } else if ((type == VCN_DECODE_RING) && (revision & VCN_BLOCK_DECODE_DISABLE_MASK)) { 299 ret = true; 300 } else if ((type == VCN_UNIFIED_RING) && (revision & VCN_BLOCK_QUEUE_DISABLE_MASK)) { 301 ret = true; 302 } 303 304 return ret; 305 } 306 307 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 308 { 309 unsigned size; 310 void *ptr; 311 int i, idx; 312 313 cancel_delayed_work_sync(&adev->vcn.idle_work); 314 315 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 316 if (adev->vcn.harvest_config & (1 << i)) 317 continue; 318 if (adev->vcn.inst[i].vcpu_bo == NULL) 319 return 0; 320 321 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 322 ptr = adev->vcn.inst[i].cpu_addr; 323 324 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 325 if (!adev->vcn.inst[i].saved_bo) 326 return -ENOMEM; 327 328 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 329 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 330 drm_dev_exit(idx); 331 } 332 } 333 return 0; 334 } 335 336 int amdgpu_vcn_resume(struct amdgpu_device *adev) 337 { 338 unsigned size; 339 void *ptr; 340 int i, idx; 341 342 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 343 if (adev->vcn.harvest_config & (1 << i)) 344 continue; 345 if (adev->vcn.inst[i].vcpu_bo == NULL) 346 return -EINVAL; 347 348 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 349 ptr = adev->vcn.inst[i].cpu_addr; 350 351 if (adev->vcn.inst[i].saved_bo != NULL) { 352 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 353 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 354 drm_dev_exit(idx); 355 } 356 kvfree(adev->vcn.inst[i].saved_bo); 357 adev->vcn.inst[i].saved_bo = NULL; 358 } else { 359 const struct common_firmware_header *hdr; 360 unsigned offset; 361 362 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 363 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 364 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 365 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 366 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 367 le32_to_cpu(hdr->ucode_size_bytes)); 368 drm_dev_exit(idx); 369 } 370 size -= le32_to_cpu(hdr->ucode_size_bytes); 371 ptr += le32_to_cpu(hdr->ucode_size_bytes); 372 } 373 memset_io(ptr, 0, size); 374 } 375 } 376 return 0; 377 } 378 379 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 380 { 381 struct amdgpu_device *adev = 382 container_of(work, struct amdgpu_device, vcn.idle_work.work); 383 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 384 unsigned int i, j; 385 int r = 0; 386 387 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 388 if (adev->vcn.harvest_config & (1 << j)) 389 continue; 390 391 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 392 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 393 } 394 395 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 396 struct dpg_pause_state new_state; 397 398 if (fence[j] || 399 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 400 new_state.fw_based = VCN_DPG_STATE__PAUSE; 401 else 402 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 403 404 adev->vcn.pause_dpg_mode(adev, j, &new_state); 405 } 406 407 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 408 fences += fence[j]; 409 } 410 411 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 412 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 413 AMD_PG_STATE_GATE); 414 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 415 false); 416 if (r) 417 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 418 } else { 419 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 420 } 421 } 422 423 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 424 { 425 struct amdgpu_device *adev = ring->adev; 426 int r = 0; 427 428 atomic_inc(&adev->vcn.total_submission_cnt); 429 430 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 431 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 432 true); 433 if (r) 434 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 435 } 436 437 mutex_lock(&adev->vcn.vcn_pg_lock); 438 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 439 AMD_PG_STATE_UNGATE); 440 441 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 442 struct dpg_pause_state new_state; 443 444 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 445 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 446 new_state.fw_based = VCN_DPG_STATE__PAUSE; 447 } else { 448 unsigned int fences = 0; 449 unsigned int i; 450 451 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 452 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 453 454 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 455 new_state.fw_based = VCN_DPG_STATE__PAUSE; 456 else 457 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 458 } 459 460 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 461 } 462 mutex_unlock(&adev->vcn.vcn_pg_lock); 463 } 464 465 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 466 { 467 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 468 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 469 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 470 471 atomic_dec(&ring->adev->vcn.total_submission_cnt); 472 473 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 474 } 475 476 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 477 { 478 struct amdgpu_device *adev = ring->adev; 479 uint32_t tmp = 0; 480 unsigned i; 481 int r; 482 483 /* VCN in SRIOV does not support direct register read/write */ 484 if (amdgpu_sriov_vf(adev)) 485 return 0; 486 487 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 488 r = amdgpu_ring_alloc(ring, 3); 489 if (r) 490 return r; 491 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 492 amdgpu_ring_write(ring, 0xDEADBEEF); 493 amdgpu_ring_commit(ring); 494 for (i = 0; i < adev->usec_timeout; i++) { 495 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 496 if (tmp == 0xDEADBEEF) 497 break; 498 udelay(1); 499 } 500 501 if (i >= adev->usec_timeout) 502 r = -ETIMEDOUT; 503 504 return r; 505 } 506 507 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 508 { 509 struct amdgpu_device *adev = ring->adev; 510 uint32_t rptr; 511 unsigned int i; 512 int r; 513 514 if (amdgpu_sriov_vf(adev)) 515 return 0; 516 517 r = amdgpu_ring_alloc(ring, 16); 518 if (r) 519 return r; 520 521 rptr = amdgpu_ring_get_rptr(ring); 522 523 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 524 amdgpu_ring_commit(ring); 525 526 for (i = 0; i < adev->usec_timeout; i++) { 527 if (amdgpu_ring_get_rptr(ring) != rptr) 528 break; 529 udelay(1); 530 } 531 532 if (i >= adev->usec_timeout) 533 r = -ETIMEDOUT; 534 535 return r; 536 } 537 538 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 539 struct amdgpu_ib *ib_msg, 540 struct dma_fence **fence) 541 { 542 struct amdgpu_device *adev = ring->adev; 543 struct dma_fence *f = NULL; 544 struct amdgpu_job *job; 545 struct amdgpu_ib *ib; 546 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 547 int i, r; 548 549 r = amdgpu_job_alloc_with_ib(adev, 64, 550 AMDGPU_IB_POOL_DIRECT, &job); 551 if (r) 552 goto err; 553 554 ib = &job->ibs[0]; 555 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 556 ib->ptr[1] = addr; 557 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 558 ib->ptr[3] = addr >> 32; 559 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 560 ib->ptr[5] = 0; 561 for (i = 6; i < 16; i += 2) { 562 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 563 ib->ptr[i+1] = 0; 564 } 565 ib->length_dw = 16; 566 567 r = amdgpu_job_submit_direct(job, ring, &f); 568 if (r) 569 goto err_free; 570 571 amdgpu_ib_free(adev, ib_msg, f); 572 573 if (fence) 574 *fence = dma_fence_get(f); 575 dma_fence_put(f); 576 577 return 0; 578 579 err_free: 580 amdgpu_job_free(job); 581 err: 582 amdgpu_ib_free(adev, ib_msg, f); 583 return r; 584 } 585 586 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 587 struct amdgpu_ib *ib) 588 { 589 struct amdgpu_device *adev = ring->adev; 590 uint32_t *msg; 591 int r, i; 592 593 memset(ib, 0, sizeof(*ib)); 594 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 595 AMDGPU_IB_POOL_DIRECT, 596 ib); 597 if (r) 598 return r; 599 600 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 601 msg[0] = cpu_to_le32(0x00000028); 602 msg[1] = cpu_to_le32(0x00000038); 603 msg[2] = cpu_to_le32(0x00000001); 604 msg[3] = cpu_to_le32(0x00000000); 605 msg[4] = cpu_to_le32(handle); 606 msg[5] = cpu_to_le32(0x00000000); 607 msg[6] = cpu_to_le32(0x00000001); 608 msg[7] = cpu_to_le32(0x00000028); 609 msg[8] = cpu_to_le32(0x00000010); 610 msg[9] = cpu_to_le32(0x00000000); 611 msg[10] = cpu_to_le32(0x00000007); 612 msg[11] = cpu_to_le32(0x00000000); 613 msg[12] = cpu_to_le32(0x00000780); 614 msg[13] = cpu_to_le32(0x00000440); 615 for (i = 14; i < 1024; ++i) 616 msg[i] = cpu_to_le32(0x0); 617 618 return 0; 619 } 620 621 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 622 struct amdgpu_ib *ib) 623 { 624 struct amdgpu_device *adev = ring->adev; 625 uint32_t *msg; 626 int r, i; 627 628 memset(ib, 0, sizeof(*ib)); 629 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 630 AMDGPU_IB_POOL_DIRECT, 631 ib); 632 if (r) 633 return r; 634 635 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 636 msg[0] = cpu_to_le32(0x00000028); 637 msg[1] = cpu_to_le32(0x00000018); 638 msg[2] = cpu_to_le32(0x00000000); 639 msg[3] = cpu_to_le32(0x00000002); 640 msg[4] = cpu_to_le32(handle); 641 msg[5] = cpu_to_le32(0x00000000); 642 for (i = 6; i < 1024; ++i) 643 msg[i] = cpu_to_le32(0x0); 644 645 return 0; 646 } 647 648 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 649 { 650 struct dma_fence *fence = NULL; 651 struct amdgpu_ib ib; 652 long r; 653 654 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 655 if (r) 656 goto error; 657 658 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 659 if (r) 660 goto error; 661 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 662 if (r) 663 goto error; 664 665 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 666 if (r) 667 goto error; 668 669 r = dma_fence_wait_timeout(fence, false, timeout); 670 if (r == 0) 671 r = -ETIMEDOUT; 672 else if (r > 0) 673 r = 0; 674 675 dma_fence_put(fence); 676 error: 677 return r; 678 } 679 680 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 681 struct amdgpu_ib *ib_msg, 682 struct dma_fence **fence) 683 { 684 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 685 const unsigned int ib_size_dw = 64; 686 struct amdgpu_device *adev = ring->adev; 687 struct dma_fence *f = NULL; 688 struct amdgpu_job *job; 689 struct amdgpu_ib *ib; 690 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 691 int i, r; 692 693 r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4, 694 AMDGPU_IB_POOL_DIRECT, &job); 695 if (r) 696 goto err; 697 698 ib = &job->ibs[0]; 699 ib->length_dw = 0; 700 701 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 702 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 703 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 704 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 705 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 706 707 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 708 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 709 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 710 711 for (i = ib->length_dw; i < ib_size_dw; ++i) 712 ib->ptr[i] = 0x0; 713 714 r = amdgpu_job_submit_direct(job, ring, &f); 715 if (r) 716 goto err_free; 717 718 amdgpu_ib_free(adev, ib_msg, f); 719 720 if (fence) 721 *fence = dma_fence_get(f); 722 dma_fence_put(f); 723 724 return 0; 725 726 err_free: 727 amdgpu_job_free(job); 728 err: 729 amdgpu_ib_free(adev, ib_msg, f); 730 return r; 731 } 732 733 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 734 { 735 struct dma_fence *fence = NULL; 736 struct amdgpu_ib ib; 737 long r; 738 739 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 740 if (r) 741 goto error; 742 743 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 744 if (r) 745 goto error; 746 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 747 if (r) 748 goto error; 749 750 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 751 if (r) 752 goto error; 753 754 r = dma_fence_wait_timeout(fence, false, timeout); 755 if (r == 0) 756 r = -ETIMEDOUT; 757 else if (r > 0) 758 r = 0; 759 760 dma_fence_put(fence); 761 error: 762 return r; 763 } 764 765 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 766 { 767 struct amdgpu_device *adev = ring->adev; 768 uint32_t rptr; 769 unsigned i; 770 int r; 771 772 if (amdgpu_sriov_vf(adev)) 773 return 0; 774 775 r = amdgpu_ring_alloc(ring, 16); 776 if (r) 777 return r; 778 779 rptr = amdgpu_ring_get_rptr(ring); 780 781 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 782 amdgpu_ring_commit(ring); 783 784 for (i = 0; i < adev->usec_timeout; i++) { 785 if (amdgpu_ring_get_rptr(ring) != rptr) 786 break; 787 udelay(1); 788 } 789 790 if (i >= adev->usec_timeout) 791 r = -ETIMEDOUT; 792 793 return r; 794 } 795 796 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 797 struct amdgpu_ib *ib_msg, 798 struct dma_fence **fence) 799 { 800 const unsigned ib_size_dw = 16; 801 struct amdgpu_job *job; 802 struct amdgpu_ib *ib; 803 struct dma_fence *f = NULL; 804 uint64_t addr; 805 int i, r; 806 807 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 808 AMDGPU_IB_POOL_DIRECT, &job); 809 if (r) 810 return r; 811 812 ib = &job->ibs[0]; 813 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 814 815 ib->length_dw = 0; 816 ib->ptr[ib->length_dw++] = 0x00000018; 817 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 818 ib->ptr[ib->length_dw++] = handle; 819 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 820 ib->ptr[ib->length_dw++] = addr; 821 ib->ptr[ib->length_dw++] = 0x0000000b; 822 823 ib->ptr[ib->length_dw++] = 0x00000014; 824 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 825 ib->ptr[ib->length_dw++] = 0x0000001c; 826 ib->ptr[ib->length_dw++] = 0x00000000; 827 ib->ptr[ib->length_dw++] = 0x00000000; 828 829 ib->ptr[ib->length_dw++] = 0x00000008; 830 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 831 832 for (i = ib->length_dw; i < ib_size_dw; ++i) 833 ib->ptr[i] = 0x0; 834 835 r = amdgpu_job_submit_direct(job, ring, &f); 836 if (r) 837 goto err; 838 839 if (fence) 840 *fence = dma_fence_get(f); 841 dma_fence_put(f); 842 843 return 0; 844 845 err: 846 amdgpu_job_free(job); 847 return r; 848 } 849 850 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 851 struct amdgpu_ib *ib_msg, 852 struct dma_fence **fence) 853 { 854 const unsigned ib_size_dw = 16; 855 struct amdgpu_job *job; 856 struct amdgpu_ib *ib; 857 struct dma_fence *f = NULL; 858 uint64_t addr; 859 int i, r; 860 861 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 862 AMDGPU_IB_POOL_DIRECT, &job); 863 if (r) 864 return r; 865 866 ib = &job->ibs[0]; 867 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 868 869 ib->length_dw = 0; 870 ib->ptr[ib->length_dw++] = 0x00000018; 871 ib->ptr[ib->length_dw++] = 0x00000001; 872 ib->ptr[ib->length_dw++] = handle; 873 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 874 ib->ptr[ib->length_dw++] = addr; 875 ib->ptr[ib->length_dw++] = 0x0000000b; 876 877 ib->ptr[ib->length_dw++] = 0x00000014; 878 ib->ptr[ib->length_dw++] = 0x00000002; 879 ib->ptr[ib->length_dw++] = 0x0000001c; 880 ib->ptr[ib->length_dw++] = 0x00000000; 881 ib->ptr[ib->length_dw++] = 0x00000000; 882 883 ib->ptr[ib->length_dw++] = 0x00000008; 884 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 885 886 for (i = ib->length_dw; i < ib_size_dw; ++i) 887 ib->ptr[i] = 0x0; 888 889 r = amdgpu_job_submit_direct(job, ring, &f); 890 if (r) 891 goto err; 892 893 if (fence) 894 *fence = dma_fence_get(f); 895 dma_fence_put(f); 896 897 return 0; 898 899 err: 900 amdgpu_job_free(job); 901 return r; 902 } 903 904 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 905 { 906 struct amdgpu_device *adev = ring->adev; 907 struct dma_fence *fence = NULL; 908 struct amdgpu_ib ib; 909 long r; 910 911 memset(&ib, 0, sizeof(ib)); 912 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 913 AMDGPU_IB_POOL_DIRECT, 914 &ib); 915 if (r) 916 return r; 917 918 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 919 if (r) 920 goto error; 921 922 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 923 if (r) 924 goto error; 925 926 r = dma_fence_wait_timeout(fence, false, timeout); 927 if (r == 0) 928 r = -ETIMEDOUT; 929 else if (r > 0) 930 r = 0; 931 932 error: 933 amdgpu_ib_free(adev, &ib, fence); 934 dma_fence_put(fence); 935 936 return r; 937 } 938 939 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 940 { 941 switch(ring) { 942 case 0: 943 return AMDGPU_RING_PRIO_0; 944 case 1: 945 return AMDGPU_RING_PRIO_1; 946 case 2: 947 return AMDGPU_RING_PRIO_2; 948 default: 949 return AMDGPU_RING_PRIO_0; 950 } 951 } 952 953 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev) 954 { 955 int i; 956 unsigned int idx; 957 958 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 959 const struct common_firmware_header *hdr; 960 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 961 962 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 963 if (adev->vcn.harvest_config & (1 << i)) 964 continue; 965 /* currently only support 2 FW instances */ 966 if (i >= 2) { 967 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 968 break; 969 } 970 idx = AMDGPU_UCODE_ID_VCN + i; 971 adev->firmware.ucode[idx].ucode_id = idx; 972 adev->firmware.ucode[idx].fw = adev->vcn.fw; 973 adev->firmware.fw_size += 974 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 975 } 976 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 977 } 978 } 979