1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <drm/drmP.h> 30 #include <drm/drm.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_pm.h" 34 #include "amdgpu_vcn.h" 35 #include "soc15d.h" 36 #include "soc15_common.h" 37 38 #include "vcn/vcn_1_0_offset.h" 39 #include "vcn/vcn_1_0_sh_mask.h" 40 41 /* 1 second timeout */ 42 #define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000) 43 44 /* Firmware Names */ 45 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 46 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 47 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 48 49 MODULE_FIRMWARE(FIRMWARE_RAVEN); 50 MODULE_FIRMWARE(FIRMWARE_PICASSO); 51 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 52 53 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 54 55 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 56 { 57 unsigned long bo_size; 58 const char *fw_name; 59 const struct common_firmware_header *hdr; 60 unsigned char fw_check; 61 int r; 62 63 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 64 65 switch (adev->asic_type) { 66 case CHIP_RAVEN: 67 if (adev->rev_id >= 8) 68 fw_name = FIRMWARE_RAVEN2; 69 else if (adev->pdev->device == 0x15d8) 70 fw_name = FIRMWARE_PICASSO; 71 else 72 fw_name = FIRMWARE_RAVEN; 73 break; 74 default: 75 return -EINVAL; 76 } 77 78 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); 79 if (r) { 80 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", 81 fw_name); 82 return r; 83 } 84 85 r = amdgpu_ucode_validate(adev->vcn.fw); 86 if (r) { 87 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", 88 fw_name); 89 release_firmware(adev->vcn.fw); 90 adev->vcn.fw = NULL; 91 return r; 92 } 93 94 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 95 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 96 97 /* Bit 20-23, it is encode major and non-zero for new naming convention. 98 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 99 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 100 * is zero in old naming convention, this field is always zero so far. 101 * These four bits are used to tell which naming convention is present. 102 */ 103 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 104 if (fw_check) { 105 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 106 107 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 108 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 109 enc_major = fw_check; 110 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 111 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 112 DRM_INFO("Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n", 113 enc_major, enc_minor, dec_ver, vep, fw_rev); 114 } else { 115 unsigned int version_major, version_minor, family_id; 116 117 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 118 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 119 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 120 DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n", 121 version_major, version_minor, family_id); 122 } 123 124 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 125 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 126 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 127 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 128 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo, 129 &adev->vcn.gpu_addr, &adev->vcn.cpu_addr); 130 if (r) { 131 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 132 return r; 133 } 134 135 return 0; 136 } 137 138 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 139 { 140 int i; 141 142 kvfree(adev->vcn.saved_bo); 143 144 amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo, 145 &adev->vcn.gpu_addr, 146 (void **)&adev->vcn.cpu_addr); 147 148 amdgpu_ring_fini(&adev->vcn.ring_dec); 149 150 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 151 amdgpu_ring_fini(&adev->vcn.ring_enc[i]); 152 153 amdgpu_ring_fini(&adev->vcn.ring_jpeg); 154 155 release_firmware(adev->vcn.fw); 156 157 return 0; 158 } 159 160 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 161 { 162 unsigned size; 163 void *ptr; 164 165 cancel_delayed_work_sync(&adev->vcn.idle_work); 166 167 if (adev->vcn.vcpu_bo == NULL) 168 return 0; 169 170 size = amdgpu_bo_size(adev->vcn.vcpu_bo); 171 ptr = adev->vcn.cpu_addr; 172 173 adev->vcn.saved_bo = kvmalloc(size, GFP_KERNEL); 174 if (!adev->vcn.saved_bo) 175 return -ENOMEM; 176 177 memcpy_fromio(adev->vcn.saved_bo, ptr, size); 178 179 return 0; 180 } 181 182 int amdgpu_vcn_resume(struct amdgpu_device *adev) 183 { 184 unsigned size; 185 void *ptr; 186 187 if (adev->vcn.vcpu_bo == NULL) 188 return -EINVAL; 189 190 size = amdgpu_bo_size(adev->vcn.vcpu_bo); 191 ptr = adev->vcn.cpu_addr; 192 193 if (adev->vcn.saved_bo != NULL) { 194 memcpy_toio(ptr, adev->vcn.saved_bo, size); 195 kvfree(adev->vcn.saved_bo); 196 adev->vcn.saved_bo = NULL; 197 } else { 198 const struct common_firmware_header *hdr; 199 unsigned offset; 200 201 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 202 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 203 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 204 memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset, 205 le32_to_cpu(hdr->ucode_size_bytes)); 206 size -= le32_to_cpu(hdr->ucode_size_bytes); 207 ptr += le32_to_cpu(hdr->ucode_size_bytes); 208 } 209 memset_io(ptr, 0, size); 210 } 211 212 return 0; 213 } 214 215 static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev, 216 struct dpg_pause_state *new_state) 217 { 218 int ret_code; 219 uint32_t reg_data = 0; 220 uint32_t reg_data2 = 0; 221 struct amdgpu_ring *ring; 222 223 /* pause/unpause if state is changed */ 224 if (adev->vcn.pause_state.fw_based != new_state->fw_based) { 225 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 226 adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, 227 new_state->fw_based, new_state->jpeg); 228 229 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 230 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 231 232 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 233 ret_code = 0; 234 235 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) 236 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 237 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 238 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 239 240 if (!ret_code) { 241 /* pause DPG non-jpeg */ 242 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 243 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 244 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 245 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 246 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); 247 248 /* Restore */ 249 ring = &adev->vcn.ring_enc[0]; 250 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 251 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 252 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 253 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 254 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 255 256 ring = &adev->vcn.ring_enc[1]; 257 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 258 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 259 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 260 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 261 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 262 263 ring = &adev->vcn.ring_dec; 264 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 265 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2)); 266 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 267 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 268 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 269 } 270 } else { 271 /* unpause dpg non-jpeg, no need to wait */ 272 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 273 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 274 } 275 adev->vcn.pause_state.fw_based = new_state->fw_based; 276 } 277 278 /* pause/unpause if state is changed */ 279 if (adev->vcn.pause_state.jpeg != new_state->jpeg) { 280 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 281 adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, 282 new_state->fw_based, new_state->jpeg); 283 284 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 285 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); 286 287 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { 288 ret_code = 0; 289 290 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) 291 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 292 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 293 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 294 295 if (!ret_code) { 296 /* Make sure JPRG Snoop is disabled before sending the pause */ 297 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 298 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; 299 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); 300 301 /* pause DPG jpeg */ 302 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 303 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 304 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 305 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, 306 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code); 307 308 /* Restore */ 309 ring = &adev->vcn.ring_jpeg; 310 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 311 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 312 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | 313 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 314 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 315 lower_32_bits(ring->gpu_addr)); 316 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 317 upper_32_bits(ring->gpu_addr)); 318 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); 319 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); 320 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 321 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 322 323 ring = &adev->vcn.ring_dec; 324 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 325 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2)); 326 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 327 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 328 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 329 } 330 } else { 331 /* unpause dpg jpeg, no need to wait */ 332 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 333 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 334 } 335 adev->vcn.pause_state.jpeg = new_state->jpeg; 336 } 337 338 return 0; 339 } 340 341 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 342 { 343 struct amdgpu_device *adev = 344 container_of(work, struct amdgpu_device, vcn.idle_work.work); 345 unsigned int fences = 0; 346 unsigned int i; 347 348 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 349 fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]); 350 } 351 352 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 353 struct dpg_pause_state new_state; 354 355 if (fences) 356 new_state.fw_based = VCN_DPG_STATE__PAUSE; 357 else 358 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 359 360 if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg)) 361 new_state.jpeg = VCN_DPG_STATE__PAUSE; 362 else 363 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 364 365 amdgpu_vcn_pause_dpg_mode(adev, &new_state); 366 } 367 368 fences += amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg); 369 fences += amdgpu_fence_count_emitted(&adev->vcn.ring_dec); 370 371 if (fences == 0) { 372 amdgpu_gfx_off_ctrl(adev, true); 373 if (adev->pm.dpm_enabled) 374 amdgpu_dpm_enable_uvd(adev, false); 375 else 376 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 377 AMD_PG_STATE_GATE); 378 } else { 379 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 380 } 381 } 382 383 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 384 { 385 struct amdgpu_device *adev = ring->adev; 386 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); 387 388 if (set_clocks) { 389 amdgpu_gfx_off_ctrl(adev, false); 390 if (adev->pm.dpm_enabled) 391 amdgpu_dpm_enable_uvd(adev, true); 392 else 393 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 394 AMD_PG_STATE_UNGATE); 395 } 396 397 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 398 struct dpg_pause_state new_state; 399 400 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 401 new_state.fw_based = VCN_DPG_STATE__PAUSE; 402 else 403 new_state.fw_based = adev->vcn.pause_state.fw_based; 404 405 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 406 new_state.jpeg = VCN_DPG_STATE__PAUSE; 407 else 408 new_state.jpeg = adev->vcn.pause_state.jpeg; 409 410 amdgpu_vcn_pause_dpg_mode(adev, &new_state); 411 } 412 } 413 414 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 415 { 416 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 417 } 418 419 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 420 { 421 struct amdgpu_device *adev = ring->adev; 422 uint32_t tmp = 0; 423 unsigned i; 424 int r; 425 426 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0xCAFEDEAD); 427 r = amdgpu_ring_alloc(ring, 3); 428 if (r) 429 return r; 430 431 amdgpu_ring_write(ring, 432 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0)); 433 amdgpu_ring_write(ring, 0xDEADBEEF); 434 amdgpu_ring_commit(ring); 435 for (i = 0; i < adev->usec_timeout; i++) { 436 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9)); 437 if (tmp == 0xDEADBEEF) 438 break; 439 DRM_UDELAY(1); 440 } 441 442 if (i >= adev->usec_timeout) 443 r = -ETIMEDOUT; 444 445 return r; 446 } 447 448 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 449 struct amdgpu_bo *bo, 450 struct dma_fence **fence) 451 { 452 struct amdgpu_device *adev = ring->adev; 453 struct dma_fence *f = NULL; 454 struct amdgpu_job *job; 455 struct amdgpu_ib *ib; 456 uint64_t addr; 457 int i, r; 458 459 r = amdgpu_job_alloc_with_ib(adev, 64, &job); 460 if (r) 461 goto err; 462 463 ib = &job->ibs[0]; 464 addr = amdgpu_bo_gpu_offset(bo); 465 ib->ptr[0] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0); 466 ib->ptr[1] = addr; 467 ib->ptr[2] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0); 468 ib->ptr[3] = addr >> 32; 469 ib->ptr[4] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0); 470 ib->ptr[5] = 0; 471 for (i = 6; i < 16; i += 2) { 472 ib->ptr[i] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0); 473 ib->ptr[i+1] = 0; 474 } 475 ib->length_dw = 16; 476 477 r = amdgpu_job_submit_direct(job, ring, &f); 478 if (r) 479 goto err_free; 480 481 amdgpu_bo_fence(bo, f, false); 482 amdgpu_bo_unreserve(bo); 483 amdgpu_bo_unref(&bo); 484 485 if (fence) 486 *fence = dma_fence_get(f); 487 dma_fence_put(f); 488 489 return 0; 490 491 err_free: 492 amdgpu_job_free(job); 493 494 err: 495 amdgpu_bo_unreserve(bo); 496 amdgpu_bo_unref(&bo); 497 return r; 498 } 499 500 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 501 struct dma_fence **fence) 502 { 503 struct amdgpu_device *adev = ring->adev; 504 struct amdgpu_bo *bo = NULL; 505 uint32_t *msg; 506 int r, i; 507 508 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 509 AMDGPU_GEM_DOMAIN_VRAM, 510 &bo, NULL, (void **)&msg); 511 if (r) 512 return r; 513 514 msg[0] = cpu_to_le32(0x00000028); 515 msg[1] = cpu_to_le32(0x00000038); 516 msg[2] = cpu_to_le32(0x00000001); 517 msg[3] = cpu_to_le32(0x00000000); 518 msg[4] = cpu_to_le32(handle); 519 msg[5] = cpu_to_le32(0x00000000); 520 msg[6] = cpu_to_le32(0x00000001); 521 msg[7] = cpu_to_le32(0x00000028); 522 msg[8] = cpu_to_le32(0x00000010); 523 msg[9] = cpu_to_le32(0x00000000); 524 msg[10] = cpu_to_le32(0x00000007); 525 msg[11] = cpu_to_le32(0x00000000); 526 msg[12] = cpu_to_le32(0x00000780); 527 msg[13] = cpu_to_le32(0x00000440); 528 for (i = 14; i < 1024; ++i) 529 msg[i] = cpu_to_le32(0x0); 530 531 return amdgpu_vcn_dec_send_msg(ring, bo, fence); 532 } 533 534 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 535 struct dma_fence **fence) 536 { 537 struct amdgpu_device *adev = ring->adev; 538 struct amdgpu_bo *bo = NULL; 539 uint32_t *msg; 540 int r, i; 541 542 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 543 AMDGPU_GEM_DOMAIN_VRAM, 544 &bo, NULL, (void **)&msg); 545 if (r) 546 return r; 547 548 msg[0] = cpu_to_le32(0x00000028); 549 msg[1] = cpu_to_le32(0x00000018); 550 msg[2] = cpu_to_le32(0x00000000); 551 msg[3] = cpu_to_le32(0x00000002); 552 msg[4] = cpu_to_le32(handle); 553 msg[5] = cpu_to_le32(0x00000000); 554 for (i = 6; i < 1024; ++i) 555 msg[i] = cpu_to_le32(0x0); 556 557 return amdgpu_vcn_dec_send_msg(ring, bo, fence); 558 } 559 560 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 561 { 562 struct dma_fence *fence; 563 long r; 564 565 r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL); 566 if (r) 567 goto error; 568 569 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence); 570 if (r) 571 goto error; 572 573 r = dma_fence_wait_timeout(fence, false, timeout); 574 if (r == 0) 575 r = -ETIMEDOUT; 576 else if (r > 0) 577 r = 0; 578 579 dma_fence_put(fence); 580 error: 581 return r; 582 } 583 584 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 585 { 586 struct amdgpu_device *adev = ring->adev; 587 uint32_t rptr = amdgpu_ring_get_rptr(ring); 588 unsigned i; 589 int r; 590 591 r = amdgpu_ring_alloc(ring, 16); 592 if (r) 593 return r; 594 595 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 596 amdgpu_ring_commit(ring); 597 598 for (i = 0; i < adev->usec_timeout; i++) { 599 if (amdgpu_ring_get_rptr(ring) != rptr) 600 break; 601 DRM_UDELAY(1); 602 } 603 604 if (i >= adev->usec_timeout) 605 r = -ETIMEDOUT; 606 607 return r; 608 } 609 610 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 611 struct dma_fence **fence) 612 { 613 const unsigned ib_size_dw = 16; 614 struct amdgpu_job *job; 615 struct amdgpu_ib *ib; 616 struct dma_fence *f = NULL; 617 uint64_t dummy; 618 int i, r; 619 620 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 621 if (r) 622 return r; 623 624 ib = &job->ibs[0]; 625 dummy = ib->gpu_addr + 1024; 626 627 ib->length_dw = 0; 628 ib->ptr[ib->length_dw++] = 0x00000018; 629 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 630 ib->ptr[ib->length_dw++] = handle; 631 ib->ptr[ib->length_dw++] = upper_32_bits(dummy); 632 ib->ptr[ib->length_dw++] = dummy; 633 ib->ptr[ib->length_dw++] = 0x0000000b; 634 635 ib->ptr[ib->length_dw++] = 0x00000014; 636 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 637 ib->ptr[ib->length_dw++] = 0x0000001c; 638 ib->ptr[ib->length_dw++] = 0x00000000; 639 ib->ptr[ib->length_dw++] = 0x00000000; 640 641 ib->ptr[ib->length_dw++] = 0x00000008; 642 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 643 644 for (i = ib->length_dw; i < ib_size_dw; ++i) 645 ib->ptr[i] = 0x0; 646 647 r = amdgpu_job_submit_direct(job, ring, &f); 648 if (r) 649 goto err; 650 651 if (fence) 652 *fence = dma_fence_get(f); 653 dma_fence_put(f); 654 655 return 0; 656 657 err: 658 amdgpu_job_free(job); 659 return r; 660 } 661 662 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 663 struct dma_fence **fence) 664 { 665 const unsigned ib_size_dw = 16; 666 struct amdgpu_job *job; 667 struct amdgpu_ib *ib; 668 struct dma_fence *f = NULL; 669 uint64_t dummy; 670 int i, r; 671 672 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 673 if (r) 674 return r; 675 676 ib = &job->ibs[0]; 677 dummy = ib->gpu_addr + 1024; 678 679 ib->length_dw = 0; 680 ib->ptr[ib->length_dw++] = 0x00000018; 681 ib->ptr[ib->length_dw++] = 0x00000001; 682 ib->ptr[ib->length_dw++] = handle; 683 ib->ptr[ib->length_dw++] = upper_32_bits(dummy); 684 ib->ptr[ib->length_dw++] = dummy; 685 ib->ptr[ib->length_dw++] = 0x0000000b; 686 687 ib->ptr[ib->length_dw++] = 0x00000014; 688 ib->ptr[ib->length_dw++] = 0x00000002; 689 ib->ptr[ib->length_dw++] = 0x0000001c; 690 ib->ptr[ib->length_dw++] = 0x00000000; 691 ib->ptr[ib->length_dw++] = 0x00000000; 692 693 ib->ptr[ib->length_dw++] = 0x00000008; 694 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 695 696 for (i = ib->length_dw; i < ib_size_dw; ++i) 697 ib->ptr[i] = 0x0; 698 699 r = amdgpu_job_submit_direct(job, ring, &f); 700 if (r) 701 goto err; 702 703 if (fence) 704 *fence = dma_fence_get(f); 705 dma_fence_put(f); 706 707 return 0; 708 709 err: 710 amdgpu_job_free(job); 711 return r; 712 } 713 714 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 715 { 716 struct dma_fence *fence = NULL; 717 long r; 718 719 r = amdgpu_vcn_enc_get_create_msg(ring, 1, NULL); 720 if (r) 721 goto error; 722 723 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &fence); 724 if (r) 725 goto error; 726 727 r = dma_fence_wait_timeout(fence, false, timeout); 728 if (r == 0) 729 r = -ETIMEDOUT; 730 else if (r > 0) 731 r = 0; 732 733 error: 734 dma_fence_put(fence); 735 return r; 736 } 737 738 int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring) 739 { 740 struct amdgpu_device *adev = ring->adev; 741 uint32_t tmp = 0; 742 unsigned i; 743 int r; 744 745 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0xCAFEDEAD); 746 r = amdgpu_ring_alloc(ring, 3); 747 748 if (r) 749 return r; 750 751 amdgpu_ring_write(ring, 752 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0, 0, 0)); 753 amdgpu_ring_write(ring, 0xDEADBEEF); 754 amdgpu_ring_commit(ring); 755 756 for (i = 0; i < adev->usec_timeout; i++) { 757 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9)); 758 if (tmp == 0xDEADBEEF) 759 break; 760 DRM_UDELAY(1); 761 } 762 763 if (i >= adev->usec_timeout) 764 r = -ETIMEDOUT; 765 766 return r; 767 } 768 769 static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle, 770 struct dma_fence **fence) 771 { 772 struct amdgpu_device *adev = ring->adev; 773 struct amdgpu_job *job; 774 struct amdgpu_ib *ib; 775 struct dma_fence *f = NULL; 776 const unsigned ib_size_dw = 16; 777 int i, r; 778 779 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 780 if (r) 781 return r; 782 783 ib = &job->ibs[0]; 784 785 ib->ptr[0] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0, 0, PACKETJ_TYPE0); 786 ib->ptr[1] = 0xDEADBEEF; 787 for (i = 2; i < 16; i += 2) { 788 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6); 789 ib->ptr[i+1] = 0; 790 } 791 ib->length_dw = 16; 792 793 r = amdgpu_job_submit_direct(job, ring, &f); 794 if (r) 795 goto err; 796 797 if (fence) 798 *fence = dma_fence_get(f); 799 dma_fence_put(f); 800 801 return 0; 802 803 err: 804 amdgpu_job_free(job); 805 return r; 806 } 807 808 int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout) 809 { 810 struct amdgpu_device *adev = ring->adev; 811 uint32_t tmp = 0; 812 unsigned i; 813 struct dma_fence *fence = NULL; 814 long r = 0; 815 816 r = amdgpu_vcn_jpeg_set_reg(ring, 1, &fence); 817 if (r) 818 goto error; 819 820 r = dma_fence_wait_timeout(fence, false, timeout); 821 if (r == 0) { 822 r = -ETIMEDOUT; 823 goto error; 824 } else if (r < 0) { 825 goto error; 826 } else { 827 r = 0; 828 } 829 830 for (i = 0; i < adev->usec_timeout; i++) { 831 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9)); 832 if (tmp == 0xDEADBEEF) 833 break; 834 DRM_UDELAY(1); 835 } 836 837 if (i >= adev->usec_timeout) 838 r = -ETIMEDOUT; 839 840 dma_fence_put(fence); 841 error: 842 return r; 843 } 844