1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <drm/drm_drv.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_pm.h" 34 #include "amdgpu_vcn.h" 35 #include "soc15d.h" 36 37 /* Firmware Names */ 38 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 39 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 40 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 41 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 42 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 43 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 44 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 45 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 46 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 47 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 48 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 49 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 50 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 51 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 52 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 53 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 54 55 MODULE_FIRMWARE(FIRMWARE_RAVEN); 56 MODULE_FIRMWARE(FIRMWARE_PICASSO); 57 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 58 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 59 MODULE_FIRMWARE(FIRMWARE_RENOIR); 60 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 61 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 62 MODULE_FIRMWARE(FIRMWARE_NAVI10); 63 MODULE_FIRMWARE(FIRMWARE_NAVI14); 64 MODULE_FIRMWARE(FIRMWARE_NAVI12); 65 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 66 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 67 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 68 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 69 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 70 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 71 72 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 73 74 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 75 { 76 unsigned long bo_size; 77 const char *fw_name; 78 const struct common_firmware_header *hdr; 79 unsigned char fw_check; 80 int i, r; 81 82 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 83 mutex_init(&adev->vcn.vcn_pg_lock); 84 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 85 atomic_set(&adev->vcn.total_submission_cnt, 0); 86 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 87 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 88 89 switch (adev->asic_type) { 90 case CHIP_RAVEN: 91 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 92 fw_name = FIRMWARE_RAVEN2; 93 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 94 fw_name = FIRMWARE_PICASSO; 95 else 96 fw_name = FIRMWARE_RAVEN; 97 break; 98 case CHIP_ARCTURUS: 99 fw_name = FIRMWARE_ARCTURUS; 100 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 101 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 102 adev->vcn.indirect_sram = true; 103 break; 104 case CHIP_RENOIR: 105 if (adev->apu_flags & AMD_APU_IS_RENOIR) 106 fw_name = FIRMWARE_RENOIR; 107 else 108 fw_name = FIRMWARE_GREEN_SARDINE; 109 110 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 111 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 112 adev->vcn.indirect_sram = true; 113 break; 114 case CHIP_ALDEBARAN: 115 fw_name = FIRMWARE_ALDEBARAN; 116 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 117 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 118 adev->vcn.indirect_sram = true; 119 break; 120 case CHIP_NAVI10: 121 fw_name = FIRMWARE_NAVI10; 122 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 123 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 124 adev->vcn.indirect_sram = true; 125 break; 126 case CHIP_NAVI14: 127 fw_name = FIRMWARE_NAVI14; 128 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 129 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 130 adev->vcn.indirect_sram = true; 131 break; 132 case CHIP_NAVI12: 133 fw_name = FIRMWARE_NAVI12; 134 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 135 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 136 adev->vcn.indirect_sram = true; 137 break; 138 case CHIP_SIENNA_CICHLID: 139 fw_name = FIRMWARE_SIENNA_CICHLID; 140 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 141 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 142 adev->vcn.indirect_sram = true; 143 break; 144 case CHIP_NAVY_FLOUNDER: 145 fw_name = FIRMWARE_NAVY_FLOUNDER; 146 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 147 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 148 adev->vcn.indirect_sram = true; 149 break; 150 case CHIP_VANGOGH: 151 fw_name = FIRMWARE_VANGOGH; 152 break; 153 case CHIP_DIMGREY_CAVEFISH: 154 fw_name = FIRMWARE_DIMGREY_CAVEFISH; 155 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 156 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 157 adev->vcn.indirect_sram = true; 158 break; 159 case CHIP_BEIGE_GOBY: 160 fw_name = FIRMWARE_BEIGE_GOBY; 161 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 162 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 163 adev->vcn.indirect_sram = true; 164 break; 165 case CHIP_YELLOW_CARP: 166 fw_name = FIRMWARE_YELLOW_CARP; 167 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 168 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 169 adev->vcn.indirect_sram = true; 170 break; 171 default: 172 return -EINVAL; 173 } 174 175 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); 176 if (r) { 177 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", 178 fw_name); 179 return r; 180 } 181 182 r = amdgpu_ucode_validate(adev->vcn.fw); 183 if (r) { 184 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", 185 fw_name); 186 release_firmware(adev->vcn.fw); 187 adev->vcn.fw = NULL; 188 return r; 189 } 190 191 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 192 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 193 194 /* Bit 20-23, it is encode major and non-zero for new naming convention. 195 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 196 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 197 * is zero in old naming convention, this field is always zero so far. 198 * These four bits are used to tell which naming convention is present. 199 */ 200 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 201 if (fw_check) { 202 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 203 204 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 205 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 206 enc_major = fw_check; 207 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 208 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 209 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 210 enc_major, enc_minor, dec_ver, vep, fw_rev); 211 } else { 212 unsigned int version_major, version_minor, family_id; 213 214 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 215 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 216 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 217 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 218 version_major, version_minor, family_id); 219 } 220 221 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 222 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 223 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 224 bo_size += AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 225 226 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 227 if (adev->vcn.harvest_config & (1 << i)) 228 continue; 229 230 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 231 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo, 232 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr); 233 if (r) { 234 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 235 return r; 236 } 237 238 adev->vcn.inst[i].fw_shared_cpu_addr = adev->vcn.inst[i].cpu_addr + 239 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 240 adev->vcn.inst[i].fw_shared_gpu_addr = adev->vcn.inst[i].gpu_addr + 241 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 242 243 if (adev->vcn.indirect_sram) { 244 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 245 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo, 246 &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr); 247 if (r) { 248 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 249 return r; 250 } 251 } 252 } 253 254 return 0; 255 } 256 257 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 258 { 259 int i, j; 260 261 cancel_delayed_work_sync(&adev->vcn.idle_work); 262 263 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 264 if (adev->vcn.harvest_config & (1 << j)) 265 continue; 266 267 if (adev->vcn.indirect_sram) { 268 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo, 269 &adev->vcn.inst[j].dpg_sram_gpu_addr, 270 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 271 } 272 kvfree(adev->vcn.inst[j].saved_bo); 273 274 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 275 &adev->vcn.inst[j].gpu_addr, 276 (void **)&adev->vcn.inst[j].cpu_addr); 277 278 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 279 280 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 281 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 282 } 283 284 release_firmware(adev->vcn.fw); 285 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 286 mutex_destroy(&adev->vcn.vcn_pg_lock); 287 288 return 0; 289 } 290 291 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 292 { 293 unsigned size; 294 void *ptr; 295 int i, idx; 296 297 cancel_delayed_work_sync(&adev->vcn.idle_work); 298 299 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 300 if (adev->vcn.harvest_config & (1 << i)) 301 continue; 302 if (adev->vcn.inst[i].vcpu_bo == NULL) 303 return 0; 304 305 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 306 ptr = adev->vcn.inst[i].cpu_addr; 307 308 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 309 if (!adev->vcn.inst[i].saved_bo) 310 return -ENOMEM; 311 312 if (drm_dev_enter(&adev->ddev, &idx)) { 313 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 314 drm_dev_exit(idx); 315 } 316 } 317 return 0; 318 } 319 320 int amdgpu_vcn_resume(struct amdgpu_device *adev) 321 { 322 unsigned size; 323 void *ptr; 324 int i, idx; 325 326 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 327 if (adev->vcn.harvest_config & (1 << i)) 328 continue; 329 if (adev->vcn.inst[i].vcpu_bo == NULL) 330 return -EINVAL; 331 332 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 333 ptr = adev->vcn.inst[i].cpu_addr; 334 335 if (adev->vcn.inst[i].saved_bo != NULL) { 336 if (drm_dev_enter(&adev->ddev, &idx)) { 337 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 338 drm_dev_exit(idx); 339 } 340 kvfree(adev->vcn.inst[i].saved_bo); 341 adev->vcn.inst[i].saved_bo = NULL; 342 } else { 343 const struct common_firmware_header *hdr; 344 unsigned offset; 345 346 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 347 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 348 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 349 if (drm_dev_enter(&adev->ddev, &idx)) { 350 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 351 le32_to_cpu(hdr->ucode_size_bytes)); 352 drm_dev_exit(idx); 353 } 354 size -= le32_to_cpu(hdr->ucode_size_bytes); 355 ptr += le32_to_cpu(hdr->ucode_size_bytes); 356 } 357 memset_io(ptr, 0, size); 358 } 359 } 360 return 0; 361 } 362 363 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 364 { 365 struct amdgpu_device *adev = 366 container_of(work, struct amdgpu_device, vcn.idle_work.work); 367 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 368 unsigned int i, j; 369 int r = 0; 370 371 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 372 if (adev->vcn.harvest_config & (1 << j)) 373 continue; 374 375 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 376 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 377 } 378 379 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 380 struct dpg_pause_state new_state; 381 382 if (fence[j] || 383 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 384 new_state.fw_based = VCN_DPG_STATE__PAUSE; 385 else 386 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 387 388 adev->vcn.pause_dpg_mode(adev, j, &new_state); 389 } 390 391 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 392 fences += fence[j]; 393 } 394 395 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 396 amdgpu_gfx_off_ctrl(adev, true); 397 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 398 AMD_PG_STATE_GATE); 399 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 400 false); 401 if (r) 402 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 403 } else { 404 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 405 } 406 } 407 408 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 409 { 410 struct amdgpu_device *adev = ring->adev; 411 int r = 0; 412 413 atomic_inc(&adev->vcn.total_submission_cnt); 414 415 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 416 amdgpu_gfx_off_ctrl(adev, false); 417 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 418 true); 419 if (r) 420 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 421 } 422 423 mutex_lock(&adev->vcn.vcn_pg_lock); 424 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 425 AMD_PG_STATE_UNGATE); 426 427 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 428 struct dpg_pause_state new_state; 429 430 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 431 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 432 new_state.fw_based = VCN_DPG_STATE__PAUSE; 433 } else { 434 unsigned int fences = 0; 435 unsigned int i; 436 437 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 438 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 439 440 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 441 new_state.fw_based = VCN_DPG_STATE__PAUSE; 442 else 443 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 444 } 445 446 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 447 } 448 mutex_unlock(&adev->vcn.vcn_pg_lock); 449 } 450 451 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 452 { 453 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 454 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 455 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 456 457 atomic_dec(&ring->adev->vcn.total_submission_cnt); 458 459 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 460 } 461 462 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 463 { 464 struct amdgpu_device *adev = ring->adev; 465 uint32_t tmp = 0; 466 unsigned i; 467 int r; 468 469 /* VCN in SRIOV does not support direct register read/write */ 470 if (amdgpu_sriov_vf(adev)) 471 return 0; 472 473 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 474 r = amdgpu_ring_alloc(ring, 3); 475 if (r) 476 return r; 477 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 478 amdgpu_ring_write(ring, 0xDEADBEEF); 479 amdgpu_ring_commit(ring); 480 for (i = 0; i < adev->usec_timeout; i++) { 481 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 482 if (tmp == 0xDEADBEEF) 483 break; 484 udelay(1); 485 } 486 487 if (i >= adev->usec_timeout) 488 r = -ETIMEDOUT; 489 490 return r; 491 } 492 493 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 494 { 495 struct amdgpu_device *adev = ring->adev; 496 uint32_t rptr; 497 unsigned int i; 498 int r; 499 500 if (amdgpu_sriov_vf(adev)) 501 return 0; 502 503 r = amdgpu_ring_alloc(ring, 16); 504 if (r) 505 return r; 506 507 rptr = amdgpu_ring_get_rptr(ring); 508 509 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 510 amdgpu_ring_commit(ring); 511 512 for (i = 0; i < adev->usec_timeout; i++) { 513 if (amdgpu_ring_get_rptr(ring) != rptr) 514 break; 515 udelay(1); 516 } 517 518 if (i >= adev->usec_timeout) 519 r = -ETIMEDOUT; 520 521 return r; 522 } 523 524 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 525 struct amdgpu_bo *bo, 526 struct dma_fence **fence) 527 { 528 struct amdgpu_device *adev = ring->adev; 529 struct dma_fence *f = NULL; 530 struct amdgpu_job *job; 531 struct amdgpu_ib *ib; 532 uint64_t addr; 533 void *msg = NULL; 534 int i, r; 535 536 r = amdgpu_job_alloc_with_ib(adev, 64, 537 AMDGPU_IB_POOL_DIRECT, &job); 538 if (r) 539 goto err; 540 541 ib = &job->ibs[0]; 542 addr = amdgpu_bo_gpu_offset(bo); 543 msg = amdgpu_bo_kptr(bo); 544 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 545 ib->ptr[1] = addr; 546 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 547 ib->ptr[3] = addr >> 32; 548 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 549 ib->ptr[5] = 0; 550 for (i = 6; i < 16; i += 2) { 551 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 552 ib->ptr[i+1] = 0; 553 } 554 ib->length_dw = 16; 555 556 r = amdgpu_job_submit_direct(job, ring, &f); 557 if (r) 558 goto err_free; 559 560 amdgpu_bo_fence(bo, f, false); 561 amdgpu_bo_unreserve(bo); 562 amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg); 563 564 if (fence) 565 *fence = dma_fence_get(f); 566 dma_fence_put(f); 567 568 return 0; 569 570 err_free: 571 amdgpu_job_free(job); 572 573 err: 574 amdgpu_bo_unreserve(bo); 575 amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg); 576 return r; 577 } 578 579 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 580 struct amdgpu_bo **bo) 581 { 582 struct amdgpu_device *adev = ring->adev; 583 uint32_t *msg; 584 int r, i; 585 586 *bo = NULL; 587 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 588 AMDGPU_GEM_DOMAIN_VRAM, 589 bo, NULL, (void **)&msg); 590 if (r) 591 return r; 592 593 msg[0] = cpu_to_le32(0x00000028); 594 msg[1] = cpu_to_le32(0x00000038); 595 msg[2] = cpu_to_le32(0x00000001); 596 msg[3] = cpu_to_le32(0x00000000); 597 msg[4] = cpu_to_le32(handle); 598 msg[5] = cpu_to_le32(0x00000000); 599 msg[6] = cpu_to_le32(0x00000001); 600 msg[7] = cpu_to_le32(0x00000028); 601 msg[8] = cpu_to_le32(0x00000010); 602 msg[9] = cpu_to_le32(0x00000000); 603 msg[10] = cpu_to_le32(0x00000007); 604 msg[11] = cpu_to_le32(0x00000000); 605 msg[12] = cpu_to_le32(0x00000780); 606 msg[13] = cpu_to_le32(0x00000440); 607 for (i = 14; i < 1024; ++i) 608 msg[i] = cpu_to_le32(0x0); 609 610 return 0; 611 } 612 613 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 614 struct amdgpu_bo **bo) 615 { 616 struct amdgpu_device *adev = ring->adev; 617 uint32_t *msg; 618 int r, i; 619 620 *bo = NULL; 621 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 622 AMDGPU_GEM_DOMAIN_VRAM, 623 bo, NULL, (void **)&msg); 624 if (r) 625 return r; 626 627 msg[0] = cpu_to_le32(0x00000028); 628 msg[1] = cpu_to_le32(0x00000018); 629 msg[2] = cpu_to_le32(0x00000000); 630 msg[3] = cpu_to_le32(0x00000002); 631 msg[4] = cpu_to_le32(handle); 632 msg[5] = cpu_to_le32(0x00000000); 633 for (i = 6; i < 1024; ++i) 634 msg[i] = cpu_to_le32(0x0); 635 636 return 0; 637 } 638 639 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 640 { 641 struct dma_fence *fence = NULL; 642 struct amdgpu_bo *bo; 643 long r; 644 645 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo); 646 if (r) 647 goto error; 648 649 r = amdgpu_vcn_dec_send_msg(ring, bo, NULL); 650 if (r) 651 goto error; 652 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo); 653 if (r) 654 goto error; 655 656 r = amdgpu_vcn_dec_send_msg(ring, bo, &fence); 657 if (r) 658 goto error; 659 660 r = dma_fence_wait_timeout(fence, false, timeout); 661 if (r == 0) 662 r = -ETIMEDOUT; 663 else if (r > 0) 664 r = 0; 665 666 dma_fence_put(fence); 667 error: 668 return r; 669 } 670 671 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 672 struct amdgpu_bo *bo, 673 struct dma_fence **fence) 674 { 675 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 676 const unsigned int ib_size_dw = 64; 677 struct amdgpu_device *adev = ring->adev; 678 struct dma_fence *f = NULL; 679 struct amdgpu_job *job; 680 struct amdgpu_ib *ib; 681 uint64_t addr; 682 int i, r; 683 684 r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4, 685 AMDGPU_IB_POOL_DIRECT, &job); 686 if (r) 687 goto err; 688 689 ib = &job->ibs[0]; 690 addr = amdgpu_bo_gpu_offset(bo); 691 ib->length_dw = 0; 692 693 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 694 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 695 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 696 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 697 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 698 699 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 700 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 701 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 702 703 for (i = ib->length_dw; i < ib_size_dw; ++i) 704 ib->ptr[i] = 0x0; 705 706 r = amdgpu_job_submit_direct(job, ring, &f); 707 if (r) 708 goto err_free; 709 710 amdgpu_bo_fence(bo, f, false); 711 amdgpu_bo_unreserve(bo); 712 amdgpu_bo_unref(&bo); 713 714 if (fence) 715 *fence = dma_fence_get(f); 716 dma_fence_put(f); 717 718 return 0; 719 720 err_free: 721 amdgpu_job_free(job); 722 723 err: 724 amdgpu_bo_unreserve(bo); 725 amdgpu_bo_unref(&bo); 726 return r; 727 } 728 729 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 730 { 731 struct dma_fence *fence = NULL; 732 struct amdgpu_bo *bo; 733 long r; 734 735 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo); 736 if (r) 737 goto error; 738 739 r = amdgpu_vcn_dec_sw_send_msg(ring, bo, NULL); 740 if (r) 741 goto error; 742 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo); 743 if (r) 744 goto error; 745 746 r = amdgpu_vcn_dec_sw_send_msg(ring, bo, &fence); 747 if (r) 748 goto error; 749 750 r = dma_fence_wait_timeout(fence, false, timeout); 751 if (r == 0) 752 r = -ETIMEDOUT; 753 else if (r > 0) 754 r = 0; 755 756 dma_fence_put(fence); 757 error: 758 return r; 759 } 760 761 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 762 { 763 struct amdgpu_device *adev = ring->adev; 764 uint32_t rptr; 765 unsigned i; 766 int r; 767 768 if (amdgpu_sriov_vf(adev)) 769 return 0; 770 771 r = amdgpu_ring_alloc(ring, 16); 772 if (r) 773 return r; 774 775 rptr = amdgpu_ring_get_rptr(ring); 776 777 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 778 amdgpu_ring_commit(ring); 779 780 for (i = 0; i < adev->usec_timeout; i++) { 781 if (amdgpu_ring_get_rptr(ring) != rptr) 782 break; 783 udelay(1); 784 } 785 786 if (i >= adev->usec_timeout) 787 r = -ETIMEDOUT; 788 789 return r; 790 } 791 792 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 793 struct amdgpu_bo *bo, 794 struct dma_fence **fence) 795 { 796 const unsigned ib_size_dw = 16; 797 struct amdgpu_job *job; 798 struct amdgpu_ib *ib; 799 struct dma_fence *f = NULL; 800 uint64_t addr; 801 int i, r; 802 803 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 804 AMDGPU_IB_POOL_DIRECT, &job); 805 if (r) 806 return r; 807 808 ib = &job->ibs[0]; 809 addr = amdgpu_bo_gpu_offset(bo); 810 811 ib->length_dw = 0; 812 ib->ptr[ib->length_dw++] = 0x00000018; 813 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 814 ib->ptr[ib->length_dw++] = handle; 815 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 816 ib->ptr[ib->length_dw++] = addr; 817 ib->ptr[ib->length_dw++] = 0x0000000b; 818 819 ib->ptr[ib->length_dw++] = 0x00000014; 820 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 821 ib->ptr[ib->length_dw++] = 0x0000001c; 822 ib->ptr[ib->length_dw++] = 0x00000000; 823 ib->ptr[ib->length_dw++] = 0x00000000; 824 825 ib->ptr[ib->length_dw++] = 0x00000008; 826 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 827 828 for (i = ib->length_dw; i < ib_size_dw; ++i) 829 ib->ptr[i] = 0x0; 830 831 r = amdgpu_job_submit_direct(job, ring, &f); 832 if (r) 833 goto err; 834 835 if (fence) 836 *fence = dma_fence_get(f); 837 dma_fence_put(f); 838 839 return 0; 840 841 err: 842 amdgpu_job_free(job); 843 return r; 844 } 845 846 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 847 struct amdgpu_bo *bo, 848 struct dma_fence **fence) 849 { 850 const unsigned ib_size_dw = 16; 851 struct amdgpu_job *job; 852 struct amdgpu_ib *ib; 853 struct dma_fence *f = NULL; 854 uint64_t addr; 855 int i, r; 856 857 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 858 AMDGPU_IB_POOL_DIRECT, &job); 859 if (r) 860 return r; 861 862 ib = &job->ibs[0]; 863 addr = amdgpu_bo_gpu_offset(bo); 864 865 ib->length_dw = 0; 866 ib->ptr[ib->length_dw++] = 0x00000018; 867 ib->ptr[ib->length_dw++] = 0x00000001; 868 ib->ptr[ib->length_dw++] = handle; 869 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 870 ib->ptr[ib->length_dw++] = addr; 871 ib->ptr[ib->length_dw++] = 0x0000000b; 872 873 ib->ptr[ib->length_dw++] = 0x00000014; 874 ib->ptr[ib->length_dw++] = 0x00000002; 875 ib->ptr[ib->length_dw++] = 0x0000001c; 876 ib->ptr[ib->length_dw++] = 0x00000000; 877 ib->ptr[ib->length_dw++] = 0x00000000; 878 879 ib->ptr[ib->length_dw++] = 0x00000008; 880 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 881 882 for (i = ib->length_dw; i < ib_size_dw; ++i) 883 ib->ptr[i] = 0x0; 884 885 r = amdgpu_job_submit_direct(job, ring, &f); 886 if (r) 887 goto err; 888 889 if (fence) 890 *fence = dma_fence_get(f); 891 dma_fence_put(f); 892 893 return 0; 894 895 err: 896 amdgpu_job_free(job); 897 return r; 898 } 899 900 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 901 { 902 struct dma_fence *fence = NULL; 903 struct amdgpu_bo *bo = NULL; 904 long r; 905 906 r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE, 907 AMDGPU_GEM_DOMAIN_VRAM, 908 &bo, NULL, NULL); 909 if (r) 910 return r; 911 912 r = amdgpu_vcn_enc_get_create_msg(ring, 1, bo, NULL); 913 if (r) 914 goto error; 915 916 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, bo, &fence); 917 if (r) 918 goto error; 919 920 r = dma_fence_wait_timeout(fence, false, timeout); 921 if (r == 0) 922 r = -ETIMEDOUT; 923 else if (r > 0) 924 r = 0; 925 926 error: 927 dma_fence_put(fence); 928 amdgpu_bo_unreserve(bo); 929 amdgpu_bo_free_kernel(&bo, NULL, NULL); 930 931 return r; 932 } 933