1 /* 2 * Copyright 2016-2024 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/dmi.h> 30 #include <linux/pci.h> 31 #include <linux/debugfs.h> 32 #include <drm/drm_drv.h> 33 34 #include "amdgpu.h" 35 #include "amdgpu_pm.h" 36 #include "amdgpu_vcn.h" 37 #include "amdgpu_reset.h" 38 #include "soc15d.h" 39 40 /* Firmware Names */ 41 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 42 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 43 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 44 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 45 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 46 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 47 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 48 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 49 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 50 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 51 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 52 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 53 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 54 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 55 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 56 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 57 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin" 58 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin" 59 #define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin" 60 #define FIRMWARE_VCN4_0_3 "amdgpu/vcn_4_0_3.bin" 61 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin" 62 #define FIRMWARE_VCN4_0_5 "amdgpu/vcn_4_0_5.bin" 63 #define FIRMWARE_VCN4_0_6 "amdgpu/vcn_4_0_6.bin" 64 #define FIRMWARE_VCN4_0_6_1 "amdgpu/vcn_4_0_6_1.bin" 65 #define FIRMWARE_VCN5_0_0 "amdgpu/vcn_5_0_0.bin" 66 #define FIRMWARE_VCN5_0_1 "amdgpu/vcn_5_0_1.bin" 67 #define FIRMWARE_VCN5_0_2 "amdgpu/vcn_5_0_2.bin" 68 #define FIRMWARE_VCN5_3_0 "amdgpu/vcn_5_3_0.bin" 69 70 MODULE_FIRMWARE(FIRMWARE_RAVEN); 71 MODULE_FIRMWARE(FIRMWARE_PICASSO); 72 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 73 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 74 MODULE_FIRMWARE(FIRMWARE_RENOIR); 75 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 76 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 77 MODULE_FIRMWARE(FIRMWARE_NAVI10); 78 MODULE_FIRMWARE(FIRMWARE_NAVI14); 79 MODULE_FIRMWARE(FIRMWARE_NAVI12); 80 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 81 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 82 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 83 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 84 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 85 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 86 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2); 87 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0); 88 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2); 89 MODULE_FIRMWARE(FIRMWARE_VCN4_0_3); 90 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4); 91 MODULE_FIRMWARE(FIRMWARE_VCN4_0_5); 92 MODULE_FIRMWARE(FIRMWARE_VCN4_0_6); 93 MODULE_FIRMWARE(FIRMWARE_VCN4_0_6_1); 94 MODULE_FIRMWARE(FIRMWARE_VCN5_0_0); 95 MODULE_FIRMWARE(FIRMWARE_VCN5_0_1); 96 MODULE_FIRMWARE(FIRMWARE_VCN5_0_2); 97 MODULE_FIRMWARE(FIRMWARE_VCN5_3_0); 98 99 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 100 static void amdgpu_vcn_reg_dump_fini(struct amdgpu_device *adev); 101 102 int amdgpu_vcn_early_init(struct amdgpu_device *adev, int i) 103 { 104 char ucode_prefix[25]; 105 int r; 106 107 adev->vcn.inst[i].adev = adev; 108 adev->vcn.inst[i].inst = i; 109 amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix)); 110 111 if (i != 0 && adev->vcn.per_inst_fw) { 112 r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw, 113 AMDGPU_UCODE_REQUIRED, 114 "amdgpu/%s_%d.bin", ucode_prefix, i); 115 if (r) 116 amdgpu_ucode_release(&adev->vcn.inst[i].fw); 117 } else { 118 if (!adev->vcn.inst[0].fw) { 119 r = amdgpu_ucode_request(adev, &adev->vcn.inst[0].fw, 120 AMDGPU_UCODE_REQUIRED, 121 "amdgpu/%s.bin", ucode_prefix); 122 if (r) 123 amdgpu_ucode_release(&adev->vcn.inst[0].fw); 124 } else { 125 r = 0; 126 } 127 adev->vcn.inst[i].fw = adev->vcn.inst[0].fw; 128 } 129 130 return r; 131 } 132 133 int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int i) 134 { 135 unsigned long bo_size; 136 const struct common_firmware_header *hdr; 137 unsigned char fw_check; 138 unsigned int fw_shared_size, log_offset; 139 int r; 140 141 mutex_init(&adev->vcn.inst[i].vcn1_jpeg1_workaround); 142 mutex_init(&adev->vcn.inst[i].vcn_pg_lock); 143 mutex_init(&adev->vcn.inst[i].engine_reset_mutex); 144 atomic_set(&adev->vcn.inst[i].total_submission_cnt, 0); 145 INIT_DELAYED_WORK(&adev->vcn.inst[i].idle_work, amdgpu_vcn_idle_work_handler); 146 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 147 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 148 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 149 adev->vcn.inst[i].indirect_sram = true; 150 151 /* 152 * Some Steam Deck's BIOS versions are incompatible with the 153 * indirect SRAM mode, leading to amdgpu being unable to get 154 * properly probed (and even potentially crashing the kernel). 155 * Hence, check for these versions here - notice this is 156 * restricted to Vangogh (Deck's APU). 157 */ 158 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 0, 2)) { 159 const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION); 160 161 if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) || 162 !strncmp("F7A0114", bios_ver, 7))) { 163 adev->vcn.inst[i].indirect_sram = false; 164 dev_info(adev->dev, 165 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver); 166 } 167 } 168 169 /* from vcn4 and above, only unified queue is used */ 170 adev->vcn.inst[i].using_unified_queue = 171 amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0); 172 173 hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data; 174 adev->vcn.inst[i].fw_version = le32_to_cpu(hdr->ucode_version); 175 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 176 177 /* Bit 20-23, it is encode major and non-zero for new naming convention. 178 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 179 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 180 * is zero in old naming convention, this field is always zero so far. 181 * These four bits are used to tell which naming convention is present. 182 */ 183 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 184 if (fw_check) { 185 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 186 187 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 188 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 189 enc_major = fw_check; 190 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 191 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 192 dev_info(adev->dev, 193 "[VCN instance %d] Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 194 i, enc_major, enc_minor, dec_ver, vep, fw_rev); 195 } else { 196 unsigned int version_major, version_minor, family_id; 197 198 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 199 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 200 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 201 dev_info(adev->dev, "[VCN instance %d] Found VCN firmware Version: %u.%u Family ID: %u\n", 202 i, version_major, version_minor, family_id); 203 } 204 205 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 206 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 207 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 208 209 if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(5, 0, 0)) { 210 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)); 211 log_offset = offsetof(struct amdgpu_vcn5_fw_shared, fw_log); 212 } else if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) { 213 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); 214 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log); 215 } else { 216 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 217 log_offset = offsetof(struct amdgpu_fw_shared, fw_log); 218 } 219 220 bo_size += fw_shared_size; 221 222 if (amdgpu_vcnfw_log) 223 bo_size += AMDGPU_VCNFW_LOG_SIZE; 224 225 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 226 AMDGPU_GEM_DOMAIN_VRAM | 227 AMDGPU_GEM_DOMAIN_GTT, 228 &adev->vcn.inst[i].vcpu_bo, 229 &adev->vcn.inst[i].gpu_addr, 230 &adev->vcn.inst[i].cpu_addr); 231 if (r) { 232 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 233 return r; 234 } 235 236 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr + 237 bo_size - fw_shared_size; 238 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr + 239 bo_size - fw_shared_size; 240 241 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size; 242 243 if (amdgpu_vcnfw_log) { 244 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 245 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 246 adev->vcn.inst[i].fw_shared.log_offset = log_offset; 247 } 248 249 if (adev->vcn.inst[i].indirect_sram) { 250 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 251 AMDGPU_GEM_DOMAIN_VRAM | 252 AMDGPU_GEM_DOMAIN_GTT, 253 &adev->vcn.inst[i].dpg_sram_bo, 254 &adev->vcn.inst[i].dpg_sram_gpu_addr, 255 &adev->vcn.inst[i].dpg_sram_cpu_addr); 256 if (r) { 257 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 258 return r; 259 } 260 } 261 262 return 0; 263 } 264 265 void amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int i) 266 { 267 int j; 268 269 if (adev->vcn.harvest_config & (1 << i)) 270 return; 271 272 amdgpu_bo_free_kernel( 273 &adev->vcn.inst[i].dpg_sram_bo, 274 &adev->vcn.inst[i].dpg_sram_gpu_addr, 275 (void **)&adev->vcn.inst[i].dpg_sram_cpu_addr); 276 277 kvfree(adev->vcn.inst[i].saved_bo); 278 279 amdgpu_bo_free_kernel(&adev->vcn.inst[i].vcpu_bo, 280 &adev->vcn.inst[i].gpu_addr, 281 (void **)&adev->vcn.inst[i].cpu_addr); 282 283 amdgpu_ring_fini(&adev->vcn.inst[i].ring_dec); 284 285 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) 286 amdgpu_ring_fini(&adev->vcn.inst[i].ring_enc[j]); 287 288 if (adev->vcn.per_inst_fw) { 289 amdgpu_ucode_release(&adev->vcn.inst[i].fw); 290 } else { 291 amdgpu_ucode_release(&adev->vcn.inst[0].fw); 292 adev->vcn.inst[i].fw = NULL; 293 } 294 295 if (adev->vcn.reg_list) 296 amdgpu_vcn_reg_dump_fini(adev); 297 298 mutex_destroy(&adev->vcn.inst[i].vcn_pg_lock); 299 mutex_destroy(&adev->vcn.inst[i].vcn1_jpeg1_workaround); 300 } 301 302 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 303 { 304 bool ret = false; 305 int vcn_config = adev->vcn.inst[vcn_instance].vcn_config; 306 307 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) 308 ret = true; 309 else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) 310 ret = true; 311 else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) 312 ret = true; 313 314 return ret; 315 } 316 317 static int amdgpu_vcn_save_vcpu_bo_inst(struct amdgpu_device *adev, int i) 318 { 319 unsigned int size; 320 void *ptr; 321 int idx; 322 323 if (adev->vcn.harvest_config & (1 << i)) 324 return 0; 325 if (adev->vcn.inst[i].vcpu_bo == NULL) 326 return 0; 327 328 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 329 ptr = adev->vcn.inst[i].cpu_addr; 330 331 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 332 if (!adev->vcn.inst[i].saved_bo) 333 return -ENOMEM; 334 335 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 336 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 337 drm_dev_exit(idx); 338 } 339 340 return 0; 341 } 342 343 int amdgpu_vcn_save_vcpu_bo(struct amdgpu_device *adev) 344 { 345 int ret, i; 346 347 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 348 ret = amdgpu_vcn_save_vcpu_bo_inst(adev, i); 349 if (ret) 350 return ret; 351 } 352 353 return 0; 354 } 355 356 int amdgpu_vcn_suspend(struct amdgpu_device *adev, int i) 357 { 358 bool in_ras_intr = amdgpu_ras_intr_triggered(); 359 360 if (adev->vcn.harvest_config & (1 << i)) 361 return 0; 362 363 /* err_event_athub and dpc recovery will corrupt VCPU buffer, so we need to 364 * restore fw data and clear buffer in amdgpu_vcn_resume() */ 365 if (in_ras_intr || amdgpu_reset_in_dpc(adev)) 366 return 0; 367 368 return amdgpu_vcn_save_vcpu_bo_inst(adev, i); 369 } 370 371 int amdgpu_vcn_resume(struct amdgpu_device *adev, int i) 372 { 373 unsigned int size; 374 void *ptr; 375 int idx; 376 377 if (adev->vcn.harvest_config & (1 << i)) 378 return 0; 379 if (adev->vcn.inst[i].vcpu_bo == NULL) 380 return -EINVAL; 381 382 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 383 ptr = adev->vcn.inst[i].cpu_addr; 384 385 if (adev->vcn.inst[i].saved_bo != NULL) { 386 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 387 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 388 drm_dev_exit(idx); 389 } 390 kvfree(adev->vcn.inst[i].saved_bo); 391 adev->vcn.inst[i].saved_bo = NULL; 392 } else { 393 const struct common_firmware_header *hdr; 394 unsigned int offset; 395 396 hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data; 397 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 398 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 399 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 400 memcpy_toio(adev->vcn.inst[i].cpu_addr, 401 adev->vcn.inst[i].fw->data + offset, 402 le32_to_cpu(hdr->ucode_size_bytes)); 403 drm_dev_exit(idx); 404 } 405 size -= le32_to_cpu(hdr->ucode_size_bytes); 406 ptr += le32_to_cpu(hdr->ucode_size_bytes); 407 } 408 memset_io(ptr, 0, size); 409 } 410 411 return 0; 412 } 413 414 void amdgpu_vcn_get_profile(struct amdgpu_device *adev) 415 { 416 int r; 417 418 mutex_lock(&adev->vcn.workload_profile_mutex); 419 420 if (adev->vcn.workload_profile_active) { 421 mutex_unlock(&adev->vcn.workload_profile_mutex); 422 return; 423 } 424 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 425 true); 426 if (r) 427 dev_warn(adev->dev, 428 "(%d) failed to enable video power profile mode\n", r); 429 else 430 adev->vcn.workload_profile_active = true; 431 mutex_unlock(&adev->vcn.workload_profile_mutex); 432 } 433 434 void amdgpu_vcn_put_profile(struct amdgpu_device *adev) 435 { 436 bool pg = true; 437 int r, i; 438 439 mutex_lock(&adev->vcn.workload_profile_mutex); 440 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 441 if (adev->vcn.inst[i].cur_state != AMD_PG_STATE_GATE) { 442 pg = false; 443 break; 444 } 445 } 446 447 if (pg) { 448 r = amdgpu_dpm_switch_power_profile( 449 adev, PP_SMC_POWER_PROFILE_VIDEO, false); 450 if (r) 451 dev_warn( 452 adev->dev, 453 "(%d) failed to disable video power profile mode\n", 454 r); 455 else 456 adev->vcn.workload_profile_active = false; 457 } 458 459 mutex_unlock(&adev->vcn.workload_profile_mutex); 460 } 461 462 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 463 { 464 struct amdgpu_vcn_inst *vcn_inst = 465 container_of(work, struct amdgpu_vcn_inst, idle_work.work); 466 struct amdgpu_device *adev = vcn_inst->adev; 467 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 468 unsigned int i = vcn_inst->inst, j; 469 470 if (adev->vcn.harvest_config & (1 << i)) 471 return; 472 473 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) 474 fence[i] += amdgpu_fence_count_emitted(&vcn_inst->ring_enc[j]); 475 476 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 477 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 478 !adev->vcn.inst[i].using_unified_queue) { 479 struct dpg_pause_state new_state; 480 481 if (fence[i] || 482 unlikely(atomic_read(&vcn_inst->dpg_enc_submission_cnt))) 483 new_state.fw_based = VCN_DPG_STATE__PAUSE; 484 else 485 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 486 487 adev->vcn.inst[i].pause_dpg_mode(vcn_inst, &new_state); 488 } 489 490 fence[i] += amdgpu_fence_count_emitted(&vcn_inst->ring_dec); 491 fences += fence[i]; 492 493 if (!fences && !atomic_read(&vcn_inst->total_submission_cnt)) { 494 mutex_lock(&vcn_inst->vcn_pg_lock); 495 vcn_inst->set_pg_state(vcn_inst, AMD_PG_STATE_GATE); 496 mutex_unlock(&vcn_inst->vcn_pg_lock); 497 amdgpu_vcn_put_profile(adev); 498 499 } else { 500 schedule_delayed_work(&vcn_inst->idle_work, VCN_IDLE_TIMEOUT); 501 } 502 } 503 504 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 505 { 506 struct amdgpu_device *adev = ring->adev; 507 struct amdgpu_vcn_inst *vcn_inst = &adev->vcn.inst[ring->me]; 508 509 if (!atomic_fetch_inc(&vcn_inst->total_submission_cnt)) 510 cancel_delayed_work_sync(&vcn_inst->idle_work); 511 512 mutex_lock(&vcn_inst->vcn_pg_lock); 513 vcn_inst->set_pg_state(vcn_inst, AMD_PG_STATE_UNGATE); 514 515 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 516 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 517 !vcn_inst->using_unified_queue) { 518 struct dpg_pause_state new_state; 519 520 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 521 atomic_inc(&vcn_inst->dpg_enc_submission_cnt); 522 new_state.fw_based = VCN_DPG_STATE__PAUSE; 523 } else { 524 unsigned int fences = 0; 525 unsigned int i; 526 527 for (i = 0; i < vcn_inst->num_enc_rings; ++i) 528 fences += amdgpu_fence_count_emitted(&vcn_inst->ring_enc[i]); 529 530 if (fences || atomic_read(&vcn_inst->dpg_enc_submission_cnt)) 531 new_state.fw_based = VCN_DPG_STATE__PAUSE; 532 else 533 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 534 } 535 536 vcn_inst->pause_dpg_mode(vcn_inst, &new_state); 537 } 538 mutex_unlock(&vcn_inst->vcn_pg_lock); 539 amdgpu_vcn_get_profile(adev); 540 } 541 542 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 543 { 544 struct amdgpu_device *adev = ring->adev; 545 546 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 547 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 548 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC && 549 !adev->vcn.inst[ring->me].using_unified_queue) 550 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 551 552 if (atomic_dec_and_test(&ring->adev->vcn.inst[ring->me].total_submission_cnt)) 553 schedule_delayed_work(&ring->adev->vcn.inst[ring->me].idle_work, 554 VCN_IDLE_TIMEOUT); 555 } 556 557 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 558 { 559 struct amdgpu_device *adev = ring->adev; 560 uint32_t tmp = 0; 561 unsigned int i; 562 int r; 563 564 /* VCN in SRIOV does not support direct register read/write */ 565 if (amdgpu_sriov_vf(adev)) 566 return 0; 567 568 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 569 r = amdgpu_ring_alloc(ring, 3); 570 if (r) 571 return r; 572 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.scratch9, 0)); 573 amdgpu_ring_write(ring, 0xDEADBEEF); 574 amdgpu_ring_commit(ring); 575 for (i = 0; i < adev->usec_timeout; i++) { 576 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 577 if (tmp == 0xDEADBEEF) 578 break; 579 udelay(1); 580 } 581 582 if (i >= adev->usec_timeout) 583 r = -ETIMEDOUT; 584 585 return r; 586 } 587 588 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 589 { 590 struct amdgpu_device *adev = ring->adev; 591 uint32_t rptr; 592 unsigned int i; 593 int r; 594 595 if (amdgpu_sriov_vf(adev)) 596 return 0; 597 598 r = amdgpu_ring_alloc(ring, 16); 599 if (r) 600 return r; 601 602 rptr = amdgpu_ring_get_rptr(ring); 603 604 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 605 amdgpu_ring_commit(ring); 606 607 for (i = 0; i < adev->usec_timeout; i++) { 608 if (amdgpu_ring_get_rptr(ring) != rptr) 609 break; 610 udelay(1); 611 } 612 613 if (i >= adev->usec_timeout) 614 r = -ETIMEDOUT; 615 616 return r; 617 } 618 619 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 620 struct amdgpu_ib *ib_msg, 621 struct dma_fence **fence) 622 { 623 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 624 struct amdgpu_device *adev = ring->adev; 625 struct dma_fence *f = NULL; 626 struct amdgpu_job *job; 627 struct amdgpu_ib *ib; 628 int i, r; 629 630 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 631 64, AMDGPU_IB_POOL_DIRECT, 632 &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); 633 if (r) 634 goto err; 635 636 ib = &job->ibs[0]; 637 ib->ptr[0] = PACKET0(adev->vcn.inst[ring->me].internal.data0, 0); 638 ib->ptr[1] = addr; 639 ib->ptr[2] = PACKET0(adev->vcn.inst[ring->me].internal.data1, 0); 640 ib->ptr[3] = addr >> 32; 641 ib->ptr[4] = PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0); 642 ib->ptr[5] = 0; 643 for (i = 6; i < 16; i += 2) { 644 ib->ptr[i] = PACKET0(adev->vcn.inst[ring->me].internal.nop, 0); 645 ib->ptr[i+1] = 0; 646 } 647 ib->length_dw = 16; 648 649 r = amdgpu_job_submit_direct(job, ring, &f); 650 if (r) 651 goto err_free; 652 653 amdgpu_ib_free(ib_msg, f); 654 655 if (fence) 656 *fence = dma_fence_get(f); 657 dma_fence_put(f); 658 659 return 0; 660 661 err_free: 662 amdgpu_job_free(job); 663 err: 664 amdgpu_ib_free(ib_msg, f); 665 return r; 666 } 667 668 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 669 struct amdgpu_ib *ib) 670 { 671 struct amdgpu_device *adev = ring->adev; 672 uint32_t *msg; 673 int r, i; 674 675 memset(ib, 0, sizeof(*ib)); 676 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 677 AMDGPU_IB_POOL_DIRECT, 678 ib); 679 if (r) 680 return r; 681 682 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 683 msg[0] = cpu_to_le32(0x00000028); 684 msg[1] = cpu_to_le32(0x00000038); 685 msg[2] = cpu_to_le32(0x00000001); 686 msg[3] = cpu_to_le32(0x00000000); 687 msg[4] = cpu_to_le32(handle); 688 msg[5] = cpu_to_le32(0x00000000); 689 msg[6] = cpu_to_le32(0x00000001); 690 msg[7] = cpu_to_le32(0x00000028); 691 msg[8] = cpu_to_le32(0x00000010); 692 msg[9] = cpu_to_le32(0x00000000); 693 msg[10] = cpu_to_le32(0x00000007); 694 msg[11] = cpu_to_le32(0x00000000); 695 msg[12] = cpu_to_le32(0x00000780); 696 msg[13] = cpu_to_le32(0x00000440); 697 for (i = 14; i < 1024; ++i) 698 msg[i] = cpu_to_le32(0x0); 699 700 return 0; 701 } 702 703 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 704 struct amdgpu_ib *ib) 705 { 706 struct amdgpu_device *adev = ring->adev; 707 uint32_t *msg; 708 int r, i; 709 710 memset(ib, 0, sizeof(*ib)); 711 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 712 AMDGPU_IB_POOL_DIRECT, 713 ib); 714 if (r) 715 return r; 716 717 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 718 msg[0] = cpu_to_le32(0x00000028); 719 msg[1] = cpu_to_le32(0x00000018); 720 msg[2] = cpu_to_le32(0x00000000); 721 msg[3] = cpu_to_le32(0x00000002); 722 msg[4] = cpu_to_le32(handle); 723 msg[5] = cpu_to_le32(0x00000000); 724 for (i = 6; i < 1024; ++i) 725 msg[i] = cpu_to_le32(0x0); 726 727 return 0; 728 } 729 730 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 731 { 732 struct dma_fence *fence = NULL; 733 struct amdgpu_ib ib; 734 long r; 735 736 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 737 if (r) 738 goto error; 739 740 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 741 if (r) 742 goto error; 743 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 744 if (r) 745 goto error; 746 747 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 748 if (r) 749 goto error; 750 751 r = dma_fence_wait_timeout(fence, false, timeout); 752 if (r == 0) 753 r = -ETIMEDOUT; 754 else if (r > 0) 755 r = 0; 756 757 dma_fence_put(fence); 758 error: 759 return r; 760 } 761 762 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, 763 uint32_t ib_pack_in_dw, bool enc) 764 { 765 uint32_t *ib_checksum; 766 767 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */ 768 ib->ptr[ib->length_dw++] = 0x30000002; 769 ib_checksum = &ib->ptr[ib->length_dw++]; 770 ib->ptr[ib->length_dw++] = ib_pack_in_dw; 771 772 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */ 773 ib->ptr[ib->length_dw++] = 0x30000001; 774 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3; 775 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t); 776 777 return ib_checksum; 778 } 779 780 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum, 781 uint32_t ib_pack_in_dw) 782 { 783 uint32_t i; 784 uint32_t checksum = 0; 785 786 for (i = 0; i < ib_pack_in_dw; i++) 787 checksum += *(*ib_checksum + 2 + i); 788 789 **ib_checksum = checksum; 790 } 791 792 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 793 struct amdgpu_ib *ib_msg, 794 struct dma_fence **fence) 795 { 796 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 797 unsigned int ib_size_dw = 64; 798 struct amdgpu_device *adev = ring->adev; 799 struct dma_fence *f = NULL; 800 struct amdgpu_job *job; 801 struct amdgpu_ib *ib; 802 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 803 uint32_t *ib_checksum; 804 uint32_t ib_pack_in_dw; 805 int i, r; 806 807 if (adev->vcn.inst[ring->me].using_unified_queue) 808 ib_size_dw += 8; 809 810 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 811 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 812 &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); 813 if (r) 814 goto err; 815 816 ib = &job->ibs[0]; 817 ib->length_dw = 0; 818 819 /* single queue headers */ 820 if (adev->vcn.inst[ring->me].using_unified_queue) { 821 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t) 822 + 4 + 2; /* engine info + decoding ib in dw */ 823 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false); 824 } 825 826 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 827 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 828 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 829 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 830 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 831 832 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 833 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 834 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 835 836 for (i = ib->length_dw; i < ib_size_dw; ++i) 837 ib->ptr[i] = 0x0; 838 839 if (adev->vcn.inst[ring->me].using_unified_queue) 840 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw); 841 842 r = amdgpu_job_submit_direct(job, ring, &f); 843 if (r) 844 goto err_free; 845 846 amdgpu_ib_free(ib_msg, f); 847 848 if (fence) 849 *fence = dma_fence_get(f); 850 dma_fence_put(f); 851 852 return 0; 853 854 err_free: 855 amdgpu_job_free(job); 856 err: 857 amdgpu_ib_free(ib_msg, f); 858 return r; 859 } 860 861 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 862 { 863 struct dma_fence *fence = NULL; 864 struct amdgpu_ib ib; 865 long r; 866 867 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 868 if (r) 869 goto error; 870 871 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 872 if (r) 873 goto error; 874 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 875 if (r) 876 goto error; 877 878 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 879 if (r) 880 goto error; 881 882 r = dma_fence_wait_timeout(fence, false, timeout); 883 if (r == 0) 884 r = -ETIMEDOUT; 885 else if (r > 0) 886 r = 0; 887 888 dma_fence_put(fence); 889 error: 890 return r; 891 } 892 893 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 894 { 895 struct amdgpu_device *adev = ring->adev; 896 uint32_t rptr; 897 unsigned int i; 898 int r; 899 900 if (amdgpu_sriov_vf(adev)) 901 return 0; 902 903 r = amdgpu_ring_alloc(ring, 16); 904 if (r) 905 return r; 906 907 rptr = amdgpu_ring_get_rptr(ring); 908 909 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 910 amdgpu_ring_commit(ring); 911 912 for (i = 0; i < adev->usec_timeout; i++) { 913 if (amdgpu_ring_get_rptr(ring) != rptr) 914 break; 915 udelay(1); 916 } 917 918 if (i >= adev->usec_timeout) 919 r = -ETIMEDOUT; 920 921 return r; 922 } 923 924 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 925 struct amdgpu_ib *ib_msg, 926 struct dma_fence **fence) 927 { 928 unsigned int ib_size_dw = 16; 929 struct amdgpu_device *adev = ring->adev; 930 struct amdgpu_job *job; 931 struct amdgpu_ib *ib; 932 struct dma_fence *f = NULL; 933 uint32_t *ib_checksum = NULL; 934 uint64_t addr; 935 int i, r; 936 937 if (adev->vcn.inst[ring->me].using_unified_queue) 938 ib_size_dw += 8; 939 940 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 941 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 942 &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); 943 if (r) 944 return r; 945 946 ib = &job->ibs[0]; 947 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 948 949 ib->length_dw = 0; 950 951 if (adev->vcn.inst[ring->me].using_unified_queue) 952 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 953 954 ib->ptr[ib->length_dw++] = 0x00000018; 955 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 956 ib->ptr[ib->length_dw++] = handle; 957 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 958 ib->ptr[ib->length_dw++] = addr; 959 ib->ptr[ib->length_dw++] = 0x00000000; 960 961 ib->ptr[ib->length_dw++] = 0x00000014; 962 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 963 ib->ptr[ib->length_dw++] = 0x0000001c; 964 ib->ptr[ib->length_dw++] = 0x00000000; 965 ib->ptr[ib->length_dw++] = 0x00000000; 966 967 ib->ptr[ib->length_dw++] = 0x00000008; 968 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 969 970 for (i = ib->length_dw; i < ib_size_dw; ++i) 971 ib->ptr[i] = 0x0; 972 973 if (adev->vcn.inst[ring->me].using_unified_queue) 974 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 975 976 r = amdgpu_job_submit_direct(job, ring, &f); 977 if (r) 978 goto err; 979 980 if (fence) 981 *fence = dma_fence_get(f); 982 dma_fence_put(f); 983 984 return 0; 985 986 err: 987 amdgpu_job_free(job); 988 return r; 989 } 990 991 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 992 struct amdgpu_ib *ib_msg, 993 struct dma_fence **fence) 994 { 995 unsigned int ib_size_dw = 16; 996 struct amdgpu_device *adev = ring->adev; 997 struct amdgpu_job *job; 998 struct amdgpu_ib *ib; 999 struct dma_fence *f = NULL; 1000 uint32_t *ib_checksum = NULL; 1001 uint64_t addr; 1002 int i, r; 1003 1004 if (adev->vcn.inst[ring->me].using_unified_queue) 1005 ib_size_dw += 8; 1006 1007 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 1008 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 1009 &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); 1010 if (r) 1011 return r; 1012 1013 ib = &job->ibs[0]; 1014 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 1015 1016 ib->length_dw = 0; 1017 1018 if (adev->vcn.inst[ring->me].using_unified_queue) 1019 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 1020 1021 ib->ptr[ib->length_dw++] = 0x00000018; 1022 ib->ptr[ib->length_dw++] = 0x00000001; 1023 ib->ptr[ib->length_dw++] = handle; 1024 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1025 ib->ptr[ib->length_dw++] = addr; 1026 ib->ptr[ib->length_dw++] = 0x00000000; 1027 1028 ib->ptr[ib->length_dw++] = 0x00000014; 1029 ib->ptr[ib->length_dw++] = 0x00000002; 1030 ib->ptr[ib->length_dw++] = 0x0000001c; 1031 ib->ptr[ib->length_dw++] = 0x00000000; 1032 ib->ptr[ib->length_dw++] = 0x00000000; 1033 1034 ib->ptr[ib->length_dw++] = 0x00000008; 1035 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 1036 1037 for (i = ib->length_dw; i < ib_size_dw; ++i) 1038 ib->ptr[i] = 0x0; 1039 1040 if (adev->vcn.inst[ring->me].using_unified_queue) 1041 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 1042 1043 r = amdgpu_job_submit_direct(job, ring, &f); 1044 if (r) 1045 goto err; 1046 1047 if (fence) 1048 *fence = dma_fence_get(f); 1049 dma_fence_put(f); 1050 1051 return 0; 1052 1053 err: 1054 amdgpu_job_free(job); 1055 return r; 1056 } 1057 1058 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1059 { 1060 struct amdgpu_device *adev = ring->adev; 1061 struct dma_fence *fence = NULL; 1062 struct amdgpu_ib ib; 1063 long r; 1064 1065 memset(&ib, 0, sizeof(ib)); 1066 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 1067 AMDGPU_IB_POOL_DIRECT, 1068 &ib); 1069 if (r) 1070 return r; 1071 1072 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 1073 if (r) 1074 goto error; 1075 1076 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 1077 if (r) 1078 goto error; 1079 1080 r = dma_fence_wait_timeout(fence, false, timeout); 1081 if (r == 0) 1082 r = -ETIMEDOUT; 1083 else if (r > 0) 1084 r = 0; 1085 1086 error: 1087 amdgpu_ib_free(&ib, fence); 1088 dma_fence_put(fence); 1089 1090 return r; 1091 } 1092 1093 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1094 { 1095 struct amdgpu_device *adev = ring->adev; 1096 long r; 1097 1098 if ((amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(4, 0, 3)) && 1099 (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(5, 0, 1)) && 1100 (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(5, 0, 2))) { 1101 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout); 1102 if (r) 1103 goto error; 1104 } 1105 1106 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout); 1107 1108 error: 1109 return r; 1110 } 1111 1112 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 1113 { 1114 switch (ring) { 1115 case 0: 1116 return AMDGPU_RING_PRIO_0; 1117 case 1: 1118 return AMDGPU_RING_PRIO_1; 1119 case 2: 1120 return AMDGPU_RING_PRIO_2; 1121 default: 1122 return AMDGPU_RING_PRIO_0; 1123 } 1124 } 1125 1126 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev, int i) 1127 { 1128 unsigned int idx; 1129 1130 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1131 const struct common_firmware_header *hdr; 1132 1133 if (adev->vcn.harvest_config & (1 << i)) 1134 return; 1135 1136 if ((amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 3) || 1137 amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(5, 0, 1) || 1138 amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(5, 0, 2)) 1139 && (i > 0)) 1140 return; 1141 1142 hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data; 1143 /* currently only support 2 FW instances */ 1144 if (i >= 2) { 1145 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 1146 return; 1147 } 1148 idx = AMDGPU_UCODE_ID_VCN + i; 1149 adev->firmware.ucode[idx].ucode_id = idx; 1150 adev->firmware.ucode[idx].fw = adev->vcn.inst[i].fw; 1151 adev->firmware.fw_size += 1152 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 1153 } 1154 } 1155 1156 /* 1157 * debugfs for mapping vcn firmware log buffer. 1158 */ 1159 #if defined(CONFIG_DEBUG_FS) 1160 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf, 1161 size_t size, loff_t *pos) 1162 { 1163 struct amdgpu_vcn_inst *vcn; 1164 void *log_buf; 1165 struct amdgpu_vcn_fwlog *plog; 1166 unsigned int read_pos, write_pos, available, i, read_bytes = 0; 1167 unsigned int read_num[2] = {0}; 1168 1169 vcn = file_inode(f)->i_private; 1170 if (!vcn) 1171 return -ENODEV; 1172 1173 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log) 1174 return -EFAULT; 1175 1176 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1177 1178 plog = (struct amdgpu_vcn_fwlog *)log_buf; 1179 read_pos = plog->rptr; 1180 write_pos = plog->wptr; 1181 1182 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE) 1183 return -EFAULT; 1184 1185 if (!size || (read_pos == write_pos)) 1186 return 0; 1187 1188 if (write_pos > read_pos) { 1189 available = write_pos - read_pos; 1190 read_num[0] = min_t(size_t, size, available); 1191 } else { 1192 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos; 1193 available = read_num[0] + write_pos - plog->header_size; 1194 if (size > available) 1195 read_num[1] = write_pos - plog->header_size; 1196 else if (size > read_num[0]) 1197 read_num[1] = size - read_num[0]; 1198 else 1199 read_num[0] = size; 1200 } 1201 1202 for (i = 0; i < 2; i++) { 1203 if (read_num[i]) { 1204 if (read_pos == AMDGPU_VCNFW_LOG_SIZE) 1205 read_pos = plog->header_size; 1206 if (read_num[i] == copy_to_user((buf + read_bytes), 1207 (log_buf + read_pos), read_num[i])) 1208 return -EFAULT; 1209 1210 read_bytes += read_num[i]; 1211 read_pos += read_num[i]; 1212 } 1213 } 1214 1215 plog->rptr = read_pos; 1216 *pos += read_bytes; 1217 return read_bytes; 1218 } 1219 1220 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = { 1221 .owner = THIS_MODULE, 1222 .read = amdgpu_debugfs_vcn_fwlog_read, 1223 .llseek = default_llseek 1224 }; 1225 #endif 1226 1227 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i, 1228 struct amdgpu_vcn_inst *vcn) 1229 { 1230 #if defined(CONFIG_DEBUG_FS) 1231 struct drm_minor *minor = adev_to_drm(adev)->primary; 1232 struct dentry *root = minor->debugfs_root; 1233 char name[32]; 1234 1235 sprintf(name, "amdgpu_vcn_%d_fwlog", i); 1236 debugfs_create_file_size(name, S_IFREG | 0444, root, vcn, 1237 &amdgpu_debugfs_vcnfwlog_fops, 1238 AMDGPU_VCNFW_LOG_SIZE); 1239 #endif 1240 } 1241 1242 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn) 1243 { 1244 #if defined(CONFIG_DEBUG_FS) 1245 uint32_t *flag = vcn->fw_shared.cpu_addr; 1246 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1247 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size; 1248 struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr; 1249 struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr 1250 + vcn->fw_shared.log_offset; 1251 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG); 1252 fw_log->is_enabled = 1; 1253 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF); 1254 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32); 1255 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE); 1256 1257 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog); 1258 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE; 1259 log_buf->rptr = log_buf->header_size; 1260 log_buf->wptr = log_buf->header_size; 1261 log_buf->wrapped = 0; 1262 #endif 1263 } 1264 1265 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, 1266 struct amdgpu_irq_src *source, 1267 struct amdgpu_iv_entry *entry) 1268 { 1269 struct ras_common_if *ras_if = adev->vcn.ras_if; 1270 struct ras_dispatch_if ih_data = { 1271 .entry = entry, 1272 }; 1273 1274 if (!ras_if) 1275 return 0; 1276 1277 if (!amdgpu_sriov_vf(adev)) { 1278 ih_data.head = *ras_if; 1279 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 1280 } else { 1281 if (adev->virt.ops && adev->virt.ops->ras_poison_handler) 1282 adev->virt.ops->ras_poison_handler(adev, ras_if->block); 1283 else 1284 dev_warn(adev->dev, 1285 "No ras_poison_handler interface in SRIOV for VCN!\n"); 1286 } 1287 1288 return 0; 1289 } 1290 1291 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1292 { 1293 int r, i; 1294 1295 r = amdgpu_ras_block_late_init(adev, ras_block); 1296 if (r) 1297 return r; 1298 1299 if (amdgpu_ras_is_supported(adev, ras_block->block)) { 1300 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1301 if (adev->vcn.harvest_config & (1 << i) || 1302 !adev->vcn.inst[i].ras_poison_irq.funcs) 1303 continue; 1304 1305 r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0); 1306 if (r) 1307 goto late_fini; 1308 } 1309 } 1310 return 0; 1311 1312 late_fini: 1313 amdgpu_ras_block_late_fini(adev, ras_block); 1314 return r; 1315 } 1316 1317 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev) 1318 { 1319 int err; 1320 struct amdgpu_vcn_ras *ras; 1321 1322 if (!adev->vcn.ras) 1323 return 0; 1324 1325 ras = adev->vcn.ras; 1326 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 1327 if (err) { 1328 dev_err(adev->dev, "Failed to register vcn ras block!\n"); 1329 return err; 1330 } 1331 1332 strcpy(ras->ras_block.ras_comm.name, "vcn"); 1333 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; 1334 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; 1335 adev->vcn.ras_if = &ras->ras_block.ras_comm; 1336 1337 if (!ras->ras_block.ras_late_init) 1338 ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init; 1339 1340 return 0; 1341 } 1342 1343 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, 1344 enum AMDGPU_UCODE_ID ucode_id) 1345 { 1346 struct amdgpu_firmware_info ucode = { 1347 .ucode_id = (ucode_id ? ucode_id : 1348 (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 1349 AMDGPU_UCODE_ID_VCN0_RAM)), 1350 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1351 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1352 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr), 1353 }; 1354 1355 return psp_execute_ip_fw_load(&adev->psp, &ucode); 1356 } 1357 1358 static ssize_t amdgpu_get_vcn_reset_mask(struct device *dev, 1359 struct device_attribute *attr, 1360 char *buf) 1361 { 1362 struct drm_device *ddev = dev_get_drvdata(dev); 1363 struct amdgpu_device *adev = drm_to_adev(ddev); 1364 1365 if (!adev) 1366 return -ENODEV; 1367 1368 return amdgpu_show_reset_mask(buf, adev->vcn.supported_reset); 1369 } 1370 1371 static DEVICE_ATTR(vcn_reset_mask, 0444, 1372 amdgpu_get_vcn_reset_mask, NULL); 1373 1374 int amdgpu_vcn_sysfs_reset_mask_init(struct amdgpu_device *adev) 1375 { 1376 int r = 0; 1377 1378 if (adev->vcn.num_vcn_inst) { 1379 r = device_create_file(adev->dev, &dev_attr_vcn_reset_mask); 1380 if (r) 1381 return r; 1382 } 1383 1384 return r; 1385 } 1386 1387 void amdgpu_vcn_sysfs_reset_mask_fini(struct amdgpu_device *adev) 1388 { 1389 if (adev->dev->kobj.sd) { 1390 if (adev->vcn.num_vcn_inst) 1391 device_remove_file(adev->dev, &dev_attr_vcn_reset_mask); 1392 } 1393 } 1394 1395 /* 1396 * debugfs to enable/disable vcn job submission to specific core or 1397 * instance. It is created only if the queue type is unified. 1398 */ 1399 #if defined(CONFIG_DEBUG_FS) 1400 static int amdgpu_debugfs_vcn_sched_mask_set(void *data, u64 val) 1401 { 1402 struct amdgpu_device *adev = (struct amdgpu_device *)data; 1403 u32 i; 1404 u64 mask; 1405 struct amdgpu_ring *ring; 1406 1407 if (!adev) 1408 return -ENODEV; 1409 1410 mask = (1ULL << adev->vcn.num_vcn_inst) - 1; 1411 if ((val & mask) == 0) 1412 return -EINVAL; 1413 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1414 ring = &adev->vcn.inst[i].ring_enc[0]; 1415 if (val & (1ULL << i)) 1416 ring->sched.ready = true; 1417 else 1418 ring->sched.ready = false; 1419 } 1420 /* publish sched.ready flag update effective immediately across smp */ 1421 smp_rmb(); 1422 return 0; 1423 } 1424 1425 static int amdgpu_debugfs_vcn_sched_mask_get(void *data, u64 *val) 1426 { 1427 struct amdgpu_device *adev = (struct amdgpu_device *)data; 1428 u32 i; 1429 u64 mask = 0; 1430 struct amdgpu_ring *ring; 1431 1432 if (!adev) 1433 return -ENODEV; 1434 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1435 ring = &adev->vcn.inst[i].ring_enc[0]; 1436 if (ring->sched.ready) 1437 mask |= 1ULL << i; 1438 } 1439 *val = mask; 1440 return 0; 1441 } 1442 1443 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_vcn_sched_mask_fops, 1444 amdgpu_debugfs_vcn_sched_mask_get, 1445 amdgpu_debugfs_vcn_sched_mask_set, "%llx\n"); 1446 #endif 1447 1448 void amdgpu_debugfs_vcn_sched_mask_init(struct amdgpu_device *adev) 1449 { 1450 #if defined(CONFIG_DEBUG_FS) 1451 struct drm_minor *minor = adev_to_drm(adev)->primary; 1452 struct dentry *root = minor->debugfs_root; 1453 char name[32]; 1454 1455 if (adev->vcn.num_vcn_inst <= 1 || !adev->vcn.inst[0].using_unified_queue) 1456 return; 1457 sprintf(name, "amdgpu_vcn_sched_mask"); 1458 debugfs_create_file(name, 0600, root, adev, 1459 &amdgpu_debugfs_vcn_sched_mask_fops); 1460 #endif 1461 } 1462 1463 /** 1464 * vcn_set_powergating_state - set VCN block powergating state 1465 * 1466 * @ip_block: amdgpu_ip_block pointer 1467 * @state: power gating state 1468 * 1469 * Set VCN block powergating state 1470 */ 1471 int vcn_set_powergating_state(struct amdgpu_ip_block *ip_block, 1472 enum amd_powergating_state state) 1473 { 1474 struct amdgpu_device *adev = ip_block->adev; 1475 int ret = 0, i; 1476 1477 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1478 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1479 1480 ret |= vinst->set_pg_state(vinst, state); 1481 } 1482 1483 return ret; 1484 } 1485 1486 static struct amdgpu_fence * 1487 amdgpu_vcn_ring_reset_begin_helper(struct amdgpu_ring *ring, 1488 struct amdgpu_ring *guilty_ring, 1489 struct amdgpu_fence *timedout_fence) 1490 { 1491 struct amdgpu_fence *fence; 1492 1493 drm_sched_wqueue_stop(&ring->sched); 1494 if (ring == guilty_ring) 1495 fence = timedout_fence; 1496 else 1497 fence = amdgpu_ring_find_guilty_fence(ring); 1498 amdgpu_ring_reset_helper_begin(ring, fence); 1499 1500 return fence; 1501 } 1502 1503 static int 1504 amdgpu_vcn_ring_reset_end_helper(struct amdgpu_ring *ring, 1505 struct amdgpu_fence *fence) 1506 { 1507 int r; 1508 1509 r = amdgpu_ring_reset_helper_end(ring, fence); 1510 if (r) 1511 return r; 1512 1513 drm_sched_wqueue_start(&ring->sched); 1514 return 0; 1515 } 1516 1517 /** 1518 * amdgpu_vcn_ring_reset - Reset a VCN ring 1519 * @ring: ring to reset 1520 * @vmid: vmid of guilty job 1521 * @timedout_fence: fence of timed out job 1522 * 1523 * This helper is for VCN blocks without unified queues because 1524 * resetting the engine resets all queues in that case. With 1525 * unified queues we have one queue per engine. 1526 * Returns: 0 on success, or a negative error code on failure. 1527 */ 1528 int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring, 1529 unsigned int vmid, 1530 struct amdgpu_fence *timedout_fence) 1531 { 1532 struct amdgpu_device *adev = ring->adev; 1533 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1534 struct amdgpu_fence *dec_fence; 1535 struct amdgpu_fence *enc_fence[AMDGPU_VCN_MAX_ENC_RINGS]; 1536 int r, i; 1537 1538 if (adev->vcn.inst[ring->me].using_unified_queue) 1539 return -EINVAL; 1540 1541 mutex_lock(&vinst->engine_reset_mutex); 1542 dec_fence = amdgpu_vcn_ring_reset_begin_helper(&vinst->ring_dec, ring, 1543 timedout_fence); 1544 for (i = 0; i < vinst->num_enc_rings; i++) 1545 enc_fence[i] = amdgpu_vcn_ring_reset_begin_helper(&vinst->ring_enc[i], ring, 1546 timedout_fence); 1547 1548 /* Perform the VCN reset for the specified instance */ 1549 r = vinst->reset(vinst); 1550 if (r) 1551 goto unlock; 1552 1553 r = amdgpu_vcn_ring_reset_end_helper(&vinst->ring_dec, dec_fence); 1554 if (r) 1555 goto unlock; 1556 for (i = 0; i < vinst->num_enc_rings; i++) { 1557 r = amdgpu_vcn_ring_reset_end_helper(&vinst->ring_enc[i], enc_fence[i]); 1558 if (r) 1559 goto unlock; 1560 } 1561 unlock: 1562 mutex_unlock(&vinst->engine_reset_mutex); 1563 1564 return r; 1565 } 1566 1567 int amdgpu_vcn_reg_dump_init(struct amdgpu_device *adev, 1568 const struct amdgpu_hwip_reg_entry *reg, u32 count) 1569 { 1570 adev->vcn.ip_dump = kcalloc(adev->vcn.num_vcn_inst * count, 1571 sizeof(uint32_t), GFP_KERNEL); 1572 if (!adev->vcn.ip_dump) 1573 return -ENOMEM; 1574 adev->vcn.reg_list = reg; 1575 adev->vcn.reg_count = count; 1576 1577 return 0; 1578 } 1579 1580 static void amdgpu_vcn_reg_dump_fini(struct amdgpu_device *adev) 1581 { 1582 kfree(adev->vcn.ip_dump); 1583 adev->vcn.ip_dump = NULL; 1584 adev->vcn.reg_list = NULL; 1585 adev->vcn.reg_count = 0; 1586 } 1587 1588 void amdgpu_vcn_dump_ip_state(struct amdgpu_ip_block *ip_block) 1589 { 1590 struct amdgpu_device *adev = ip_block->adev; 1591 int i, j; 1592 bool is_powered; 1593 u32 inst_off; 1594 1595 if (!adev->vcn.ip_dump) 1596 return; 1597 1598 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1599 if (adev->vcn.harvest_config & (1 << i)) 1600 continue; 1601 1602 inst_off = i * adev->vcn.reg_count; 1603 /* mmUVD_POWER_STATUS is always readable and is the first in reg_list */ 1604 adev->vcn.ip_dump[inst_off] = 1605 RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->vcn.reg_list[0], i)); 1606 is_powered = (adev->vcn.ip_dump[inst_off] & 1607 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF) != 1608 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 1609 1610 if (is_powered) 1611 for (j = 1; j < adev->vcn.reg_count; j++) 1612 adev->vcn.ip_dump[inst_off + j] = 1613 RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->vcn.reg_list[j], i)); 1614 } 1615 } 1616 1617 void amdgpu_vcn_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1618 { 1619 struct amdgpu_device *adev = ip_block->adev; 1620 int i, j; 1621 bool is_powered; 1622 u32 inst_off; 1623 1624 if (!adev->vcn.ip_dump) 1625 return; 1626 1627 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 1628 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1629 if (adev->vcn.harvest_config & (1 << i)) { 1630 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 1631 continue; 1632 } 1633 1634 inst_off = i * adev->vcn.reg_count; 1635 is_powered = (adev->vcn.ip_dump[inst_off] & 1636 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF) != 1637 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 1638 1639 if (is_powered) { 1640 drm_printf(p, "\nActive Instance:VCN%d\n", i); 1641 for (j = 0; j < adev->vcn.reg_count; j++) 1642 drm_printf(p, "%-50s \t 0x%08x\n", adev->vcn.reg_list[j].reg_name, 1643 adev->vcn.ip_dump[inst_off + j]); 1644 } else { 1645 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 1646 } 1647 } 1648 } 1649