1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/dmi.h> 30 #include <linux/pci.h> 31 #include <linux/debugfs.h> 32 #include <drm/drm_drv.h> 33 34 #include "amdgpu.h" 35 #include "amdgpu_pm.h" 36 #include "amdgpu_vcn.h" 37 #include "soc15d.h" 38 39 /* Firmware Names */ 40 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 41 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 42 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 43 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 44 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 45 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 46 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 47 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 48 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 49 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 50 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 51 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 52 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 53 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 54 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 55 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 56 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin" 57 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin" 58 #define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin" 59 #define FIRMWARE_VCN4_0_3 "amdgpu/vcn_4_0_3.bin" 60 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin" 61 #define FIRMWARE_VCN4_0_5 "amdgpu/vcn_4_0_5.bin" 62 #define FIRMWARE_VCN5_0_0 "amdgpu/vcn_5_0_0.bin" 63 64 MODULE_FIRMWARE(FIRMWARE_RAVEN); 65 MODULE_FIRMWARE(FIRMWARE_PICASSO); 66 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 67 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 68 MODULE_FIRMWARE(FIRMWARE_RENOIR); 69 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 70 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 71 MODULE_FIRMWARE(FIRMWARE_NAVI10); 72 MODULE_FIRMWARE(FIRMWARE_NAVI14); 73 MODULE_FIRMWARE(FIRMWARE_NAVI12); 74 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 75 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 76 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 77 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 78 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 79 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 80 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2); 81 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0); 82 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2); 83 MODULE_FIRMWARE(FIRMWARE_VCN4_0_3); 84 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4); 85 MODULE_FIRMWARE(FIRMWARE_VCN4_0_5); 86 MODULE_FIRMWARE(FIRMWARE_VCN5_0_0); 87 88 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 89 90 int amdgpu_vcn_early_init(struct amdgpu_device *adev) 91 { 92 char ucode_prefix[30]; 93 char fw_name[40]; 94 int r; 95 96 amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix)); 97 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); 98 r = amdgpu_ucode_request(adev, &adev->vcn.fw, fw_name); 99 if (r) 100 amdgpu_ucode_release(&adev->vcn.fw); 101 102 return r; 103 } 104 105 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 106 { 107 unsigned long bo_size; 108 const struct common_firmware_header *hdr; 109 unsigned char fw_check; 110 unsigned int fw_shared_size, log_offset; 111 int i, r; 112 113 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 114 mutex_init(&adev->vcn.vcn_pg_lock); 115 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 116 atomic_set(&adev->vcn.total_submission_cnt, 0); 117 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 118 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 119 120 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 121 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 122 adev->vcn.indirect_sram = true; 123 124 /* 125 * Some Steam Deck's BIOS versions are incompatible with the 126 * indirect SRAM mode, leading to amdgpu being unable to get 127 * properly probed (and even potentially crashing the kernel). 128 * Hence, check for these versions here - notice this is 129 * restricted to Vangogh (Deck's APU). 130 */ 131 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 0, 2)) { 132 const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION); 133 134 if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) || 135 !strncmp("F7A0114", bios_ver, 7))) { 136 adev->vcn.indirect_sram = false; 137 dev_info(adev->dev, 138 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver); 139 } 140 } 141 142 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 143 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 144 145 /* Bit 20-23, it is encode major and non-zero for new naming convention. 146 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 147 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 148 * is zero in old naming convention, this field is always zero so far. 149 * These four bits are used to tell which naming convention is present. 150 */ 151 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 152 if (fw_check) { 153 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 154 155 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 156 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 157 enc_major = fw_check; 158 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 159 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 160 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 161 enc_major, enc_minor, dec_ver, vep, fw_rev); 162 } else { 163 unsigned int version_major, version_minor, family_id; 164 165 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 166 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 167 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 168 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 169 version_major, version_minor, family_id); 170 } 171 172 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 173 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 174 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 175 176 if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) { 177 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); 178 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log); 179 } else { 180 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 181 log_offset = offsetof(struct amdgpu_fw_shared, fw_log); 182 } 183 184 bo_size += fw_shared_size; 185 186 if (amdgpu_vcnfw_log) 187 bo_size += AMDGPU_VCNFW_LOG_SIZE; 188 189 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 190 if (adev->vcn.harvest_config & (1 << i)) 191 continue; 192 193 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 194 AMDGPU_GEM_DOMAIN_VRAM | 195 AMDGPU_GEM_DOMAIN_GTT, 196 &adev->vcn.inst[i].vcpu_bo, 197 &adev->vcn.inst[i].gpu_addr, 198 &adev->vcn.inst[i].cpu_addr); 199 if (r) { 200 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 201 return r; 202 } 203 204 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr + 205 bo_size - fw_shared_size; 206 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr + 207 bo_size - fw_shared_size; 208 209 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size; 210 211 if (amdgpu_vcnfw_log) { 212 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 213 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 214 adev->vcn.inst[i].fw_shared.log_offset = log_offset; 215 } 216 217 if (adev->vcn.indirect_sram) { 218 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 219 AMDGPU_GEM_DOMAIN_VRAM | 220 AMDGPU_GEM_DOMAIN_GTT, 221 &adev->vcn.inst[i].dpg_sram_bo, 222 &adev->vcn.inst[i].dpg_sram_gpu_addr, 223 &adev->vcn.inst[i].dpg_sram_cpu_addr); 224 if (r) { 225 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 226 return r; 227 } 228 } 229 } 230 231 return 0; 232 } 233 234 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 235 { 236 int i, j; 237 238 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 239 if (adev->vcn.harvest_config & (1 << j)) 240 continue; 241 242 amdgpu_bo_free_kernel( 243 &adev->vcn.inst[j].dpg_sram_bo, 244 &adev->vcn.inst[j].dpg_sram_gpu_addr, 245 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 246 247 kvfree(adev->vcn.inst[j].saved_bo); 248 249 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 250 &adev->vcn.inst[j].gpu_addr, 251 (void **)&adev->vcn.inst[j].cpu_addr); 252 253 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 254 255 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 256 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 257 } 258 259 amdgpu_ucode_release(&adev->vcn.fw); 260 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 261 mutex_destroy(&adev->vcn.vcn_pg_lock); 262 263 return 0; 264 } 265 266 /* from vcn4 and above, only unified queue is used */ 267 static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring) 268 { 269 struct amdgpu_device *adev = ring->adev; 270 bool ret = false; 271 272 if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) 273 ret = true; 274 275 return ret; 276 } 277 278 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 279 { 280 bool ret = false; 281 int vcn_config = adev->vcn.vcn_config[vcn_instance]; 282 283 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) 284 ret = true; 285 else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) 286 ret = true; 287 else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) 288 ret = true; 289 290 return ret; 291 } 292 293 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 294 { 295 unsigned int size; 296 void *ptr; 297 int i, idx; 298 299 bool in_ras_intr = amdgpu_ras_intr_triggered(); 300 301 cancel_delayed_work_sync(&adev->vcn.idle_work); 302 303 /* err_event_athub will corrupt VCPU buffer, so we need to 304 * restore fw data and clear buffer in amdgpu_vcn_resume() */ 305 if (in_ras_intr) 306 return 0; 307 308 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 309 if (adev->vcn.harvest_config & (1 << i)) 310 continue; 311 if (adev->vcn.inst[i].vcpu_bo == NULL) 312 return 0; 313 314 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 315 ptr = adev->vcn.inst[i].cpu_addr; 316 317 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 318 if (!adev->vcn.inst[i].saved_bo) 319 return -ENOMEM; 320 321 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 322 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 323 drm_dev_exit(idx); 324 } 325 } 326 return 0; 327 } 328 329 int amdgpu_vcn_resume(struct amdgpu_device *adev) 330 { 331 unsigned int size; 332 void *ptr; 333 int i, idx; 334 335 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 336 if (adev->vcn.harvest_config & (1 << i)) 337 continue; 338 if (adev->vcn.inst[i].vcpu_bo == NULL) 339 return -EINVAL; 340 341 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 342 ptr = adev->vcn.inst[i].cpu_addr; 343 344 if (adev->vcn.inst[i].saved_bo != NULL) { 345 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 346 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 347 drm_dev_exit(idx); 348 } 349 kvfree(adev->vcn.inst[i].saved_bo); 350 adev->vcn.inst[i].saved_bo = NULL; 351 } else { 352 const struct common_firmware_header *hdr; 353 unsigned int offset; 354 355 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 356 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 357 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 358 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 359 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 360 le32_to_cpu(hdr->ucode_size_bytes)); 361 drm_dev_exit(idx); 362 } 363 size -= le32_to_cpu(hdr->ucode_size_bytes); 364 ptr += le32_to_cpu(hdr->ucode_size_bytes); 365 } 366 memset_io(ptr, 0, size); 367 } 368 } 369 return 0; 370 } 371 372 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 373 { 374 struct amdgpu_device *adev = 375 container_of(work, struct amdgpu_device, vcn.idle_work.work); 376 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 377 unsigned int i, j; 378 int r = 0; 379 380 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 381 if (adev->vcn.harvest_config & (1 << j)) 382 continue; 383 384 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 385 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 386 387 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 388 struct dpg_pause_state new_state; 389 390 if (fence[j] || 391 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 392 new_state.fw_based = VCN_DPG_STATE__PAUSE; 393 else 394 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 395 396 adev->vcn.pause_dpg_mode(adev, j, &new_state); 397 } 398 399 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 400 fences += fence[j]; 401 } 402 403 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 404 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 405 AMD_PG_STATE_GATE); 406 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 407 false); 408 if (r) 409 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 410 } else { 411 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 412 } 413 } 414 415 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 416 { 417 struct amdgpu_device *adev = ring->adev; 418 int r = 0; 419 420 atomic_inc(&adev->vcn.total_submission_cnt); 421 422 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 423 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 424 true); 425 if (r) 426 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 427 } 428 429 mutex_lock(&adev->vcn.vcn_pg_lock); 430 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 431 AMD_PG_STATE_UNGATE); 432 433 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 434 struct dpg_pause_state new_state; 435 436 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 437 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 438 new_state.fw_based = VCN_DPG_STATE__PAUSE; 439 } else { 440 unsigned int fences = 0; 441 unsigned int i; 442 443 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 444 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 445 446 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 447 new_state.fw_based = VCN_DPG_STATE__PAUSE; 448 else 449 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 450 } 451 452 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 453 } 454 mutex_unlock(&adev->vcn.vcn_pg_lock); 455 } 456 457 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 458 { 459 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 460 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 461 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 462 463 atomic_dec(&ring->adev->vcn.total_submission_cnt); 464 465 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 466 } 467 468 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 469 { 470 struct amdgpu_device *adev = ring->adev; 471 uint32_t tmp = 0; 472 unsigned int i; 473 int r; 474 475 /* VCN in SRIOV does not support direct register read/write */ 476 if (amdgpu_sriov_vf(adev)) 477 return 0; 478 479 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 480 r = amdgpu_ring_alloc(ring, 3); 481 if (r) 482 return r; 483 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 484 amdgpu_ring_write(ring, 0xDEADBEEF); 485 amdgpu_ring_commit(ring); 486 for (i = 0; i < adev->usec_timeout; i++) { 487 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 488 if (tmp == 0xDEADBEEF) 489 break; 490 udelay(1); 491 } 492 493 if (i >= adev->usec_timeout) 494 r = -ETIMEDOUT; 495 496 return r; 497 } 498 499 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 500 { 501 struct amdgpu_device *adev = ring->adev; 502 uint32_t rptr; 503 unsigned int i; 504 int r; 505 506 if (amdgpu_sriov_vf(adev)) 507 return 0; 508 509 r = amdgpu_ring_alloc(ring, 16); 510 if (r) 511 return r; 512 513 rptr = amdgpu_ring_get_rptr(ring); 514 515 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 516 amdgpu_ring_commit(ring); 517 518 for (i = 0; i < adev->usec_timeout; i++) { 519 if (amdgpu_ring_get_rptr(ring) != rptr) 520 break; 521 udelay(1); 522 } 523 524 if (i >= adev->usec_timeout) 525 r = -ETIMEDOUT; 526 527 return r; 528 } 529 530 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 531 struct amdgpu_ib *ib_msg, 532 struct dma_fence **fence) 533 { 534 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 535 struct amdgpu_device *adev = ring->adev; 536 struct dma_fence *f = NULL; 537 struct amdgpu_job *job; 538 struct amdgpu_ib *ib; 539 int i, r; 540 541 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 542 64, AMDGPU_IB_POOL_DIRECT, 543 &job); 544 if (r) 545 goto err; 546 547 ib = &job->ibs[0]; 548 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 549 ib->ptr[1] = addr; 550 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 551 ib->ptr[3] = addr >> 32; 552 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 553 ib->ptr[5] = 0; 554 for (i = 6; i < 16; i += 2) { 555 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 556 ib->ptr[i+1] = 0; 557 } 558 ib->length_dw = 16; 559 560 r = amdgpu_job_submit_direct(job, ring, &f); 561 if (r) 562 goto err_free; 563 564 amdgpu_ib_free(adev, ib_msg, f); 565 566 if (fence) 567 *fence = dma_fence_get(f); 568 dma_fence_put(f); 569 570 return 0; 571 572 err_free: 573 amdgpu_job_free(job); 574 err: 575 amdgpu_ib_free(adev, ib_msg, f); 576 return r; 577 } 578 579 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 580 struct amdgpu_ib *ib) 581 { 582 struct amdgpu_device *adev = ring->adev; 583 uint32_t *msg; 584 int r, i; 585 586 memset(ib, 0, sizeof(*ib)); 587 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 588 AMDGPU_IB_POOL_DIRECT, 589 ib); 590 if (r) 591 return r; 592 593 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 594 msg[0] = cpu_to_le32(0x00000028); 595 msg[1] = cpu_to_le32(0x00000038); 596 msg[2] = cpu_to_le32(0x00000001); 597 msg[3] = cpu_to_le32(0x00000000); 598 msg[4] = cpu_to_le32(handle); 599 msg[5] = cpu_to_le32(0x00000000); 600 msg[6] = cpu_to_le32(0x00000001); 601 msg[7] = cpu_to_le32(0x00000028); 602 msg[8] = cpu_to_le32(0x00000010); 603 msg[9] = cpu_to_le32(0x00000000); 604 msg[10] = cpu_to_le32(0x00000007); 605 msg[11] = cpu_to_le32(0x00000000); 606 msg[12] = cpu_to_le32(0x00000780); 607 msg[13] = cpu_to_le32(0x00000440); 608 for (i = 14; i < 1024; ++i) 609 msg[i] = cpu_to_le32(0x0); 610 611 return 0; 612 } 613 614 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 615 struct amdgpu_ib *ib) 616 { 617 struct amdgpu_device *adev = ring->adev; 618 uint32_t *msg; 619 int r, i; 620 621 memset(ib, 0, sizeof(*ib)); 622 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 623 AMDGPU_IB_POOL_DIRECT, 624 ib); 625 if (r) 626 return r; 627 628 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 629 msg[0] = cpu_to_le32(0x00000028); 630 msg[1] = cpu_to_le32(0x00000018); 631 msg[2] = cpu_to_le32(0x00000000); 632 msg[3] = cpu_to_le32(0x00000002); 633 msg[4] = cpu_to_le32(handle); 634 msg[5] = cpu_to_le32(0x00000000); 635 for (i = 6; i < 1024; ++i) 636 msg[i] = cpu_to_le32(0x0); 637 638 return 0; 639 } 640 641 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 642 { 643 struct dma_fence *fence = NULL; 644 struct amdgpu_ib ib; 645 long r; 646 647 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 648 if (r) 649 goto error; 650 651 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 652 if (r) 653 goto error; 654 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 655 if (r) 656 goto error; 657 658 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 659 if (r) 660 goto error; 661 662 r = dma_fence_wait_timeout(fence, false, timeout); 663 if (r == 0) 664 r = -ETIMEDOUT; 665 else if (r > 0) 666 r = 0; 667 668 dma_fence_put(fence); 669 error: 670 return r; 671 } 672 673 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, 674 uint32_t ib_pack_in_dw, bool enc) 675 { 676 uint32_t *ib_checksum; 677 678 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */ 679 ib->ptr[ib->length_dw++] = 0x30000002; 680 ib_checksum = &ib->ptr[ib->length_dw++]; 681 ib->ptr[ib->length_dw++] = ib_pack_in_dw; 682 683 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */ 684 ib->ptr[ib->length_dw++] = 0x30000001; 685 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3; 686 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t); 687 688 return ib_checksum; 689 } 690 691 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum, 692 uint32_t ib_pack_in_dw) 693 { 694 uint32_t i; 695 uint32_t checksum = 0; 696 697 for (i = 0; i < ib_pack_in_dw; i++) 698 checksum += *(*ib_checksum + 2 + i); 699 700 **ib_checksum = checksum; 701 } 702 703 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 704 struct amdgpu_ib *ib_msg, 705 struct dma_fence **fence) 706 { 707 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 708 unsigned int ib_size_dw = 64; 709 struct amdgpu_device *adev = ring->adev; 710 struct dma_fence *f = NULL; 711 struct amdgpu_job *job; 712 struct amdgpu_ib *ib; 713 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 714 bool sq = amdgpu_vcn_using_unified_queue(ring); 715 uint32_t *ib_checksum; 716 uint32_t ib_pack_in_dw; 717 int i, r; 718 719 if (sq) 720 ib_size_dw += 8; 721 722 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 723 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 724 &job); 725 if (r) 726 goto err; 727 728 ib = &job->ibs[0]; 729 ib->length_dw = 0; 730 731 /* single queue headers */ 732 if (sq) { 733 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t) 734 + 4 + 2; /* engine info + decoding ib in dw */ 735 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false); 736 } 737 738 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 739 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 740 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 741 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 742 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 743 744 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 745 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 746 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 747 748 for (i = ib->length_dw; i < ib_size_dw; ++i) 749 ib->ptr[i] = 0x0; 750 751 if (sq) 752 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw); 753 754 r = amdgpu_job_submit_direct(job, ring, &f); 755 if (r) 756 goto err_free; 757 758 amdgpu_ib_free(adev, ib_msg, f); 759 760 if (fence) 761 *fence = dma_fence_get(f); 762 dma_fence_put(f); 763 764 return 0; 765 766 err_free: 767 amdgpu_job_free(job); 768 err: 769 amdgpu_ib_free(adev, ib_msg, f); 770 return r; 771 } 772 773 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 774 { 775 struct dma_fence *fence = NULL; 776 struct amdgpu_ib ib; 777 long r; 778 779 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 780 if (r) 781 goto error; 782 783 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 784 if (r) 785 goto error; 786 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 787 if (r) 788 goto error; 789 790 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 791 if (r) 792 goto error; 793 794 r = dma_fence_wait_timeout(fence, false, timeout); 795 if (r == 0) 796 r = -ETIMEDOUT; 797 else if (r > 0) 798 r = 0; 799 800 dma_fence_put(fence); 801 error: 802 return r; 803 } 804 805 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 806 { 807 struct amdgpu_device *adev = ring->adev; 808 uint32_t rptr; 809 unsigned int i; 810 int r; 811 812 if (amdgpu_sriov_vf(adev)) 813 return 0; 814 815 r = amdgpu_ring_alloc(ring, 16); 816 if (r) 817 return r; 818 819 rptr = amdgpu_ring_get_rptr(ring); 820 821 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 822 amdgpu_ring_commit(ring); 823 824 for (i = 0; i < adev->usec_timeout; i++) { 825 if (amdgpu_ring_get_rptr(ring) != rptr) 826 break; 827 udelay(1); 828 } 829 830 if (i >= adev->usec_timeout) 831 r = -ETIMEDOUT; 832 833 return r; 834 } 835 836 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 837 struct amdgpu_ib *ib_msg, 838 struct dma_fence **fence) 839 { 840 unsigned int ib_size_dw = 16; 841 struct amdgpu_job *job; 842 struct amdgpu_ib *ib; 843 struct dma_fence *f = NULL; 844 uint32_t *ib_checksum = NULL; 845 uint64_t addr; 846 bool sq = amdgpu_vcn_using_unified_queue(ring); 847 int i, r; 848 849 if (sq) 850 ib_size_dw += 8; 851 852 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 853 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 854 &job); 855 if (r) 856 return r; 857 858 ib = &job->ibs[0]; 859 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 860 861 ib->length_dw = 0; 862 863 if (sq) 864 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 865 866 ib->ptr[ib->length_dw++] = 0x00000018; 867 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 868 ib->ptr[ib->length_dw++] = handle; 869 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 870 ib->ptr[ib->length_dw++] = addr; 871 ib->ptr[ib->length_dw++] = 0x0000000b; 872 873 ib->ptr[ib->length_dw++] = 0x00000014; 874 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 875 ib->ptr[ib->length_dw++] = 0x0000001c; 876 ib->ptr[ib->length_dw++] = 0x00000000; 877 ib->ptr[ib->length_dw++] = 0x00000000; 878 879 ib->ptr[ib->length_dw++] = 0x00000008; 880 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 881 882 for (i = ib->length_dw; i < ib_size_dw; ++i) 883 ib->ptr[i] = 0x0; 884 885 if (sq) 886 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 887 888 r = amdgpu_job_submit_direct(job, ring, &f); 889 if (r) 890 goto err; 891 892 if (fence) 893 *fence = dma_fence_get(f); 894 dma_fence_put(f); 895 896 return 0; 897 898 err: 899 amdgpu_job_free(job); 900 return r; 901 } 902 903 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 904 struct amdgpu_ib *ib_msg, 905 struct dma_fence **fence) 906 { 907 unsigned int ib_size_dw = 16; 908 struct amdgpu_job *job; 909 struct amdgpu_ib *ib; 910 struct dma_fence *f = NULL; 911 uint32_t *ib_checksum = NULL; 912 uint64_t addr; 913 bool sq = amdgpu_vcn_using_unified_queue(ring); 914 int i, r; 915 916 if (sq) 917 ib_size_dw += 8; 918 919 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 920 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 921 &job); 922 if (r) 923 return r; 924 925 ib = &job->ibs[0]; 926 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 927 928 ib->length_dw = 0; 929 930 if (sq) 931 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 932 933 ib->ptr[ib->length_dw++] = 0x00000018; 934 ib->ptr[ib->length_dw++] = 0x00000001; 935 ib->ptr[ib->length_dw++] = handle; 936 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 937 ib->ptr[ib->length_dw++] = addr; 938 ib->ptr[ib->length_dw++] = 0x0000000b; 939 940 ib->ptr[ib->length_dw++] = 0x00000014; 941 ib->ptr[ib->length_dw++] = 0x00000002; 942 ib->ptr[ib->length_dw++] = 0x0000001c; 943 ib->ptr[ib->length_dw++] = 0x00000000; 944 ib->ptr[ib->length_dw++] = 0x00000000; 945 946 ib->ptr[ib->length_dw++] = 0x00000008; 947 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 948 949 for (i = ib->length_dw; i < ib_size_dw; ++i) 950 ib->ptr[i] = 0x0; 951 952 if (sq) 953 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 954 955 r = amdgpu_job_submit_direct(job, ring, &f); 956 if (r) 957 goto err; 958 959 if (fence) 960 *fence = dma_fence_get(f); 961 dma_fence_put(f); 962 963 return 0; 964 965 err: 966 amdgpu_job_free(job); 967 return r; 968 } 969 970 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 971 { 972 struct amdgpu_device *adev = ring->adev; 973 struct dma_fence *fence = NULL; 974 struct amdgpu_ib ib; 975 long r; 976 977 memset(&ib, 0, sizeof(ib)); 978 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 979 AMDGPU_IB_POOL_DIRECT, 980 &ib); 981 if (r) 982 return r; 983 984 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 985 if (r) 986 goto error; 987 988 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 989 if (r) 990 goto error; 991 992 r = dma_fence_wait_timeout(fence, false, timeout); 993 if (r == 0) 994 r = -ETIMEDOUT; 995 else if (r > 0) 996 r = 0; 997 998 error: 999 amdgpu_ib_free(adev, &ib, fence); 1000 dma_fence_put(fence); 1001 1002 return r; 1003 } 1004 1005 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1006 { 1007 struct amdgpu_device *adev = ring->adev; 1008 long r; 1009 1010 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(4, 0, 3)) { 1011 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout); 1012 if (r) 1013 goto error; 1014 } 1015 1016 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout); 1017 1018 error: 1019 return r; 1020 } 1021 1022 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 1023 { 1024 switch (ring) { 1025 case 0: 1026 return AMDGPU_RING_PRIO_0; 1027 case 1: 1028 return AMDGPU_RING_PRIO_1; 1029 case 2: 1030 return AMDGPU_RING_PRIO_2; 1031 default: 1032 return AMDGPU_RING_PRIO_0; 1033 } 1034 } 1035 1036 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev) 1037 { 1038 int i; 1039 unsigned int idx; 1040 1041 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1042 const struct common_firmware_header *hdr; 1043 1044 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 1045 1046 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1047 if (adev->vcn.harvest_config & (1 << i)) 1048 continue; 1049 /* currently only support 2 FW instances */ 1050 if (i >= 2) { 1051 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 1052 break; 1053 } 1054 idx = AMDGPU_UCODE_ID_VCN + i; 1055 adev->firmware.ucode[idx].ucode_id = idx; 1056 adev->firmware.ucode[idx].fw = adev->vcn.fw; 1057 adev->firmware.fw_size += 1058 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 1059 1060 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == 1061 IP_VERSION(4, 0, 3)) 1062 break; 1063 } 1064 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 1065 } 1066 } 1067 1068 /* 1069 * debugfs for mapping vcn firmware log buffer. 1070 */ 1071 #if defined(CONFIG_DEBUG_FS) 1072 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf, 1073 size_t size, loff_t *pos) 1074 { 1075 struct amdgpu_vcn_inst *vcn; 1076 void *log_buf; 1077 volatile struct amdgpu_vcn_fwlog *plog; 1078 unsigned int read_pos, write_pos, available, i, read_bytes = 0; 1079 unsigned int read_num[2] = {0}; 1080 1081 vcn = file_inode(f)->i_private; 1082 if (!vcn) 1083 return -ENODEV; 1084 1085 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log) 1086 return -EFAULT; 1087 1088 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1089 1090 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf; 1091 read_pos = plog->rptr; 1092 write_pos = plog->wptr; 1093 1094 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE) 1095 return -EFAULT; 1096 1097 if (!size || (read_pos == write_pos)) 1098 return 0; 1099 1100 if (write_pos > read_pos) { 1101 available = write_pos - read_pos; 1102 read_num[0] = min_t(size_t, size, available); 1103 } else { 1104 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos; 1105 available = read_num[0] + write_pos - plog->header_size; 1106 if (size > available) 1107 read_num[1] = write_pos - plog->header_size; 1108 else if (size > read_num[0]) 1109 read_num[1] = size - read_num[0]; 1110 else 1111 read_num[0] = size; 1112 } 1113 1114 for (i = 0; i < 2; i++) { 1115 if (read_num[i]) { 1116 if (read_pos == AMDGPU_VCNFW_LOG_SIZE) 1117 read_pos = plog->header_size; 1118 if (read_num[i] == copy_to_user((buf + read_bytes), 1119 (log_buf + read_pos), read_num[i])) 1120 return -EFAULT; 1121 1122 read_bytes += read_num[i]; 1123 read_pos += read_num[i]; 1124 } 1125 } 1126 1127 plog->rptr = read_pos; 1128 *pos += read_bytes; 1129 return read_bytes; 1130 } 1131 1132 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = { 1133 .owner = THIS_MODULE, 1134 .read = amdgpu_debugfs_vcn_fwlog_read, 1135 .llseek = default_llseek 1136 }; 1137 #endif 1138 1139 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i, 1140 struct amdgpu_vcn_inst *vcn) 1141 { 1142 #if defined(CONFIG_DEBUG_FS) 1143 struct drm_minor *minor = adev_to_drm(adev)->primary; 1144 struct dentry *root = minor->debugfs_root; 1145 char name[32]; 1146 1147 sprintf(name, "amdgpu_vcn_%d_fwlog", i); 1148 debugfs_create_file_size(name, S_IFREG | 0444, root, vcn, 1149 &amdgpu_debugfs_vcnfwlog_fops, 1150 AMDGPU_VCNFW_LOG_SIZE); 1151 #endif 1152 } 1153 1154 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn) 1155 { 1156 #if defined(CONFIG_DEBUG_FS) 1157 volatile uint32_t *flag = vcn->fw_shared.cpu_addr; 1158 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1159 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size; 1160 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr; 1161 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr 1162 + vcn->fw_shared.log_offset; 1163 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG); 1164 fw_log->is_enabled = 1; 1165 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF); 1166 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32); 1167 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE); 1168 1169 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog); 1170 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE; 1171 log_buf->rptr = log_buf->header_size; 1172 log_buf->wptr = log_buf->header_size; 1173 log_buf->wrapped = 0; 1174 #endif 1175 } 1176 1177 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, 1178 struct amdgpu_irq_src *source, 1179 struct amdgpu_iv_entry *entry) 1180 { 1181 struct ras_common_if *ras_if = adev->vcn.ras_if; 1182 struct ras_dispatch_if ih_data = { 1183 .entry = entry, 1184 }; 1185 1186 if (!ras_if) 1187 return 0; 1188 1189 if (!amdgpu_sriov_vf(adev)) { 1190 ih_data.head = *ras_if; 1191 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 1192 } else { 1193 if (adev->virt.ops && adev->virt.ops->ras_poison_handler) 1194 adev->virt.ops->ras_poison_handler(adev, ras_if->block); 1195 else 1196 dev_warn(adev->dev, 1197 "No ras_poison_handler interface in SRIOV for VCN!\n"); 1198 } 1199 1200 return 0; 1201 } 1202 1203 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1204 { 1205 int r, i; 1206 1207 r = amdgpu_ras_block_late_init(adev, ras_block); 1208 if (r) 1209 return r; 1210 1211 if (amdgpu_ras_is_supported(adev, ras_block->block)) { 1212 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1213 if (adev->vcn.harvest_config & (1 << i) || 1214 !adev->vcn.inst[i].ras_poison_irq.funcs) 1215 continue; 1216 1217 r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0); 1218 if (r) 1219 goto late_fini; 1220 } 1221 } 1222 return 0; 1223 1224 late_fini: 1225 amdgpu_ras_block_late_fini(adev, ras_block); 1226 return r; 1227 } 1228 1229 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev) 1230 { 1231 int err; 1232 struct amdgpu_vcn_ras *ras; 1233 1234 if (!adev->vcn.ras) 1235 return 0; 1236 1237 ras = adev->vcn.ras; 1238 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 1239 if (err) { 1240 dev_err(adev->dev, "Failed to register vcn ras block!\n"); 1241 return err; 1242 } 1243 1244 strcpy(ras->ras_block.ras_comm.name, "vcn"); 1245 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; 1246 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; 1247 adev->vcn.ras_if = &ras->ras_block.ras_comm; 1248 1249 if (!ras->ras_block.ras_late_init) 1250 ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init; 1251 1252 return 0; 1253 } 1254 1255 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, 1256 enum AMDGPU_UCODE_ID ucode_id) 1257 { 1258 struct amdgpu_firmware_info ucode = { 1259 .ucode_id = (ucode_id ? ucode_id : 1260 (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 1261 AMDGPU_UCODE_ID_VCN0_RAM)), 1262 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1263 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1264 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr), 1265 }; 1266 1267 return psp_execute_ip_fw_load(&adev->psp, &ucode); 1268 } 1269