1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <drm/drm_drv.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_pm.h" 34 #include "amdgpu_vcn.h" 35 #include "soc15d.h" 36 37 /* Firmware Names */ 38 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 39 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 40 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 41 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 42 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 43 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 44 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 45 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 46 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 47 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 48 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 49 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 50 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 51 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 52 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 53 54 MODULE_FIRMWARE(FIRMWARE_RAVEN); 55 MODULE_FIRMWARE(FIRMWARE_PICASSO); 56 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 57 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 58 MODULE_FIRMWARE(FIRMWARE_RENOIR); 59 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 60 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 61 MODULE_FIRMWARE(FIRMWARE_NAVI10); 62 MODULE_FIRMWARE(FIRMWARE_NAVI14); 63 MODULE_FIRMWARE(FIRMWARE_NAVI12); 64 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 65 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 66 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 67 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 68 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 69 70 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 71 72 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 73 { 74 unsigned long bo_size; 75 const char *fw_name; 76 const struct common_firmware_header *hdr; 77 unsigned char fw_check; 78 int i, r; 79 80 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 81 mutex_init(&adev->vcn.vcn_pg_lock); 82 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 83 atomic_set(&adev->vcn.total_submission_cnt, 0); 84 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 85 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 86 87 switch (adev->asic_type) { 88 case CHIP_RAVEN: 89 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 90 fw_name = FIRMWARE_RAVEN2; 91 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 92 fw_name = FIRMWARE_PICASSO; 93 else 94 fw_name = FIRMWARE_RAVEN; 95 break; 96 case CHIP_ARCTURUS: 97 fw_name = FIRMWARE_ARCTURUS; 98 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 99 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 100 adev->vcn.indirect_sram = true; 101 break; 102 case CHIP_RENOIR: 103 if (adev->apu_flags & AMD_APU_IS_RENOIR) 104 fw_name = FIRMWARE_RENOIR; 105 else 106 fw_name = FIRMWARE_GREEN_SARDINE; 107 108 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 109 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 110 adev->vcn.indirect_sram = true; 111 break; 112 case CHIP_ALDEBARAN: 113 fw_name = FIRMWARE_ALDEBARAN; 114 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 115 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 116 adev->vcn.indirect_sram = true; 117 break; 118 case CHIP_NAVI10: 119 fw_name = FIRMWARE_NAVI10; 120 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 121 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 122 adev->vcn.indirect_sram = true; 123 break; 124 case CHIP_NAVI14: 125 fw_name = FIRMWARE_NAVI14; 126 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 127 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 128 adev->vcn.indirect_sram = true; 129 break; 130 case CHIP_NAVI12: 131 fw_name = FIRMWARE_NAVI12; 132 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 133 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 134 adev->vcn.indirect_sram = true; 135 break; 136 case CHIP_SIENNA_CICHLID: 137 fw_name = FIRMWARE_SIENNA_CICHLID; 138 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 139 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 140 adev->vcn.indirect_sram = true; 141 break; 142 case CHIP_NAVY_FLOUNDER: 143 fw_name = FIRMWARE_NAVY_FLOUNDER; 144 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 145 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 146 adev->vcn.indirect_sram = true; 147 break; 148 case CHIP_VANGOGH: 149 fw_name = FIRMWARE_VANGOGH; 150 break; 151 case CHIP_DIMGREY_CAVEFISH: 152 fw_name = FIRMWARE_DIMGREY_CAVEFISH; 153 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 154 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 155 adev->vcn.indirect_sram = true; 156 break; 157 case CHIP_BEIGE_GOBY: 158 fw_name = FIRMWARE_BEIGE_GOBY; 159 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 160 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 161 adev->vcn.indirect_sram = true; 162 break; 163 default: 164 return -EINVAL; 165 } 166 167 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); 168 if (r) { 169 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", 170 fw_name); 171 return r; 172 } 173 174 r = amdgpu_ucode_validate(adev->vcn.fw); 175 if (r) { 176 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", 177 fw_name); 178 release_firmware(adev->vcn.fw); 179 adev->vcn.fw = NULL; 180 return r; 181 } 182 183 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 184 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 185 186 /* Bit 20-23, it is encode major and non-zero for new naming convention. 187 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 188 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 189 * is zero in old naming convention, this field is always zero so far. 190 * These four bits are used to tell which naming convention is present. 191 */ 192 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 193 if (fw_check) { 194 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 195 196 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 197 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 198 enc_major = fw_check; 199 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 200 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 201 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 202 enc_major, enc_minor, dec_ver, vep, fw_rev); 203 } else { 204 unsigned int version_major, version_minor, family_id; 205 206 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 207 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 208 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 209 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 210 version_major, version_minor, family_id); 211 } 212 213 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 214 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 215 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 216 bo_size += AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 217 218 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 219 if (adev->vcn.harvest_config & (1 << i)) 220 continue; 221 222 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 223 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo, 224 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr); 225 if (r) { 226 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 227 return r; 228 } 229 230 adev->vcn.inst[i].fw_shared_cpu_addr = adev->vcn.inst[i].cpu_addr + 231 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 232 adev->vcn.inst[i].fw_shared_gpu_addr = adev->vcn.inst[i].gpu_addr + 233 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 234 235 if (adev->vcn.indirect_sram) { 236 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 237 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo, 238 &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr); 239 if (r) { 240 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 241 return r; 242 } 243 } 244 } 245 246 return 0; 247 } 248 249 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 250 { 251 int i, j; 252 253 cancel_delayed_work_sync(&adev->vcn.idle_work); 254 255 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 256 if (adev->vcn.harvest_config & (1 << j)) 257 continue; 258 259 if (adev->vcn.indirect_sram) { 260 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo, 261 &adev->vcn.inst[j].dpg_sram_gpu_addr, 262 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 263 } 264 kvfree(adev->vcn.inst[j].saved_bo); 265 266 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 267 &adev->vcn.inst[j].gpu_addr, 268 (void **)&adev->vcn.inst[j].cpu_addr); 269 270 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 271 272 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 273 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 274 } 275 276 release_firmware(adev->vcn.fw); 277 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 278 mutex_destroy(&adev->vcn.vcn_pg_lock); 279 280 return 0; 281 } 282 283 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 284 { 285 unsigned size; 286 void *ptr; 287 int i, idx; 288 289 cancel_delayed_work_sync(&adev->vcn.idle_work); 290 291 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 292 if (adev->vcn.harvest_config & (1 << i)) 293 continue; 294 if (adev->vcn.inst[i].vcpu_bo == NULL) 295 return 0; 296 297 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 298 ptr = adev->vcn.inst[i].cpu_addr; 299 300 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 301 if (!adev->vcn.inst[i].saved_bo) 302 return -ENOMEM; 303 304 if (drm_dev_enter(&adev->ddev, &idx)) { 305 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 306 drm_dev_exit(idx); 307 } 308 } 309 return 0; 310 } 311 312 int amdgpu_vcn_resume(struct amdgpu_device *adev) 313 { 314 unsigned size; 315 void *ptr; 316 int i, idx; 317 318 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 319 if (adev->vcn.harvest_config & (1 << i)) 320 continue; 321 if (adev->vcn.inst[i].vcpu_bo == NULL) 322 return -EINVAL; 323 324 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 325 ptr = adev->vcn.inst[i].cpu_addr; 326 327 if (adev->vcn.inst[i].saved_bo != NULL) { 328 if (drm_dev_enter(&adev->ddev, &idx)) { 329 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 330 drm_dev_exit(idx); 331 } 332 kvfree(adev->vcn.inst[i].saved_bo); 333 adev->vcn.inst[i].saved_bo = NULL; 334 } else { 335 const struct common_firmware_header *hdr; 336 unsigned offset; 337 338 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 339 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 340 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 341 if (drm_dev_enter(&adev->ddev, &idx)) { 342 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 343 le32_to_cpu(hdr->ucode_size_bytes)); 344 drm_dev_exit(idx); 345 } 346 size -= le32_to_cpu(hdr->ucode_size_bytes); 347 ptr += le32_to_cpu(hdr->ucode_size_bytes); 348 } 349 memset_io(ptr, 0, size); 350 } 351 } 352 return 0; 353 } 354 355 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 356 { 357 struct amdgpu_device *adev = 358 container_of(work, struct amdgpu_device, vcn.idle_work.work); 359 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 360 unsigned int i, j; 361 int r = 0; 362 363 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 364 if (adev->vcn.harvest_config & (1 << j)) 365 continue; 366 367 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 368 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 369 } 370 371 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 372 struct dpg_pause_state new_state; 373 374 if (fence[j] || 375 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 376 new_state.fw_based = VCN_DPG_STATE__PAUSE; 377 else 378 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 379 380 adev->vcn.pause_dpg_mode(adev, j, &new_state); 381 } 382 383 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 384 fences += fence[j]; 385 } 386 387 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 388 amdgpu_gfx_off_ctrl(adev, true); 389 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 390 AMD_PG_STATE_GATE); 391 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 392 false); 393 if (r) 394 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 395 } else { 396 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 397 } 398 } 399 400 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 401 { 402 struct amdgpu_device *adev = ring->adev; 403 int r = 0; 404 405 atomic_inc(&adev->vcn.total_submission_cnt); 406 407 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 408 amdgpu_gfx_off_ctrl(adev, false); 409 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 410 true); 411 if (r) 412 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 413 } 414 415 mutex_lock(&adev->vcn.vcn_pg_lock); 416 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 417 AMD_PG_STATE_UNGATE); 418 419 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 420 struct dpg_pause_state new_state; 421 422 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 423 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 424 new_state.fw_based = VCN_DPG_STATE__PAUSE; 425 } else { 426 unsigned int fences = 0; 427 unsigned int i; 428 429 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 430 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 431 432 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 433 new_state.fw_based = VCN_DPG_STATE__PAUSE; 434 else 435 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 436 } 437 438 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 439 } 440 mutex_unlock(&adev->vcn.vcn_pg_lock); 441 } 442 443 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 444 { 445 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 446 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 447 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 448 449 atomic_dec(&ring->adev->vcn.total_submission_cnt); 450 451 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 452 } 453 454 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 455 { 456 struct amdgpu_device *adev = ring->adev; 457 uint32_t tmp = 0; 458 unsigned i; 459 int r; 460 461 /* VCN in SRIOV does not support direct register read/write */ 462 if (amdgpu_sriov_vf(adev)) 463 return 0; 464 465 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 466 r = amdgpu_ring_alloc(ring, 3); 467 if (r) 468 return r; 469 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 470 amdgpu_ring_write(ring, 0xDEADBEEF); 471 amdgpu_ring_commit(ring); 472 for (i = 0; i < adev->usec_timeout; i++) { 473 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 474 if (tmp == 0xDEADBEEF) 475 break; 476 udelay(1); 477 } 478 479 if (i >= adev->usec_timeout) 480 r = -ETIMEDOUT; 481 482 return r; 483 } 484 485 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 486 { 487 struct amdgpu_device *adev = ring->adev; 488 uint32_t rptr; 489 unsigned int i; 490 int r; 491 492 if (amdgpu_sriov_vf(adev)) 493 return 0; 494 495 r = amdgpu_ring_alloc(ring, 16); 496 if (r) 497 return r; 498 499 rptr = amdgpu_ring_get_rptr(ring); 500 501 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 502 amdgpu_ring_commit(ring); 503 504 for (i = 0; i < adev->usec_timeout; i++) { 505 if (amdgpu_ring_get_rptr(ring) != rptr) 506 break; 507 udelay(1); 508 } 509 510 if (i >= adev->usec_timeout) 511 r = -ETIMEDOUT; 512 513 return r; 514 } 515 516 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 517 struct amdgpu_bo *bo, 518 struct dma_fence **fence) 519 { 520 struct amdgpu_device *adev = ring->adev; 521 struct dma_fence *f = NULL; 522 struct amdgpu_job *job; 523 struct amdgpu_ib *ib; 524 uint64_t addr; 525 void *msg = NULL; 526 int i, r; 527 528 r = amdgpu_job_alloc_with_ib(adev, 64, 529 AMDGPU_IB_POOL_DIRECT, &job); 530 if (r) 531 goto err; 532 533 ib = &job->ibs[0]; 534 addr = amdgpu_bo_gpu_offset(bo); 535 msg = amdgpu_bo_kptr(bo); 536 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 537 ib->ptr[1] = addr; 538 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 539 ib->ptr[3] = addr >> 32; 540 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 541 ib->ptr[5] = 0; 542 for (i = 6; i < 16; i += 2) { 543 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 544 ib->ptr[i+1] = 0; 545 } 546 ib->length_dw = 16; 547 548 r = amdgpu_job_submit_direct(job, ring, &f); 549 if (r) 550 goto err_free; 551 552 amdgpu_bo_fence(bo, f, false); 553 amdgpu_bo_unreserve(bo); 554 amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg); 555 556 if (fence) 557 *fence = dma_fence_get(f); 558 dma_fence_put(f); 559 560 return 0; 561 562 err_free: 563 amdgpu_job_free(job); 564 565 err: 566 amdgpu_bo_unreserve(bo); 567 amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg); 568 return r; 569 } 570 571 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 572 struct amdgpu_bo **bo) 573 { 574 struct amdgpu_device *adev = ring->adev; 575 uint32_t *msg; 576 int r, i; 577 578 *bo = NULL; 579 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 580 AMDGPU_GEM_DOMAIN_VRAM, 581 bo, NULL, (void **)&msg); 582 if (r) 583 return r; 584 585 msg[0] = cpu_to_le32(0x00000028); 586 msg[1] = cpu_to_le32(0x00000038); 587 msg[2] = cpu_to_le32(0x00000001); 588 msg[3] = cpu_to_le32(0x00000000); 589 msg[4] = cpu_to_le32(handle); 590 msg[5] = cpu_to_le32(0x00000000); 591 msg[6] = cpu_to_le32(0x00000001); 592 msg[7] = cpu_to_le32(0x00000028); 593 msg[8] = cpu_to_le32(0x00000010); 594 msg[9] = cpu_to_le32(0x00000000); 595 msg[10] = cpu_to_le32(0x00000007); 596 msg[11] = cpu_to_le32(0x00000000); 597 msg[12] = cpu_to_le32(0x00000780); 598 msg[13] = cpu_to_le32(0x00000440); 599 for (i = 14; i < 1024; ++i) 600 msg[i] = cpu_to_le32(0x0); 601 602 return 0; 603 } 604 605 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 606 struct amdgpu_bo **bo) 607 { 608 struct amdgpu_device *adev = ring->adev; 609 uint32_t *msg; 610 int r, i; 611 612 *bo = NULL; 613 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 614 AMDGPU_GEM_DOMAIN_VRAM, 615 bo, NULL, (void **)&msg); 616 if (r) 617 return r; 618 619 msg[0] = cpu_to_le32(0x00000028); 620 msg[1] = cpu_to_le32(0x00000018); 621 msg[2] = cpu_to_le32(0x00000000); 622 msg[3] = cpu_to_le32(0x00000002); 623 msg[4] = cpu_to_le32(handle); 624 msg[5] = cpu_to_le32(0x00000000); 625 for (i = 6; i < 1024; ++i) 626 msg[i] = cpu_to_le32(0x0); 627 628 return 0; 629 } 630 631 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 632 { 633 struct dma_fence *fence = NULL; 634 struct amdgpu_bo *bo; 635 long r; 636 637 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo); 638 if (r) 639 goto error; 640 641 r = amdgpu_vcn_dec_send_msg(ring, bo, NULL); 642 if (r) 643 goto error; 644 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo); 645 if (r) 646 goto error; 647 648 r = amdgpu_vcn_dec_send_msg(ring, bo, &fence); 649 if (r) 650 goto error; 651 652 r = dma_fence_wait_timeout(fence, false, timeout); 653 if (r == 0) 654 r = -ETIMEDOUT; 655 else if (r > 0) 656 r = 0; 657 658 dma_fence_put(fence); 659 error: 660 return r; 661 } 662 663 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 664 struct amdgpu_bo *bo, 665 struct dma_fence **fence) 666 { 667 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 668 const unsigned int ib_size_dw = 64; 669 struct amdgpu_device *adev = ring->adev; 670 struct dma_fence *f = NULL; 671 struct amdgpu_job *job; 672 struct amdgpu_ib *ib; 673 uint64_t addr; 674 int i, r; 675 676 r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4, 677 AMDGPU_IB_POOL_DIRECT, &job); 678 if (r) 679 goto err; 680 681 ib = &job->ibs[0]; 682 addr = amdgpu_bo_gpu_offset(bo); 683 ib->length_dw = 0; 684 685 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 686 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 687 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 688 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 689 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 690 691 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 692 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 693 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 694 695 for (i = ib->length_dw; i < ib_size_dw; ++i) 696 ib->ptr[i] = 0x0; 697 698 r = amdgpu_job_submit_direct(job, ring, &f); 699 if (r) 700 goto err_free; 701 702 amdgpu_bo_fence(bo, f, false); 703 amdgpu_bo_unreserve(bo); 704 amdgpu_bo_unref(&bo); 705 706 if (fence) 707 *fence = dma_fence_get(f); 708 dma_fence_put(f); 709 710 return 0; 711 712 err_free: 713 amdgpu_job_free(job); 714 715 err: 716 amdgpu_bo_unreserve(bo); 717 amdgpu_bo_unref(&bo); 718 return r; 719 } 720 721 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 722 { 723 struct dma_fence *fence = NULL; 724 struct amdgpu_bo *bo; 725 long r; 726 727 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo); 728 if (r) 729 goto error; 730 731 r = amdgpu_vcn_dec_sw_send_msg(ring, bo, NULL); 732 if (r) 733 goto error; 734 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo); 735 if (r) 736 goto error; 737 738 r = amdgpu_vcn_dec_sw_send_msg(ring, bo, &fence); 739 if (r) 740 goto error; 741 742 r = dma_fence_wait_timeout(fence, false, timeout); 743 if (r == 0) 744 r = -ETIMEDOUT; 745 else if (r > 0) 746 r = 0; 747 748 dma_fence_put(fence); 749 error: 750 return r; 751 } 752 753 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 754 { 755 struct amdgpu_device *adev = ring->adev; 756 uint32_t rptr; 757 unsigned i; 758 int r; 759 760 if (amdgpu_sriov_vf(adev)) 761 return 0; 762 763 r = amdgpu_ring_alloc(ring, 16); 764 if (r) 765 return r; 766 767 rptr = amdgpu_ring_get_rptr(ring); 768 769 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 770 amdgpu_ring_commit(ring); 771 772 for (i = 0; i < adev->usec_timeout; i++) { 773 if (amdgpu_ring_get_rptr(ring) != rptr) 774 break; 775 udelay(1); 776 } 777 778 if (i >= adev->usec_timeout) 779 r = -ETIMEDOUT; 780 781 return r; 782 } 783 784 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 785 struct amdgpu_bo *bo, 786 struct dma_fence **fence) 787 { 788 const unsigned ib_size_dw = 16; 789 struct amdgpu_job *job; 790 struct amdgpu_ib *ib; 791 struct dma_fence *f = NULL; 792 uint64_t addr; 793 int i, r; 794 795 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 796 AMDGPU_IB_POOL_DIRECT, &job); 797 if (r) 798 return r; 799 800 ib = &job->ibs[0]; 801 addr = amdgpu_bo_gpu_offset(bo); 802 803 ib->length_dw = 0; 804 ib->ptr[ib->length_dw++] = 0x00000018; 805 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 806 ib->ptr[ib->length_dw++] = handle; 807 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 808 ib->ptr[ib->length_dw++] = addr; 809 ib->ptr[ib->length_dw++] = 0x0000000b; 810 811 ib->ptr[ib->length_dw++] = 0x00000014; 812 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 813 ib->ptr[ib->length_dw++] = 0x0000001c; 814 ib->ptr[ib->length_dw++] = 0x00000000; 815 ib->ptr[ib->length_dw++] = 0x00000000; 816 817 ib->ptr[ib->length_dw++] = 0x00000008; 818 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 819 820 for (i = ib->length_dw; i < ib_size_dw; ++i) 821 ib->ptr[i] = 0x0; 822 823 r = amdgpu_job_submit_direct(job, ring, &f); 824 if (r) 825 goto err; 826 827 if (fence) 828 *fence = dma_fence_get(f); 829 dma_fence_put(f); 830 831 return 0; 832 833 err: 834 amdgpu_job_free(job); 835 return r; 836 } 837 838 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 839 struct amdgpu_bo *bo, 840 struct dma_fence **fence) 841 { 842 const unsigned ib_size_dw = 16; 843 struct amdgpu_job *job; 844 struct amdgpu_ib *ib; 845 struct dma_fence *f = NULL; 846 uint64_t addr; 847 int i, r; 848 849 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 850 AMDGPU_IB_POOL_DIRECT, &job); 851 if (r) 852 return r; 853 854 ib = &job->ibs[0]; 855 addr = amdgpu_bo_gpu_offset(bo); 856 857 ib->length_dw = 0; 858 ib->ptr[ib->length_dw++] = 0x00000018; 859 ib->ptr[ib->length_dw++] = 0x00000001; 860 ib->ptr[ib->length_dw++] = handle; 861 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 862 ib->ptr[ib->length_dw++] = addr; 863 ib->ptr[ib->length_dw++] = 0x0000000b; 864 865 ib->ptr[ib->length_dw++] = 0x00000014; 866 ib->ptr[ib->length_dw++] = 0x00000002; 867 ib->ptr[ib->length_dw++] = 0x0000001c; 868 ib->ptr[ib->length_dw++] = 0x00000000; 869 ib->ptr[ib->length_dw++] = 0x00000000; 870 871 ib->ptr[ib->length_dw++] = 0x00000008; 872 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 873 874 for (i = ib->length_dw; i < ib_size_dw; ++i) 875 ib->ptr[i] = 0x0; 876 877 r = amdgpu_job_submit_direct(job, ring, &f); 878 if (r) 879 goto err; 880 881 if (fence) 882 *fence = dma_fence_get(f); 883 dma_fence_put(f); 884 885 return 0; 886 887 err: 888 amdgpu_job_free(job); 889 return r; 890 } 891 892 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 893 { 894 struct dma_fence *fence = NULL; 895 struct amdgpu_bo *bo = NULL; 896 long r; 897 898 r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE, 899 AMDGPU_GEM_DOMAIN_VRAM, 900 &bo, NULL, NULL); 901 if (r) 902 return r; 903 904 r = amdgpu_vcn_enc_get_create_msg(ring, 1, bo, NULL); 905 if (r) 906 goto error; 907 908 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, bo, &fence); 909 if (r) 910 goto error; 911 912 r = dma_fence_wait_timeout(fence, false, timeout); 913 if (r == 0) 914 r = -ETIMEDOUT; 915 else if (r > 0) 916 r = 0; 917 918 error: 919 dma_fence_put(fence); 920 amdgpu_bo_unreserve(bo); 921 amdgpu_bo_free_kernel(&bo, NULL, NULL); 922 923 return r; 924 } 925