1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 31 #include <drm/drm.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_pm.h" 35 #include "amdgpu_vcn.h" 36 #include "soc15d.h" 37 #include "soc15_common.h" 38 39 #include "vcn/vcn_1_0_offset.h" 40 #include "vcn/vcn_1_0_sh_mask.h" 41 42 /* 1 second timeout */ 43 #define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000) 44 45 /* Firmware Names */ 46 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 47 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 48 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 49 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 50 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 51 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 52 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 53 54 MODULE_FIRMWARE(FIRMWARE_RAVEN); 55 MODULE_FIRMWARE(FIRMWARE_PICASSO); 56 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 57 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 58 MODULE_FIRMWARE(FIRMWARE_NAVI10); 59 MODULE_FIRMWARE(FIRMWARE_NAVI14); 60 MODULE_FIRMWARE(FIRMWARE_NAVI12); 61 62 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 63 64 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 65 { 66 unsigned long bo_size; 67 const char *fw_name; 68 const struct common_firmware_header *hdr; 69 unsigned char fw_check; 70 int i, r; 71 72 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 73 74 switch (adev->asic_type) { 75 case CHIP_RAVEN: 76 if (adev->rev_id >= 8) 77 fw_name = FIRMWARE_RAVEN2; 78 else if (adev->pdev->device == 0x15d8) 79 fw_name = FIRMWARE_PICASSO; 80 else 81 fw_name = FIRMWARE_RAVEN; 82 break; 83 case CHIP_ARCTURUS: 84 fw_name = FIRMWARE_ARCTURUS; 85 break; 86 case CHIP_NAVI10: 87 fw_name = FIRMWARE_NAVI10; 88 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 89 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 90 adev->vcn.indirect_sram = true; 91 break; 92 case CHIP_NAVI14: 93 fw_name = FIRMWARE_NAVI14; 94 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 95 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 96 adev->vcn.indirect_sram = true; 97 break; 98 case CHIP_NAVI12: 99 fw_name = FIRMWARE_NAVI12; 100 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 101 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 102 adev->vcn.indirect_sram = true; 103 break; 104 default: 105 return -EINVAL; 106 } 107 108 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); 109 if (r) { 110 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", 111 fw_name); 112 return r; 113 } 114 115 r = amdgpu_ucode_validate(adev->vcn.fw); 116 if (r) { 117 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", 118 fw_name); 119 release_firmware(adev->vcn.fw); 120 adev->vcn.fw = NULL; 121 return r; 122 } 123 124 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 125 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 126 127 /* Bit 20-23, it is encode major and non-zero for new naming convention. 128 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 129 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 130 * is zero in old naming convention, this field is always zero so far. 131 * These four bits are used to tell which naming convention is present. 132 */ 133 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 134 if (fw_check) { 135 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 136 137 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 138 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 139 enc_major = fw_check; 140 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 141 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 142 DRM_INFO("Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n", 143 enc_major, enc_minor, dec_ver, vep, fw_rev); 144 } else { 145 unsigned int version_major, version_minor, family_id; 146 147 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 148 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 149 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 150 DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n", 151 version_major, version_minor, family_id); 152 } 153 154 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 155 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 156 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 157 158 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 159 if (adev->vcn.harvest_config & (1 << i)) 160 continue; 161 162 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 163 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo, 164 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr); 165 if (r) { 166 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 167 return r; 168 } 169 } 170 171 if (adev->vcn.indirect_sram) { 172 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 173 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.dpg_sram_bo, 174 &adev->vcn.dpg_sram_gpu_addr, &adev->vcn.dpg_sram_cpu_addr); 175 if (r) { 176 dev_err(adev->dev, "(%d) failed to allocate DPG bo\n", r); 177 return r; 178 } 179 } 180 181 return 0; 182 } 183 184 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 185 { 186 int i, j; 187 188 if (adev->vcn.indirect_sram) { 189 amdgpu_bo_free_kernel(&adev->vcn.dpg_sram_bo, 190 &adev->vcn.dpg_sram_gpu_addr, 191 (void **)&adev->vcn.dpg_sram_cpu_addr); 192 } 193 194 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 195 if (adev->vcn.harvest_config & (1 << j)) 196 continue; 197 kvfree(adev->vcn.inst[j].saved_bo); 198 199 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 200 &adev->vcn.inst[j].gpu_addr, 201 (void **)&adev->vcn.inst[j].cpu_addr); 202 203 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 204 205 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 206 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 207 208 amdgpu_ring_fini(&adev->vcn.inst[j].ring_jpeg); 209 } 210 211 release_firmware(adev->vcn.fw); 212 213 return 0; 214 } 215 216 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 217 { 218 unsigned size; 219 void *ptr; 220 int i; 221 222 cancel_delayed_work_sync(&adev->vcn.idle_work); 223 224 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 225 if (adev->vcn.harvest_config & (1 << i)) 226 continue; 227 if (adev->vcn.inst[i].vcpu_bo == NULL) 228 return 0; 229 230 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 231 ptr = adev->vcn.inst[i].cpu_addr; 232 233 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 234 if (!adev->vcn.inst[i].saved_bo) 235 return -ENOMEM; 236 237 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 238 } 239 return 0; 240 } 241 242 int amdgpu_vcn_resume(struct amdgpu_device *adev) 243 { 244 unsigned size; 245 void *ptr; 246 int i; 247 248 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 249 if (adev->vcn.harvest_config & (1 << i)) 250 continue; 251 if (adev->vcn.inst[i].vcpu_bo == NULL) 252 return -EINVAL; 253 254 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 255 ptr = adev->vcn.inst[i].cpu_addr; 256 257 if (adev->vcn.inst[i].saved_bo != NULL) { 258 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 259 kvfree(adev->vcn.inst[i].saved_bo); 260 adev->vcn.inst[i].saved_bo = NULL; 261 } else { 262 const struct common_firmware_header *hdr; 263 unsigned offset; 264 265 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 266 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 267 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 268 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 269 le32_to_cpu(hdr->ucode_size_bytes)); 270 size -= le32_to_cpu(hdr->ucode_size_bytes); 271 ptr += le32_to_cpu(hdr->ucode_size_bytes); 272 } 273 memset_io(ptr, 0, size); 274 } 275 } 276 return 0; 277 } 278 279 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 280 { 281 struct amdgpu_device *adev = 282 container_of(work, struct amdgpu_device, vcn.idle_work.work); 283 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 284 unsigned int i, j; 285 286 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 287 if (adev->vcn.harvest_config & (1 << j)) 288 continue; 289 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 290 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 291 } 292 293 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 294 struct dpg_pause_state new_state; 295 296 if (fence[j]) 297 new_state.fw_based = VCN_DPG_STATE__PAUSE; 298 else 299 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 300 301 if (amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg)) 302 new_state.jpeg = VCN_DPG_STATE__PAUSE; 303 else 304 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 305 306 adev->vcn.pause_dpg_mode(adev, &new_state); 307 } 308 309 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg); 310 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 311 fences += fence[j]; 312 } 313 314 if (fences == 0) { 315 amdgpu_gfx_off_ctrl(adev, true); 316 if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled) 317 amdgpu_dpm_enable_uvd(adev, false); 318 else 319 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 320 AMD_PG_STATE_GATE); 321 } else { 322 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 323 } 324 } 325 326 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 327 { 328 struct amdgpu_device *adev = ring->adev; 329 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); 330 331 if (set_clocks) { 332 amdgpu_gfx_off_ctrl(adev, false); 333 if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled) 334 amdgpu_dpm_enable_uvd(adev, true); 335 else 336 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 337 AMD_PG_STATE_UNGATE); 338 } 339 340 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 341 struct dpg_pause_state new_state; 342 unsigned int fences = 0; 343 unsigned int i; 344 345 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 346 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 347 } 348 if (fences) 349 new_state.fw_based = VCN_DPG_STATE__PAUSE; 350 else 351 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 352 353 if (amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_jpeg)) 354 new_state.jpeg = VCN_DPG_STATE__PAUSE; 355 else 356 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 357 358 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 359 new_state.fw_based = VCN_DPG_STATE__PAUSE; 360 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 361 new_state.jpeg = VCN_DPG_STATE__PAUSE; 362 363 adev->vcn.pause_dpg_mode(adev, &new_state); 364 } 365 } 366 367 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 368 { 369 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 370 } 371 372 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 373 { 374 struct amdgpu_device *adev = ring->adev; 375 uint32_t tmp = 0; 376 unsigned i; 377 int r; 378 379 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 380 r = amdgpu_ring_alloc(ring, 3); 381 if (r) 382 return r; 383 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 384 amdgpu_ring_write(ring, 0xDEADBEEF); 385 amdgpu_ring_commit(ring); 386 for (i = 0; i < adev->usec_timeout; i++) { 387 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 388 if (tmp == 0xDEADBEEF) 389 break; 390 udelay(1); 391 } 392 393 if (i >= adev->usec_timeout) 394 r = -ETIMEDOUT; 395 396 return r; 397 } 398 399 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 400 struct amdgpu_bo *bo, 401 struct dma_fence **fence) 402 { 403 struct amdgpu_device *adev = ring->adev; 404 struct dma_fence *f = NULL; 405 struct amdgpu_job *job; 406 struct amdgpu_ib *ib; 407 uint64_t addr; 408 int i, r; 409 410 r = amdgpu_job_alloc_with_ib(adev, 64, &job); 411 if (r) 412 goto err; 413 414 ib = &job->ibs[0]; 415 addr = amdgpu_bo_gpu_offset(bo); 416 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 417 ib->ptr[1] = addr; 418 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 419 ib->ptr[3] = addr >> 32; 420 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 421 ib->ptr[5] = 0; 422 for (i = 6; i < 16; i += 2) { 423 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 424 ib->ptr[i+1] = 0; 425 } 426 ib->length_dw = 16; 427 428 r = amdgpu_job_submit_direct(job, ring, &f); 429 if (r) 430 goto err_free; 431 432 amdgpu_bo_fence(bo, f, false); 433 amdgpu_bo_unreserve(bo); 434 amdgpu_bo_unref(&bo); 435 436 if (fence) 437 *fence = dma_fence_get(f); 438 dma_fence_put(f); 439 440 return 0; 441 442 err_free: 443 amdgpu_job_free(job); 444 445 err: 446 amdgpu_bo_unreserve(bo); 447 amdgpu_bo_unref(&bo); 448 return r; 449 } 450 451 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 452 struct dma_fence **fence) 453 { 454 struct amdgpu_device *adev = ring->adev; 455 struct amdgpu_bo *bo = NULL; 456 uint32_t *msg; 457 int r, i; 458 459 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 460 AMDGPU_GEM_DOMAIN_VRAM, 461 &bo, NULL, (void **)&msg); 462 if (r) 463 return r; 464 465 msg[0] = cpu_to_le32(0x00000028); 466 msg[1] = cpu_to_le32(0x00000038); 467 msg[2] = cpu_to_le32(0x00000001); 468 msg[3] = cpu_to_le32(0x00000000); 469 msg[4] = cpu_to_le32(handle); 470 msg[5] = cpu_to_le32(0x00000000); 471 msg[6] = cpu_to_le32(0x00000001); 472 msg[7] = cpu_to_le32(0x00000028); 473 msg[8] = cpu_to_le32(0x00000010); 474 msg[9] = cpu_to_le32(0x00000000); 475 msg[10] = cpu_to_le32(0x00000007); 476 msg[11] = cpu_to_le32(0x00000000); 477 msg[12] = cpu_to_le32(0x00000780); 478 msg[13] = cpu_to_le32(0x00000440); 479 for (i = 14; i < 1024; ++i) 480 msg[i] = cpu_to_le32(0x0); 481 482 return amdgpu_vcn_dec_send_msg(ring, bo, fence); 483 } 484 485 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 486 struct dma_fence **fence) 487 { 488 struct amdgpu_device *adev = ring->adev; 489 struct amdgpu_bo *bo = NULL; 490 uint32_t *msg; 491 int r, i; 492 493 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 494 AMDGPU_GEM_DOMAIN_VRAM, 495 &bo, NULL, (void **)&msg); 496 if (r) 497 return r; 498 499 msg[0] = cpu_to_le32(0x00000028); 500 msg[1] = cpu_to_le32(0x00000018); 501 msg[2] = cpu_to_le32(0x00000000); 502 msg[3] = cpu_to_le32(0x00000002); 503 msg[4] = cpu_to_le32(handle); 504 msg[5] = cpu_to_le32(0x00000000); 505 for (i = 6; i < 1024; ++i) 506 msg[i] = cpu_to_le32(0x0); 507 508 return amdgpu_vcn_dec_send_msg(ring, bo, fence); 509 } 510 511 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 512 { 513 struct dma_fence *fence; 514 long r; 515 516 r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL); 517 if (r) 518 goto error; 519 520 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence); 521 if (r) 522 goto error; 523 524 r = dma_fence_wait_timeout(fence, false, timeout); 525 if (r == 0) 526 r = -ETIMEDOUT; 527 else if (r > 0) 528 r = 0; 529 530 dma_fence_put(fence); 531 error: 532 return r; 533 } 534 535 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 536 { 537 struct amdgpu_device *adev = ring->adev; 538 uint32_t rptr; 539 unsigned i; 540 int r; 541 542 r = amdgpu_ring_alloc(ring, 16); 543 if (r) 544 return r; 545 546 rptr = amdgpu_ring_get_rptr(ring); 547 548 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 549 amdgpu_ring_commit(ring); 550 551 for (i = 0; i < adev->usec_timeout; i++) { 552 if (amdgpu_ring_get_rptr(ring) != rptr) 553 break; 554 udelay(1); 555 } 556 557 if (i >= adev->usec_timeout) 558 r = -ETIMEDOUT; 559 560 return r; 561 } 562 563 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 564 struct dma_fence **fence) 565 { 566 const unsigned ib_size_dw = 16; 567 struct amdgpu_job *job; 568 struct amdgpu_ib *ib; 569 struct dma_fence *f = NULL; 570 uint64_t dummy; 571 int i, r; 572 573 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 574 if (r) 575 return r; 576 577 ib = &job->ibs[0]; 578 dummy = ib->gpu_addr + 1024; 579 580 ib->length_dw = 0; 581 ib->ptr[ib->length_dw++] = 0x00000018; 582 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 583 ib->ptr[ib->length_dw++] = handle; 584 ib->ptr[ib->length_dw++] = upper_32_bits(dummy); 585 ib->ptr[ib->length_dw++] = dummy; 586 ib->ptr[ib->length_dw++] = 0x0000000b; 587 588 ib->ptr[ib->length_dw++] = 0x00000014; 589 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 590 ib->ptr[ib->length_dw++] = 0x0000001c; 591 ib->ptr[ib->length_dw++] = 0x00000000; 592 ib->ptr[ib->length_dw++] = 0x00000000; 593 594 ib->ptr[ib->length_dw++] = 0x00000008; 595 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 596 597 for (i = ib->length_dw; i < ib_size_dw; ++i) 598 ib->ptr[i] = 0x0; 599 600 r = amdgpu_job_submit_direct(job, ring, &f); 601 if (r) 602 goto err; 603 604 if (fence) 605 *fence = dma_fence_get(f); 606 dma_fence_put(f); 607 608 return 0; 609 610 err: 611 amdgpu_job_free(job); 612 return r; 613 } 614 615 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 616 struct dma_fence **fence) 617 { 618 const unsigned ib_size_dw = 16; 619 struct amdgpu_job *job; 620 struct amdgpu_ib *ib; 621 struct dma_fence *f = NULL; 622 uint64_t dummy; 623 int i, r; 624 625 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 626 if (r) 627 return r; 628 629 ib = &job->ibs[0]; 630 dummy = ib->gpu_addr + 1024; 631 632 ib->length_dw = 0; 633 ib->ptr[ib->length_dw++] = 0x00000018; 634 ib->ptr[ib->length_dw++] = 0x00000001; 635 ib->ptr[ib->length_dw++] = handle; 636 ib->ptr[ib->length_dw++] = upper_32_bits(dummy); 637 ib->ptr[ib->length_dw++] = dummy; 638 ib->ptr[ib->length_dw++] = 0x0000000b; 639 640 ib->ptr[ib->length_dw++] = 0x00000014; 641 ib->ptr[ib->length_dw++] = 0x00000002; 642 ib->ptr[ib->length_dw++] = 0x0000001c; 643 ib->ptr[ib->length_dw++] = 0x00000000; 644 ib->ptr[ib->length_dw++] = 0x00000000; 645 646 ib->ptr[ib->length_dw++] = 0x00000008; 647 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 648 649 for (i = ib->length_dw; i < ib_size_dw; ++i) 650 ib->ptr[i] = 0x0; 651 652 r = amdgpu_job_submit_direct(job, ring, &f); 653 if (r) 654 goto err; 655 656 if (fence) 657 *fence = dma_fence_get(f); 658 dma_fence_put(f); 659 660 return 0; 661 662 err: 663 amdgpu_job_free(job); 664 return r; 665 } 666 667 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 668 { 669 struct dma_fence *fence = NULL; 670 long r; 671 672 r = amdgpu_vcn_enc_get_create_msg(ring, 1, NULL); 673 if (r) 674 goto error; 675 676 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &fence); 677 if (r) 678 goto error; 679 680 r = dma_fence_wait_timeout(fence, false, timeout); 681 if (r == 0) 682 r = -ETIMEDOUT; 683 else if (r > 0) 684 r = 0; 685 686 error: 687 dma_fence_put(fence); 688 return r; 689 } 690 691 int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring) 692 { 693 struct amdgpu_device *adev = ring->adev; 694 uint32_t tmp = 0; 695 unsigned i; 696 int r; 697 698 WREG32(adev->vcn.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD); 699 r = amdgpu_ring_alloc(ring, 3); 700 if (r) 701 return r; 702 703 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.jpeg_pitch, 0)); 704 amdgpu_ring_write(ring, 0xDEADBEEF); 705 amdgpu_ring_commit(ring); 706 707 for (i = 0; i < adev->usec_timeout; i++) { 708 tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch); 709 if (tmp == 0xDEADBEEF) 710 break; 711 udelay(1); 712 } 713 714 if (i >= adev->usec_timeout) 715 r = -ETIMEDOUT; 716 717 return r; 718 } 719 720 static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle, 721 struct dma_fence **fence) 722 { 723 struct amdgpu_device *adev = ring->adev; 724 struct amdgpu_job *job; 725 struct amdgpu_ib *ib; 726 struct dma_fence *f = NULL; 727 const unsigned ib_size_dw = 16; 728 int i, r; 729 730 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 731 if (r) 732 return r; 733 734 ib = &job->ibs[0]; 735 736 ib->ptr[0] = PACKETJ(adev->vcn.internal.jpeg_pitch, 0, 0, PACKETJ_TYPE0); 737 ib->ptr[1] = 0xDEADBEEF; 738 for (i = 2; i < 16; i += 2) { 739 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6); 740 ib->ptr[i+1] = 0; 741 } 742 ib->length_dw = 16; 743 744 r = amdgpu_job_submit_direct(job, ring, &f); 745 if (r) 746 goto err; 747 748 if (fence) 749 *fence = dma_fence_get(f); 750 dma_fence_put(f); 751 752 return 0; 753 754 err: 755 amdgpu_job_free(job); 756 return r; 757 } 758 759 int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout) 760 { 761 struct amdgpu_device *adev = ring->adev; 762 uint32_t tmp = 0; 763 unsigned i; 764 struct dma_fence *fence = NULL; 765 long r = 0; 766 767 r = amdgpu_vcn_jpeg_set_reg(ring, 1, &fence); 768 if (r) 769 goto error; 770 771 r = dma_fence_wait_timeout(fence, false, timeout); 772 if (r == 0) { 773 r = -ETIMEDOUT; 774 goto error; 775 } else if (r < 0) { 776 goto error; 777 } else { 778 r = 0; 779 } 780 781 for (i = 0; i < adev->usec_timeout; i++) { 782 tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch); 783 if (tmp == 0xDEADBEEF) 784 break; 785 udelay(1); 786 } 787 788 if (i >= adev->usec_timeout) 789 r = -ETIMEDOUT; 790 791 dma_fence_put(fence); 792 error: 793 return r; 794 } 795