1 /* 2 * Copyright 2016-2024 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/dmi.h> 30 #include <linux/pci.h> 31 #include <linux/debugfs.h> 32 #include <drm/drm_drv.h> 33 34 #include "amdgpu.h" 35 #include "amdgpu_pm.h" 36 #include "amdgpu_vcn.h" 37 #include "soc15d.h" 38 39 /* Firmware Names */ 40 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 41 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 42 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 43 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 44 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 45 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 46 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 47 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 48 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 49 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 50 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 51 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 52 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 53 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 54 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 55 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 56 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin" 57 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin" 58 #define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin" 59 #define FIRMWARE_VCN4_0_3 "amdgpu/vcn_4_0_3.bin" 60 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin" 61 #define FIRMWARE_VCN4_0_5 "amdgpu/vcn_4_0_5.bin" 62 #define FIRMWARE_VCN4_0_6 "amdgpu/vcn_4_0_6.bin" 63 #define FIRMWARE_VCN4_0_6_1 "amdgpu/vcn_4_0_6_1.bin" 64 #define FIRMWARE_VCN5_0_0 "amdgpu/vcn_5_0_0.bin" 65 #define FIRMWARE_VCN5_0_1 "amdgpu/vcn_5_0_1.bin" 66 67 MODULE_FIRMWARE(FIRMWARE_RAVEN); 68 MODULE_FIRMWARE(FIRMWARE_PICASSO); 69 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 70 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 71 MODULE_FIRMWARE(FIRMWARE_RENOIR); 72 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 73 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 74 MODULE_FIRMWARE(FIRMWARE_NAVI10); 75 MODULE_FIRMWARE(FIRMWARE_NAVI14); 76 MODULE_FIRMWARE(FIRMWARE_NAVI12); 77 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 78 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 79 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 80 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 81 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 82 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 83 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2); 84 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0); 85 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2); 86 MODULE_FIRMWARE(FIRMWARE_VCN4_0_3); 87 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4); 88 MODULE_FIRMWARE(FIRMWARE_VCN4_0_5); 89 MODULE_FIRMWARE(FIRMWARE_VCN4_0_6); 90 MODULE_FIRMWARE(FIRMWARE_VCN4_0_6_1); 91 MODULE_FIRMWARE(FIRMWARE_VCN5_0_0); 92 MODULE_FIRMWARE(FIRMWARE_VCN5_0_1); 93 94 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 95 static void amdgpu_vcn_reg_dump_fini(struct amdgpu_device *adev); 96 97 int amdgpu_vcn_early_init(struct amdgpu_device *adev, int i) 98 { 99 char ucode_prefix[25]; 100 int r; 101 102 adev->vcn.inst[i].adev = adev; 103 adev->vcn.inst[i].inst = i; 104 amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix)); 105 106 if (i != 0 && adev->vcn.per_inst_fw) { 107 r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw, 108 AMDGPU_UCODE_REQUIRED, 109 "amdgpu/%s_%d.bin", ucode_prefix, i); 110 if (r) 111 amdgpu_ucode_release(&adev->vcn.inst[i].fw); 112 } else { 113 if (!adev->vcn.inst[0].fw) { 114 r = amdgpu_ucode_request(adev, &adev->vcn.inst[0].fw, 115 AMDGPU_UCODE_REQUIRED, 116 "amdgpu/%s.bin", ucode_prefix); 117 if (r) 118 amdgpu_ucode_release(&adev->vcn.inst[0].fw); 119 } else { 120 r = 0; 121 } 122 adev->vcn.inst[i].fw = adev->vcn.inst[0].fw; 123 } 124 125 return r; 126 } 127 128 int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int i) 129 { 130 unsigned long bo_size; 131 const struct common_firmware_header *hdr; 132 unsigned char fw_check; 133 unsigned int fw_shared_size, log_offset; 134 int r; 135 136 mutex_init(&adev->vcn.inst[i].vcn1_jpeg1_workaround); 137 mutex_init(&adev->vcn.inst[i].vcn_pg_lock); 138 mutex_init(&adev->vcn.inst[i].engine_reset_mutex); 139 atomic_set(&adev->vcn.inst[i].total_submission_cnt, 0); 140 INIT_DELAYED_WORK(&adev->vcn.inst[i].idle_work, amdgpu_vcn_idle_work_handler); 141 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 142 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 143 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 144 adev->vcn.inst[i].indirect_sram = true; 145 146 /* 147 * Some Steam Deck's BIOS versions are incompatible with the 148 * indirect SRAM mode, leading to amdgpu being unable to get 149 * properly probed (and even potentially crashing the kernel). 150 * Hence, check for these versions here - notice this is 151 * restricted to Vangogh (Deck's APU). 152 */ 153 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 0, 2)) { 154 const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION); 155 156 if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) || 157 !strncmp("F7A0114", bios_ver, 7))) { 158 adev->vcn.inst[i].indirect_sram = false; 159 dev_info(adev->dev, 160 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver); 161 } 162 } 163 164 /* from vcn4 and above, only unified queue is used */ 165 adev->vcn.inst[i].using_unified_queue = 166 amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0); 167 168 hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data; 169 adev->vcn.inst[i].fw_version = le32_to_cpu(hdr->ucode_version); 170 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 171 172 /* Bit 20-23, it is encode major and non-zero for new naming convention. 173 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 174 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 175 * is zero in old naming convention, this field is always zero so far. 176 * These four bits are used to tell which naming convention is present. 177 */ 178 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 179 if (fw_check) { 180 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 181 182 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 183 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 184 enc_major = fw_check; 185 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 186 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 187 dev_info(adev->dev, 188 "Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 189 enc_major, enc_minor, dec_ver, vep, fw_rev); 190 } else { 191 unsigned int version_major, version_minor, family_id; 192 193 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 194 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 195 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 196 dev_info(adev->dev, "Found VCN firmware Version: %u.%u Family ID: %u\n", 197 version_major, version_minor, family_id); 198 } 199 200 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 201 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 202 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 203 204 if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(5, 0, 0)) { 205 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)); 206 log_offset = offsetof(struct amdgpu_vcn5_fw_shared, fw_log); 207 } else if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) { 208 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); 209 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log); 210 } else { 211 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 212 log_offset = offsetof(struct amdgpu_fw_shared, fw_log); 213 } 214 215 bo_size += fw_shared_size; 216 217 if (amdgpu_vcnfw_log) 218 bo_size += AMDGPU_VCNFW_LOG_SIZE; 219 220 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 221 AMDGPU_GEM_DOMAIN_VRAM | 222 AMDGPU_GEM_DOMAIN_GTT, 223 &adev->vcn.inst[i].vcpu_bo, 224 &adev->vcn.inst[i].gpu_addr, 225 &adev->vcn.inst[i].cpu_addr); 226 if (r) { 227 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 228 return r; 229 } 230 231 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr + 232 bo_size - fw_shared_size; 233 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr + 234 bo_size - fw_shared_size; 235 236 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size; 237 238 if (amdgpu_vcnfw_log) { 239 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 240 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 241 adev->vcn.inst[i].fw_shared.log_offset = log_offset; 242 } 243 244 if (adev->vcn.inst[i].indirect_sram) { 245 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 246 AMDGPU_GEM_DOMAIN_VRAM | 247 AMDGPU_GEM_DOMAIN_GTT, 248 &adev->vcn.inst[i].dpg_sram_bo, 249 &adev->vcn.inst[i].dpg_sram_gpu_addr, 250 &adev->vcn.inst[i].dpg_sram_cpu_addr); 251 if (r) { 252 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 253 return r; 254 } 255 } 256 257 return 0; 258 } 259 260 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int i) 261 { 262 int j; 263 264 if (adev->vcn.harvest_config & (1 << i)) 265 return 0; 266 267 amdgpu_bo_free_kernel( 268 &adev->vcn.inst[i].dpg_sram_bo, 269 &adev->vcn.inst[i].dpg_sram_gpu_addr, 270 (void **)&adev->vcn.inst[i].dpg_sram_cpu_addr); 271 272 kvfree(adev->vcn.inst[i].saved_bo); 273 274 amdgpu_bo_free_kernel(&adev->vcn.inst[i].vcpu_bo, 275 &adev->vcn.inst[i].gpu_addr, 276 (void **)&adev->vcn.inst[i].cpu_addr); 277 278 amdgpu_ring_fini(&adev->vcn.inst[i].ring_dec); 279 280 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) 281 amdgpu_ring_fini(&adev->vcn.inst[i].ring_enc[j]); 282 283 if (adev->vcn.per_inst_fw) { 284 amdgpu_ucode_release(&adev->vcn.inst[i].fw); 285 } else { 286 amdgpu_ucode_release(&adev->vcn.inst[0].fw); 287 adev->vcn.inst[i].fw = NULL; 288 } 289 290 if (adev->vcn.reg_list) 291 amdgpu_vcn_reg_dump_fini(adev); 292 293 mutex_destroy(&adev->vcn.inst[i].vcn_pg_lock); 294 mutex_destroy(&adev->vcn.inst[i].vcn1_jpeg1_workaround); 295 296 return 0; 297 } 298 299 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 300 { 301 bool ret = false; 302 int vcn_config = adev->vcn.inst[vcn_instance].vcn_config; 303 304 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) 305 ret = true; 306 else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) 307 ret = true; 308 else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) 309 ret = true; 310 311 return ret; 312 } 313 314 static int amdgpu_vcn_save_vcpu_bo_inst(struct amdgpu_device *adev, int i) 315 { 316 unsigned int size; 317 void *ptr; 318 int idx; 319 320 if (adev->vcn.harvest_config & (1 << i)) 321 return 0; 322 if (adev->vcn.inst[i].vcpu_bo == NULL) 323 return 0; 324 325 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 326 ptr = adev->vcn.inst[i].cpu_addr; 327 328 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 329 if (!adev->vcn.inst[i].saved_bo) 330 return -ENOMEM; 331 332 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 333 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 334 drm_dev_exit(idx); 335 } 336 337 return 0; 338 } 339 340 int amdgpu_vcn_save_vcpu_bo(struct amdgpu_device *adev) 341 { 342 int ret, i; 343 344 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 345 ret = amdgpu_vcn_save_vcpu_bo_inst(adev, i); 346 if (ret) 347 return ret; 348 } 349 350 return 0; 351 } 352 353 int amdgpu_vcn_suspend(struct amdgpu_device *adev, int i) 354 { 355 bool in_ras_intr = amdgpu_ras_intr_triggered(); 356 357 if (adev->vcn.harvest_config & (1 << i)) 358 return 0; 359 360 cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work); 361 362 /* err_event_athub and dpc recovery will corrupt VCPU buffer, so we need to 363 * restore fw data and clear buffer in amdgpu_vcn_resume() */ 364 if (in_ras_intr || adev->pcie_reset_ctx.in_link_reset) 365 return 0; 366 367 return amdgpu_vcn_save_vcpu_bo_inst(adev, i); 368 } 369 370 int amdgpu_vcn_resume(struct amdgpu_device *adev, int i) 371 { 372 unsigned int size; 373 void *ptr; 374 int idx; 375 376 if (adev->vcn.harvest_config & (1 << i)) 377 return 0; 378 if (adev->vcn.inst[i].vcpu_bo == NULL) 379 return -EINVAL; 380 381 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 382 ptr = adev->vcn.inst[i].cpu_addr; 383 384 if (adev->vcn.inst[i].saved_bo != NULL) { 385 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 386 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 387 drm_dev_exit(idx); 388 } 389 kvfree(adev->vcn.inst[i].saved_bo); 390 adev->vcn.inst[i].saved_bo = NULL; 391 } else { 392 const struct common_firmware_header *hdr; 393 unsigned int offset; 394 395 hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data; 396 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 397 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 398 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 399 memcpy_toio(adev->vcn.inst[i].cpu_addr, 400 adev->vcn.inst[i].fw->data + offset, 401 le32_to_cpu(hdr->ucode_size_bytes)); 402 drm_dev_exit(idx); 403 } 404 size -= le32_to_cpu(hdr->ucode_size_bytes); 405 ptr += le32_to_cpu(hdr->ucode_size_bytes); 406 } 407 memset_io(ptr, 0, size); 408 } 409 410 return 0; 411 } 412 413 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 414 { 415 struct amdgpu_vcn_inst *vcn_inst = 416 container_of(work, struct amdgpu_vcn_inst, idle_work.work); 417 struct amdgpu_device *adev = vcn_inst->adev; 418 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 419 unsigned int i = vcn_inst->inst, j; 420 int r = 0; 421 422 if (adev->vcn.harvest_config & (1 << i)) 423 return; 424 425 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) 426 fence[i] += amdgpu_fence_count_emitted(&vcn_inst->ring_enc[j]); 427 428 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 429 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 430 !adev->vcn.inst[i].using_unified_queue) { 431 struct dpg_pause_state new_state; 432 433 if (fence[i] || 434 unlikely(atomic_read(&vcn_inst->dpg_enc_submission_cnt))) 435 new_state.fw_based = VCN_DPG_STATE__PAUSE; 436 else 437 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 438 439 adev->vcn.inst[i].pause_dpg_mode(vcn_inst, &new_state); 440 } 441 442 fence[i] += amdgpu_fence_count_emitted(&vcn_inst->ring_dec); 443 fences += fence[i]; 444 445 if (!fences && !atomic_read(&vcn_inst->total_submission_cnt)) { 446 mutex_lock(&vcn_inst->vcn_pg_lock); 447 vcn_inst->set_pg_state(vcn_inst, AMD_PG_STATE_GATE); 448 mutex_unlock(&vcn_inst->vcn_pg_lock); 449 mutex_lock(&adev->vcn.workload_profile_mutex); 450 if (adev->vcn.workload_profile_active) { 451 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 452 false); 453 if (r) 454 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 455 adev->vcn.workload_profile_active = false; 456 } 457 mutex_unlock(&adev->vcn.workload_profile_mutex); 458 } else { 459 schedule_delayed_work(&vcn_inst->idle_work, VCN_IDLE_TIMEOUT); 460 } 461 } 462 463 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 464 { 465 struct amdgpu_device *adev = ring->adev; 466 struct amdgpu_vcn_inst *vcn_inst = &adev->vcn.inst[ring->me]; 467 int r = 0; 468 469 atomic_inc(&vcn_inst->total_submission_cnt); 470 471 cancel_delayed_work_sync(&vcn_inst->idle_work); 472 473 /* We can safely return early here because we've cancelled the 474 * the delayed work so there is no one else to set it to false 475 * and we don't care if someone else sets it to true. 476 */ 477 if (adev->vcn.workload_profile_active) 478 goto pg_lock; 479 480 mutex_lock(&adev->vcn.workload_profile_mutex); 481 if (!adev->vcn.workload_profile_active) { 482 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 483 true); 484 if (r) 485 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 486 adev->vcn.workload_profile_active = true; 487 } 488 mutex_unlock(&adev->vcn.workload_profile_mutex); 489 490 pg_lock: 491 mutex_lock(&vcn_inst->vcn_pg_lock); 492 vcn_inst->set_pg_state(vcn_inst, AMD_PG_STATE_UNGATE); 493 494 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 495 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 496 !vcn_inst->using_unified_queue) { 497 struct dpg_pause_state new_state; 498 499 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 500 atomic_inc(&vcn_inst->dpg_enc_submission_cnt); 501 new_state.fw_based = VCN_DPG_STATE__PAUSE; 502 } else { 503 unsigned int fences = 0; 504 unsigned int i; 505 506 for (i = 0; i < vcn_inst->num_enc_rings; ++i) 507 fences += amdgpu_fence_count_emitted(&vcn_inst->ring_enc[i]); 508 509 if (fences || atomic_read(&vcn_inst->dpg_enc_submission_cnt)) 510 new_state.fw_based = VCN_DPG_STATE__PAUSE; 511 else 512 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 513 } 514 515 vcn_inst->pause_dpg_mode(vcn_inst, &new_state); 516 } 517 mutex_unlock(&vcn_inst->vcn_pg_lock); 518 } 519 520 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 521 { 522 struct amdgpu_device *adev = ring->adev; 523 524 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 525 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 526 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC && 527 !adev->vcn.inst[ring->me].using_unified_queue) 528 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 529 530 atomic_dec(&ring->adev->vcn.inst[ring->me].total_submission_cnt); 531 532 schedule_delayed_work(&ring->adev->vcn.inst[ring->me].idle_work, 533 VCN_IDLE_TIMEOUT); 534 } 535 536 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 537 { 538 struct amdgpu_device *adev = ring->adev; 539 uint32_t tmp = 0; 540 unsigned int i; 541 int r; 542 543 /* VCN in SRIOV does not support direct register read/write */ 544 if (amdgpu_sriov_vf(adev)) 545 return 0; 546 547 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 548 r = amdgpu_ring_alloc(ring, 3); 549 if (r) 550 return r; 551 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.scratch9, 0)); 552 amdgpu_ring_write(ring, 0xDEADBEEF); 553 amdgpu_ring_commit(ring); 554 for (i = 0; i < adev->usec_timeout; i++) { 555 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 556 if (tmp == 0xDEADBEEF) 557 break; 558 udelay(1); 559 } 560 561 if (i >= adev->usec_timeout) 562 r = -ETIMEDOUT; 563 564 return r; 565 } 566 567 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 568 { 569 struct amdgpu_device *adev = ring->adev; 570 uint32_t rptr; 571 unsigned int i; 572 int r; 573 574 if (amdgpu_sriov_vf(adev)) 575 return 0; 576 577 r = amdgpu_ring_alloc(ring, 16); 578 if (r) 579 return r; 580 581 rptr = amdgpu_ring_get_rptr(ring); 582 583 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 584 amdgpu_ring_commit(ring); 585 586 for (i = 0; i < adev->usec_timeout; i++) { 587 if (amdgpu_ring_get_rptr(ring) != rptr) 588 break; 589 udelay(1); 590 } 591 592 if (i >= adev->usec_timeout) 593 r = -ETIMEDOUT; 594 595 return r; 596 } 597 598 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 599 struct amdgpu_ib *ib_msg, 600 struct dma_fence **fence) 601 { 602 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 603 struct amdgpu_device *adev = ring->adev; 604 struct dma_fence *f = NULL; 605 struct amdgpu_job *job; 606 struct amdgpu_ib *ib; 607 int i, r; 608 609 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 610 64, AMDGPU_IB_POOL_DIRECT, 611 &job); 612 if (r) 613 goto err; 614 615 ib = &job->ibs[0]; 616 ib->ptr[0] = PACKET0(adev->vcn.inst[ring->me].internal.data0, 0); 617 ib->ptr[1] = addr; 618 ib->ptr[2] = PACKET0(adev->vcn.inst[ring->me].internal.data1, 0); 619 ib->ptr[3] = addr >> 32; 620 ib->ptr[4] = PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0); 621 ib->ptr[5] = 0; 622 for (i = 6; i < 16; i += 2) { 623 ib->ptr[i] = PACKET0(adev->vcn.inst[ring->me].internal.nop, 0); 624 ib->ptr[i+1] = 0; 625 } 626 ib->length_dw = 16; 627 628 r = amdgpu_job_submit_direct(job, ring, &f); 629 if (r) 630 goto err_free; 631 632 amdgpu_ib_free(ib_msg, f); 633 634 if (fence) 635 *fence = dma_fence_get(f); 636 dma_fence_put(f); 637 638 return 0; 639 640 err_free: 641 amdgpu_job_free(job); 642 err: 643 amdgpu_ib_free(ib_msg, f); 644 return r; 645 } 646 647 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 648 struct amdgpu_ib *ib) 649 { 650 struct amdgpu_device *adev = ring->adev; 651 uint32_t *msg; 652 int r, i; 653 654 memset(ib, 0, sizeof(*ib)); 655 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 656 AMDGPU_IB_POOL_DIRECT, 657 ib); 658 if (r) 659 return r; 660 661 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 662 msg[0] = cpu_to_le32(0x00000028); 663 msg[1] = cpu_to_le32(0x00000038); 664 msg[2] = cpu_to_le32(0x00000001); 665 msg[3] = cpu_to_le32(0x00000000); 666 msg[4] = cpu_to_le32(handle); 667 msg[5] = cpu_to_le32(0x00000000); 668 msg[6] = cpu_to_le32(0x00000001); 669 msg[7] = cpu_to_le32(0x00000028); 670 msg[8] = cpu_to_le32(0x00000010); 671 msg[9] = cpu_to_le32(0x00000000); 672 msg[10] = cpu_to_le32(0x00000007); 673 msg[11] = cpu_to_le32(0x00000000); 674 msg[12] = cpu_to_le32(0x00000780); 675 msg[13] = cpu_to_le32(0x00000440); 676 for (i = 14; i < 1024; ++i) 677 msg[i] = cpu_to_le32(0x0); 678 679 return 0; 680 } 681 682 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 683 struct amdgpu_ib *ib) 684 { 685 struct amdgpu_device *adev = ring->adev; 686 uint32_t *msg; 687 int r, i; 688 689 memset(ib, 0, sizeof(*ib)); 690 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 691 AMDGPU_IB_POOL_DIRECT, 692 ib); 693 if (r) 694 return r; 695 696 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 697 msg[0] = cpu_to_le32(0x00000028); 698 msg[1] = cpu_to_le32(0x00000018); 699 msg[2] = cpu_to_le32(0x00000000); 700 msg[3] = cpu_to_le32(0x00000002); 701 msg[4] = cpu_to_le32(handle); 702 msg[5] = cpu_to_le32(0x00000000); 703 for (i = 6; i < 1024; ++i) 704 msg[i] = cpu_to_le32(0x0); 705 706 return 0; 707 } 708 709 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 710 { 711 struct dma_fence *fence = NULL; 712 struct amdgpu_ib ib; 713 long r; 714 715 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 716 if (r) 717 goto error; 718 719 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 720 if (r) 721 goto error; 722 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 723 if (r) 724 goto error; 725 726 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 727 if (r) 728 goto error; 729 730 r = dma_fence_wait_timeout(fence, false, timeout); 731 if (r == 0) 732 r = -ETIMEDOUT; 733 else if (r > 0) 734 r = 0; 735 736 dma_fence_put(fence); 737 error: 738 return r; 739 } 740 741 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, 742 uint32_t ib_pack_in_dw, bool enc) 743 { 744 uint32_t *ib_checksum; 745 746 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */ 747 ib->ptr[ib->length_dw++] = 0x30000002; 748 ib_checksum = &ib->ptr[ib->length_dw++]; 749 ib->ptr[ib->length_dw++] = ib_pack_in_dw; 750 751 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */ 752 ib->ptr[ib->length_dw++] = 0x30000001; 753 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3; 754 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t); 755 756 return ib_checksum; 757 } 758 759 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum, 760 uint32_t ib_pack_in_dw) 761 { 762 uint32_t i; 763 uint32_t checksum = 0; 764 765 for (i = 0; i < ib_pack_in_dw; i++) 766 checksum += *(*ib_checksum + 2 + i); 767 768 **ib_checksum = checksum; 769 } 770 771 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 772 struct amdgpu_ib *ib_msg, 773 struct dma_fence **fence) 774 { 775 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 776 unsigned int ib_size_dw = 64; 777 struct amdgpu_device *adev = ring->adev; 778 struct dma_fence *f = NULL; 779 struct amdgpu_job *job; 780 struct amdgpu_ib *ib; 781 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 782 uint32_t *ib_checksum; 783 uint32_t ib_pack_in_dw; 784 int i, r; 785 786 if (adev->vcn.inst[ring->me].using_unified_queue) 787 ib_size_dw += 8; 788 789 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 790 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 791 &job); 792 if (r) 793 goto err; 794 795 ib = &job->ibs[0]; 796 ib->length_dw = 0; 797 798 /* single queue headers */ 799 if (adev->vcn.inst[ring->me].using_unified_queue) { 800 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t) 801 + 4 + 2; /* engine info + decoding ib in dw */ 802 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false); 803 } 804 805 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 806 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 807 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 808 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 809 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 810 811 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 812 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 813 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 814 815 for (i = ib->length_dw; i < ib_size_dw; ++i) 816 ib->ptr[i] = 0x0; 817 818 if (adev->vcn.inst[ring->me].using_unified_queue) 819 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw); 820 821 r = amdgpu_job_submit_direct(job, ring, &f); 822 if (r) 823 goto err_free; 824 825 amdgpu_ib_free(ib_msg, f); 826 827 if (fence) 828 *fence = dma_fence_get(f); 829 dma_fence_put(f); 830 831 return 0; 832 833 err_free: 834 amdgpu_job_free(job); 835 err: 836 amdgpu_ib_free(ib_msg, f); 837 return r; 838 } 839 840 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 841 { 842 struct dma_fence *fence = NULL; 843 struct amdgpu_ib ib; 844 long r; 845 846 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 847 if (r) 848 goto error; 849 850 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 851 if (r) 852 goto error; 853 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 854 if (r) 855 goto error; 856 857 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 858 if (r) 859 goto error; 860 861 r = dma_fence_wait_timeout(fence, false, timeout); 862 if (r == 0) 863 r = -ETIMEDOUT; 864 else if (r > 0) 865 r = 0; 866 867 dma_fence_put(fence); 868 error: 869 return r; 870 } 871 872 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 873 { 874 struct amdgpu_device *adev = ring->adev; 875 uint32_t rptr; 876 unsigned int i; 877 int r; 878 879 if (amdgpu_sriov_vf(adev)) 880 return 0; 881 882 r = amdgpu_ring_alloc(ring, 16); 883 if (r) 884 return r; 885 886 rptr = amdgpu_ring_get_rptr(ring); 887 888 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 889 amdgpu_ring_commit(ring); 890 891 for (i = 0; i < adev->usec_timeout; i++) { 892 if (amdgpu_ring_get_rptr(ring) != rptr) 893 break; 894 udelay(1); 895 } 896 897 if (i >= adev->usec_timeout) 898 r = -ETIMEDOUT; 899 900 return r; 901 } 902 903 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 904 struct amdgpu_ib *ib_msg, 905 struct dma_fence **fence) 906 { 907 unsigned int ib_size_dw = 16; 908 struct amdgpu_device *adev = ring->adev; 909 struct amdgpu_job *job; 910 struct amdgpu_ib *ib; 911 struct dma_fence *f = NULL; 912 uint32_t *ib_checksum = NULL; 913 uint64_t addr; 914 int i, r; 915 916 if (adev->vcn.inst[ring->me].using_unified_queue) 917 ib_size_dw += 8; 918 919 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 920 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 921 &job); 922 if (r) 923 return r; 924 925 ib = &job->ibs[0]; 926 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 927 928 ib->length_dw = 0; 929 930 if (adev->vcn.inst[ring->me].using_unified_queue) 931 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 932 933 ib->ptr[ib->length_dw++] = 0x00000018; 934 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 935 ib->ptr[ib->length_dw++] = handle; 936 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 937 ib->ptr[ib->length_dw++] = addr; 938 ib->ptr[ib->length_dw++] = 0x00000000; 939 940 ib->ptr[ib->length_dw++] = 0x00000014; 941 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 942 ib->ptr[ib->length_dw++] = 0x0000001c; 943 ib->ptr[ib->length_dw++] = 0x00000000; 944 ib->ptr[ib->length_dw++] = 0x00000000; 945 946 ib->ptr[ib->length_dw++] = 0x00000008; 947 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 948 949 for (i = ib->length_dw; i < ib_size_dw; ++i) 950 ib->ptr[i] = 0x0; 951 952 if (adev->vcn.inst[ring->me].using_unified_queue) 953 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 954 955 r = amdgpu_job_submit_direct(job, ring, &f); 956 if (r) 957 goto err; 958 959 if (fence) 960 *fence = dma_fence_get(f); 961 dma_fence_put(f); 962 963 return 0; 964 965 err: 966 amdgpu_job_free(job); 967 return r; 968 } 969 970 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 971 struct amdgpu_ib *ib_msg, 972 struct dma_fence **fence) 973 { 974 unsigned int ib_size_dw = 16; 975 struct amdgpu_device *adev = ring->adev; 976 struct amdgpu_job *job; 977 struct amdgpu_ib *ib; 978 struct dma_fence *f = NULL; 979 uint32_t *ib_checksum = NULL; 980 uint64_t addr; 981 int i, r; 982 983 if (adev->vcn.inst[ring->me].using_unified_queue) 984 ib_size_dw += 8; 985 986 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 987 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 988 &job); 989 if (r) 990 return r; 991 992 ib = &job->ibs[0]; 993 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 994 995 ib->length_dw = 0; 996 997 if (adev->vcn.inst[ring->me].using_unified_queue) 998 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 999 1000 ib->ptr[ib->length_dw++] = 0x00000018; 1001 ib->ptr[ib->length_dw++] = 0x00000001; 1002 ib->ptr[ib->length_dw++] = handle; 1003 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1004 ib->ptr[ib->length_dw++] = addr; 1005 ib->ptr[ib->length_dw++] = 0x00000000; 1006 1007 ib->ptr[ib->length_dw++] = 0x00000014; 1008 ib->ptr[ib->length_dw++] = 0x00000002; 1009 ib->ptr[ib->length_dw++] = 0x0000001c; 1010 ib->ptr[ib->length_dw++] = 0x00000000; 1011 ib->ptr[ib->length_dw++] = 0x00000000; 1012 1013 ib->ptr[ib->length_dw++] = 0x00000008; 1014 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 1015 1016 for (i = ib->length_dw; i < ib_size_dw; ++i) 1017 ib->ptr[i] = 0x0; 1018 1019 if (adev->vcn.inst[ring->me].using_unified_queue) 1020 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 1021 1022 r = amdgpu_job_submit_direct(job, ring, &f); 1023 if (r) 1024 goto err; 1025 1026 if (fence) 1027 *fence = dma_fence_get(f); 1028 dma_fence_put(f); 1029 1030 return 0; 1031 1032 err: 1033 amdgpu_job_free(job); 1034 return r; 1035 } 1036 1037 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1038 { 1039 struct amdgpu_device *adev = ring->adev; 1040 struct dma_fence *fence = NULL; 1041 struct amdgpu_ib ib; 1042 long r; 1043 1044 memset(&ib, 0, sizeof(ib)); 1045 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 1046 AMDGPU_IB_POOL_DIRECT, 1047 &ib); 1048 if (r) 1049 return r; 1050 1051 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 1052 if (r) 1053 goto error; 1054 1055 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 1056 if (r) 1057 goto error; 1058 1059 r = dma_fence_wait_timeout(fence, false, timeout); 1060 if (r == 0) 1061 r = -ETIMEDOUT; 1062 else if (r > 0) 1063 r = 0; 1064 1065 error: 1066 amdgpu_ib_free(&ib, fence); 1067 dma_fence_put(fence); 1068 1069 return r; 1070 } 1071 1072 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1073 { 1074 struct amdgpu_device *adev = ring->adev; 1075 long r; 1076 1077 if ((amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(4, 0, 3)) && 1078 (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(5, 0, 1))) { 1079 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout); 1080 if (r) 1081 goto error; 1082 } 1083 1084 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout); 1085 1086 error: 1087 return r; 1088 } 1089 1090 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 1091 { 1092 switch (ring) { 1093 case 0: 1094 return AMDGPU_RING_PRIO_0; 1095 case 1: 1096 return AMDGPU_RING_PRIO_1; 1097 case 2: 1098 return AMDGPU_RING_PRIO_2; 1099 default: 1100 return AMDGPU_RING_PRIO_0; 1101 } 1102 } 1103 1104 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev, int i) 1105 { 1106 unsigned int idx; 1107 1108 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1109 const struct common_firmware_header *hdr; 1110 1111 if (adev->vcn.harvest_config & (1 << i)) 1112 return; 1113 1114 if ((amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 3) || 1115 amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(5, 0, 1)) 1116 && (i > 0)) 1117 return; 1118 1119 hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data; 1120 /* currently only support 2 FW instances */ 1121 if (i >= 2) { 1122 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 1123 return; 1124 } 1125 idx = AMDGPU_UCODE_ID_VCN + i; 1126 adev->firmware.ucode[idx].ucode_id = idx; 1127 adev->firmware.ucode[idx].fw = adev->vcn.inst[i].fw; 1128 adev->firmware.fw_size += 1129 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 1130 } 1131 } 1132 1133 /* 1134 * debugfs for mapping vcn firmware log buffer. 1135 */ 1136 #if defined(CONFIG_DEBUG_FS) 1137 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf, 1138 size_t size, loff_t *pos) 1139 { 1140 struct amdgpu_vcn_inst *vcn; 1141 void *log_buf; 1142 volatile struct amdgpu_vcn_fwlog *plog; 1143 unsigned int read_pos, write_pos, available, i, read_bytes = 0; 1144 unsigned int read_num[2] = {0}; 1145 1146 vcn = file_inode(f)->i_private; 1147 if (!vcn) 1148 return -ENODEV; 1149 1150 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log) 1151 return -EFAULT; 1152 1153 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1154 1155 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf; 1156 read_pos = plog->rptr; 1157 write_pos = plog->wptr; 1158 1159 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE) 1160 return -EFAULT; 1161 1162 if (!size || (read_pos == write_pos)) 1163 return 0; 1164 1165 if (write_pos > read_pos) { 1166 available = write_pos - read_pos; 1167 read_num[0] = min_t(size_t, size, available); 1168 } else { 1169 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos; 1170 available = read_num[0] + write_pos - plog->header_size; 1171 if (size > available) 1172 read_num[1] = write_pos - plog->header_size; 1173 else if (size > read_num[0]) 1174 read_num[1] = size - read_num[0]; 1175 else 1176 read_num[0] = size; 1177 } 1178 1179 for (i = 0; i < 2; i++) { 1180 if (read_num[i]) { 1181 if (read_pos == AMDGPU_VCNFW_LOG_SIZE) 1182 read_pos = plog->header_size; 1183 if (read_num[i] == copy_to_user((buf + read_bytes), 1184 (log_buf + read_pos), read_num[i])) 1185 return -EFAULT; 1186 1187 read_bytes += read_num[i]; 1188 read_pos += read_num[i]; 1189 } 1190 } 1191 1192 plog->rptr = read_pos; 1193 *pos += read_bytes; 1194 return read_bytes; 1195 } 1196 1197 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = { 1198 .owner = THIS_MODULE, 1199 .read = amdgpu_debugfs_vcn_fwlog_read, 1200 .llseek = default_llseek 1201 }; 1202 #endif 1203 1204 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i, 1205 struct amdgpu_vcn_inst *vcn) 1206 { 1207 #if defined(CONFIG_DEBUG_FS) 1208 struct drm_minor *minor = adev_to_drm(adev)->primary; 1209 struct dentry *root = minor->debugfs_root; 1210 char name[32]; 1211 1212 sprintf(name, "amdgpu_vcn_%d_fwlog", i); 1213 debugfs_create_file_size(name, S_IFREG | 0444, root, vcn, 1214 &amdgpu_debugfs_vcnfwlog_fops, 1215 AMDGPU_VCNFW_LOG_SIZE); 1216 #endif 1217 } 1218 1219 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn) 1220 { 1221 #if defined(CONFIG_DEBUG_FS) 1222 volatile uint32_t *flag = vcn->fw_shared.cpu_addr; 1223 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1224 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size; 1225 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr; 1226 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr 1227 + vcn->fw_shared.log_offset; 1228 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG); 1229 fw_log->is_enabled = 1; 1230 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF); 1231 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32); 1232 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE); 1233 1234 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog); 1235 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE; 1236 log_buf->rptr = log_buf->header_size; 1237 log_buf->wptr = log_buf->header_size; 1238 log_buf->wrapped = 0; 1239 #endif 1240 } 1241 1242 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, 1243 struct amdgpu_irq_src *source, 1244 struct amdgpu_iv_entry *entry) 1245 { 1246 struct ras_common_if *ras_if = adev->vcn.ras_if; 1247 struct ras_dispatch_if ih_data = { 1248 .entry = entry, 1249 }; 1250 1251 if (!ras_if) 1252 return 0; 1253 1254 if (!amdgpu_sriov_vf(adev)) { 1255 ih_data.head = *ras_if; 1256 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 1257 } else { 1258 if (adev->virt.ops && adev->virt.ops->ras_poison_handler) 1259 adev->virt.ops->ras_poison_handler(adev, ras_if->block); 1260 else 1261 dev_warn(adev->dev, 1262 "No ras_poison_handler interface in SRIOV for VCN!\n"); 1263 } 1264 1265 return 0; 1266 } 1267 1268 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1269 { 1270 int r, i; 1271 1272 r = amdgpu_ras_block_late_init(adev, ras_block); 1273 if (r) 1274 return r; 1275 1276 if (amdgpu_ras_is_supported(adev, ras_block->block)) { 1277 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1278 if (adev->vcn.harvest_config & (1 << i) || 1279 !adev->vcn.inst[i].ras_poison_irq.funcs) 1280 continue; 1281 1282 r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0); 1283 if (r) 1284 goto late_fini; 1285 } 1286 } 1287 return 0; 1288 1289 late_fini: 1290 amdgpu_ras_block_late_fini(adev, ras_block); 1291 return r; 1292 } 1293 1294 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev) 1295 { 1296 int err; 1297 struct amdgpu_vcn_ras *ras; 1298 1299 if (!adev->vcn.ras) 1300 return 0; 1301 1302 ras = adev->vcn.ras; 1303 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 1304 if (err) { 1305 dev_err(adev->dev, "Failed to register vcn ras block!\n"); 1306 return err; 1307 } 1308 1309 strcpy(ras->ras_block.ras_comm.name, "vcn"); 1310 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; 1311 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; 1312 adev->vcn.ras_if = &ras->ras_block.ras_comm; 1313 1314 if (!ras->ras_block.ras_late_init) 1315 ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init; 1316 1317 return 0; 1318 } 1319 1320 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, 1321 enum AMDGPU_UCODE_ID ucode_id) 1322 { 1323 struct amdgpu_firmware_info ucode = { 1324 .ucode_id = (ucode_id ? ucode_id : 1325 (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 1326 AMDGPU_UCODE_ID_VCN0_RAM)), 1327 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1328 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1329 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr), 1330 }; 1331 1332 return psp_execute_ip_fw_load(&adev->psp, &ucode); 1333 } 1334 1335 static ssize_t amdgpu_get_vcn_reset_mask(struct device *dev, 1336 struct device_attribute *attr, 1337 char *buf) 1338 { 1339 struct drm_device *ddev = dev_get_drvdata(dev); 1340 struct amdgpu_device *adev = drm_to_adev(ddev); 1341 1342 if (!adev) 1343 return -ENODEV; 1344 1345 return amdgpu_show_reset_mask(buf, adev->vcn.supported_reset); 1346 } 1347 1348 static DEVICE_ATTR(vcn_reset_mask, 0444, 1349 amdgpu_get_vcn_reset_mask, NULL); 1350 1351 int amdgpu_vcn_sysfs_reset_mask_init(struct amdgpu_device *adev) 1352 { 1353 int r = 0; 1354 1355 if (adev->vcn.num_vcn_inst) { 1356 r = device_create_file(adev->dev, &dev_attr_vcn_reset_mask); 1357 if (r) 1358 return r; 1359 } 1360 1361 return r; 1362 } 1363 1364 void amdgpu_vcn_sysfs_reset_mask_fini(struct amdgpu_device *adev) 1365 { 1366 if (adev->dev->kobj.sd) { 1367 if (adev->vcn.num_vcn_inst) 1368 device_remove_file(adev->dev, &dev_attr_vcn_reset_mask); 1369 } 1370 } 1371 1372 /* 1373 * debugfs to enable/disable vcn job submission to specific core or 1374 * instance. It is created only if the queue type is unified. 1375 */ 1376 #if defined(CONFIG_DEBUG_FS) 1377 static int amdgpu_debugfs_vcn_sched_mask_set(void *data, u64 val) 1378 { 1379 struct amdgpu_device *adev = (struct amdgpu_device *)data; 1380 u32 i; 1381 u64 mask; 1382 struct amdgpu_ring *ring; 1383 1384 if (!adev) 1385 return -ENODEV; 1386 1387 mask = (1ULL << adev->vcn.num_vcn_inst) - 1; 1388 if ((val & mask) == 0) 1389 return -EINVAL; 1390 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1391 ring = &adev->vcn.inst[i].ring_enc[0]; 1392 if (val & (1ULL << i)) 1393 ring->sched.ready = true; 1394 else 1395 ring->sched.ready = false; 1396 } 1397 /* publish sched.ready flag update effective immediately across smp */ 1398 smp_rmb(); 1399 return 0; 1400 } 1401 1402 static int amdgpu_debugfs_vcn_sched_mask_get(void *data, u64 *val) 1403 { 1404 struct amdgpu_device *adev = (struct amdgpu_device *)data; 1405 u32 i; 1406 u64 mask = 0; 1407 struct amdgpu_ring *ring; 1408 1409 if (!adev) 1410 return -ENODEV; 1411 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1412 ring = &adev->vcn.inst[i].ring_enc[0]; 1413 if (ring->sched.ready) 1414 mask |= 1ULL << i; 1415 } 1416 *val = mask; 1417 return 0; 1418 } 1419 1420 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_vcn_sched_mask_fops, 1421 amdgpu_debugfs_vcn_sched_mask_get, 1422 amdgpu_debugfs_vcn_sched_mask_set, "%llx\n"); 1423 #endif 1424 1425 void amdgpu_debugfs_vcn_sched_mask_init(struct amdgpu_device *adev) 1426 { 1427 #if defined(CONFIG_DEBUG_FS) 1428 struct drm_minor *minor = adev_to_drm(adev)->primary; 1429 struct dentry *root = minor->debugfs_root; 1430 char name[32]; 1431 1432 if (adev->vcn.num_vcn_inst <= 1 || !adev->vcn.inst[0].using_unified_queue) 1433 return; 1434 sprintf(name, "amdgpu_vcn_sched_mask"); 1435 debugfs_create_file(name, 0600, root, adev, 1436 &amdgpu_debugfs_vcn_sched_mask_fops); 1437 #endif 1438 } 1439 1440 /** 1441 * vcn_set_powergating_state - set VCN block powergating state 1442 * 1443 * @ip_block: amdgpu_ip_block pointer 1444 * @state: power gating state 1445 * 1446 * Set VCN block powergating state 1447 */ 1448 int vcn_set_powergating_state(struct amdgpu_ip_block *ip_block, 1449 enum amd_powergating_state state) 1450 { 1451 struct amdgpu_device *adev = ip_block->adev; 1452 int ret = 0, i; 1453 1454 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1455 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1456 1457 ret |= vinst->set_pg_state(vinst, state); 1458 } 1459 1460 return ret; 1461 } 1462 1463 /** 1464 * amdgpu_vcn_reset_engine - Reset a specific VCN engine 1465 * @adev: Pointer to the AMDGPU device 1466 * @instance_id: VCN engine instance to reset 1467 * 1468 * Returns: 0 on success, or a negative error code on failure. 1469 */ 1470 static int amdgpu_vcn_reset_engine(struct amdgpu_device *adev, 1471 uint32_t instance_id) 1472 { 1473 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[instance_id]; 1474 int r, i; 1475 1476 mutex_lock(&vinst->engine_reset_mutex); 1477 /* Stop the scheduler's work queue for the dec and enc rings if they are running. 1478 * This ensures that no new tasks are submitted to the queues while 1479 * the reset is in progress. 1480 */ 1481 drm_sched_wqueue_stop(&vinst->ring_dec.sched); 1482 for (i = 0; i < vinst->num_enc_rings; i++) 1483 drm_sched_wqueue_stop(&vinst->ring_enc[i].sched); 1484 1485 /* Perform the VCN reset for the specified instance */ 1486 r = vinst->reset(vinst); 1487 if (r) 1488 goto unlock; 1489 r = amdgpu_ring_test_ring(&vinst->ring_dec); 1490 if (r) 1491 goto unlock; 1492 for (i = 0; i < vinst->num_enc_rings; i++) { 1493 r = amdgpu_ring_test_ring(&vinst->ring_enc[i]); 1494 if (r) 1495 goto unlock; 1496 } 1497 amdgpu_fence_driver_force_completion(&vinst->ring_dec); 1498 for (i = 0; i < vinst->num_enc_rings; i++) 1499 amdgpu_fence_driver_force_completion(&vinst->ring_enc[i]); 1500 1501 /* Restart the scheduler's work queue for the dec and enc rings 1502 * if they were stopped by this function. This allows new tasks 1503 * to be submitted to the queues after the reset is complete. 1504 */ 1505 drm_sched_wqueue_start(&vinst->ring_dec.sched); 1506 for (i = 0; i < vinst->num_enc_rings; i++) 1507 drm_sched_wqueue_start(&vinst->ring_enc[i].sched); 1508 1509 unlock: 1510 mutex_unlock(&vinst->engine_reset_mutex); 1511 1512 return r; 1513 } 1514 1515 /** 1516 * amdgpu_vcn_ring_reset - Reset a VCN ring 1517 * @ring: ring to reset 1518 * @vmid: vmid of guilty job 1519 * @timedout_fence: fence of timed out job 1520 * 1521 * This helper is for VCN blocks without unified queues because 1522 * resetting the engine resets all queues in that case. With 1523 * unified queues we have one queue per engine. 1524 * Returns: 0 on success, or a negative error code on failure. 1525 */ 1526 int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring, 1527 unsigned int vmid, 1528 struct amdgpu_fence *timedout_fence) 1529 { 1530 struct amdgpu_device *adev = ring->adev; 1531 1532 if (adev->vcn.inst[ring->me].using_unified_queue) 1533 return -EINVAL; 1534 1535 return amdgpu_vcn_reset_engine(adev, ring->me); 1536 } 1537 1538 int amdgpu_vcn_reg_dump_init(struct amdgpu_device *adev, 1539 const struct amdgpu_hwip_reg_entry *reg, u32 count) 1540 { 1541 adev->vcn.ip_dump = kcalloc(adev->vcn.num_vcn_inst * count, 1542 sizeof(uint32_t), GFP_KERNEL); 1543 if (!adev->vcn.ip_dump) 1544 return -ENOMEM; 1545 adev->vcn.reg_list = reg; 1546 adev->vcn.reg_count = count; 1547 1548 return 0; 1549 } 1550 1551 static void amdgpu_vcn_reg_dump_fini(struct amdgpu_device *adev) 1552 { 1553 kfree(adev->vcn.ip_dump); 1554 adev->vcn.ip_dump = NULL; 1555 adev->vcn.reg_list = NULL; 1556 adev->vcn.reg_count = 0; 1557 } 1558 1559 void amdgpu_vcn_dump_ip_state(struct amdgpu_ip_block *ip_block) 1560 { 1561 struct amdgpu_device *adev = ip_block->adev; 1562 int i, j; 1563 bool is_powered; 1564 u32 inst_off; 1565 1566 if (!adev->vcn.ip_dump) 1567 return; 1568 1569 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1570 if (adev->vcn.harvest_config & (1 << i)) 1571 continue; 1572 1573 inst_off = i * adev->vcn.reg_count; 1574 /* mmUVD_POWER_STATUS is always readable and is the first in reg_list */ 1575 adev->vcn.ip_dump[inst_off] = 1576 RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->vcn.reg_list[0], i)); 1577 is_powered = (adev->vcn.ip_dump[inst_off] & 1578 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF) != 1579 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 1580 1581 if (is_powered) 1582 for (j = 1; j < adev->vcn.reg_count; j++) 1583 adev->vcn.ip_dump[inst_off + j] = 1584 RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->vcn.reg_list[j], i)); 1585 } 1586 } 1587 1588 void amdgpu_vcn_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1589 { 1590 struct amdgpu_device *adev = ip_block->adev; 1591 int i, j; 1592 bool is_powered; 1593 u32 inst_off; 1594 1595 if (!adev->vcn.ip_dump) 1596 return; 1597 1598 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 1599 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1600 if (adev->vcn.harvest_config & (1 << i)) { 1601 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 1602 continue; 1603 } 1604 1605 inst_off = i * adev->vcn.reg_count; 1606 is_powered = (adev->vcn.ip_dump[inst_off] & 1607 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF) != 1608 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 1609 1610 if (is_powered) { 1611 drm_printf(p, "\nActive Instance:VCN%d\n", i); 1612 for (j = 0; j < adev->vcn.reg_count; j++) 1613 drm_printf(p, "%-50s \t 0x%08x\n", adev->vcn.reg_list[j].reg_name, 1614 adev->vcn.ip_dump[inst_off + j]); 1615 } else { 1616 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 1617 } 1618 } 1619 } 1620