1 /* 2 * Copyright 2016-2024 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/dmi.h> 30 #include <linux/pci.h> 31 #include <linux/debugfs.h> 32 #include <drm/drm_drv.h> 33 34 #include "amdgpu.h" 35 #include "amdgpu_pm.h" 36 #include "amdgpu_vcn.h" 37 #include "amdgpu_reset.h" 38 #include "soc15d.h" 39 40 /* Firmware Names */ 41 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 42 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 43 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 44 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 45 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 46 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 47 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 48 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 49 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 50 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 51 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 52 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 53 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 54 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 55 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 56 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 57 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin" 58 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin" 59 #define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin" 60 #define FIRMWARE_VCN4_0_3 "amdgpu/vcn_4_0_3.bin" 61 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin" 62 #define FIRMWARE_VCN4_0_5 "amdgpu/vcn_4_0_5.bin" 63 #define FIRMWARE_VCN4_0_6 "amdgpu/vcn_4_0_6.bin" 64 #define FIRMWARE_VCN4_0_6_1 "amdgpu/vcn_4_0_6_1.bin" 65 #define FIRMWARE_VCN5_0_0 "amdgpu/vcn_5_0_0.bin" 66 #define FIRMWARE_VCN5_0_1 "amdgpu/vcn_5_0_1.bin" 67 #define FIRMWARE_VCN5_0_2 "amdgpu/vcn_5_0_2.bin" 68 #define FIRMWARE_VCN5_3_0 "amdgpu/vcn_5_3_0.bin" 69 70 MODULE_FIRMWARE(FIRMWARE_RAVEN); 71 MODULE_FIRMWARE(FIRMWARE_PICASSO); 72 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 73 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 74 MODULE_FIRMWARE(FIRMWARE_RENOIR); 75 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 76 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 77 MODULE_FIRMWARE(FIRMWARE_NAVI10); 78 MODULE_FIRMWARE(FIRMWARE_NAVI14); 79 MODULE_FIRMWARE(FIRMWARE_NAVI12); 80 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 81 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 82 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 83 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 84 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 85 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 86 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2); 87 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0); 88 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2); 89 MODULE_FIRMWARE(FIRMWARE_VCN4_0_3); 90 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4); 91 MODULE_FIRMWARE(FIRMWARE_VCN4_0_5); 92 MODULE_FIRMWARE(FIRMWARE_VCN4_0_6); 93 MODULE_FIRMWARE(FIRMWARE_VCN4_0_6_1); 94 MODULE_FIRMWARE(FIRMWARE_VCN5_0_0); 95 MODULE_FIRMWARE(FIRMWARE_VCN5_0_1); 96 MODULE_FIRMWARE(FIRMWARE_VCN5_0_2); 97 MODULE_FIRMWARE(FIRMWARE_VCN5_3_0); 98 99 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 100 static void amdgpu_vcn_reg_dump_fini(struct amdgpu_device *adev); 101 102 int amdgpu_vcn_early_init(struct amdgpu_device *adev, int i) 103 { 104 char ucode_prefix[25]; 105 int r; 106 107 adev->vcn.inst[i].adev = adev; 108 adev->vcn.inst[i].inst = i; 109 amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix)); 110 111 if (i != 0 && adev->vcn.per_inst_fw) { 112 r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw, 113 AMDGPU_UCODE_REQUIRED, 114 "amdgpu/%s_%d.bin", ucode_prefix, i); 115 if (r) 116 amdgpu_ucode_release(&adev->vcn.inst[i].fw); 117 } else { 118 if (!adev->vcn.inst[0].fw) { 119 r = amdgpu_ucode_request(adev, &adev->vcn.inst[0].fw, 120 AMDGPU_UCODE_REQUIRED, 121 "amdgpu/%s.bin", ucode_prefix); 122 if (r) 123 amdgpu_ucode_release(&adev->vcn.inst[0].fw); 124 } else { 125 r = 0; 126 } 127 adev->vcn.inst[i].fw = adev->vcn.inst[0].fw; 128 } 129 130 return r; 131 } 132 133 int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int i) 134 { 135 unsigned long bo_size; 136 const struct common_firmware_header *hdr; 137 unsigned char fw_check; 138 unsigned int fw_shared_size, log_offset; 139 int r; 140 141 mutex_init(&adev->vcn.inst[i].vcn1_jpeg1_workaround); 142 mutex_init(&adev->vcn.inst[i].vcn_pg_lock); 143 mutex_init(&adev->vcn.inst[i].engine_reset_mutex); 144 atomic_set(&adev->vcn.inst[i].total_submission_cnt, 0); 145 INIT_DELAYED_WORK(&adev->vcn.inst[i].idle_work, amdgpu_vcn_idle_work_handler); 146 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 147 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 148 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 149 adev->vcn.inst[i].indirect_sram = true; 150 151 /* 152 * Some Steam Deck's BIOS versions are incompatible with the 153 * indirect SRAM mode, leading to amdgpu being unable to get 154 * properly probed (and even potentially crashing the kernel). 155 * Hence, check for these versions here - notice this is 156 * restricted to Vangogh (Deck's APU). 157 */ 158 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 0, 2)) { 159 const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION); 160 161 if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) || 162 !strncmp("F7A0114", bios_ver, 7))) { 163 adev->vcn.inst[i].indirect_sram = false; 164 dev_info(adev->dev, 165 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver); 166 } 167 } 168 169 /* from vcn4 and above, only unified queue is used */ 170 adev->vcn.inst[i].using_unified_queue = 171 amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0); 172 173 hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data; 174 adev->vcn.inst[i].fw_version = le32_to_cpu(hdr->ucode_version); 175 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 176 177 /* Bit 20-23, it is encode major and non-zero for new naming convention. 178 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 179 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 180 * is zero in old naming convention, this field is always zero so far. 181 * These four bits are used to tell which naming convention is present. 182 */ 183 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 184 if (fw_check) { 185 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 186 187 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 188 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 189 enc_major = fw_check; 190 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 191 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 192 dev_info(adev->dev, 193 "[VCN instance %d] Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 194 i, enc_major, enc_minor, dec_ver, vep, fw_rev); 195 } else { 196 unsigned int version_major, version_minor, family_id; 197 198 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 199 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 200 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 201 dev_info(adev->dev, "[VCN instance %d] Found VCN firmware Version: %u.%u Family ID: %u\n", 202 i, version_major, version_minor, family_id); 203 } 204 205 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 206 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 207 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 208 209 if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(5, 0, 0)) { 210 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)); 211 log_offset = offsetof(struct amdgpu_vcn5_fw_shared, fw_log); 212 } else if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) { 213 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); 214 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log); 215 } else { 216 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 217 log_offset = offsetof(struct amdgpu_fw_shared, fw_log); 218 } 219 220 bo_size += fw_shared_size; 221 222 if (amdgpu_vcnfw_log) 223 bo_size += AMDGPU_VCNFW_LOG_SIZE; 224 225 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 226 AMDGPU_GEM_DOMAIN_VRAM | 227 AMDGPU_GEM_DOMAIN_GTT, 228 &adev->vcn.inst[i].vcpu_bo, 229 &adev->vcn.inst[i].gpu_addr, 230 &adev->vcn.inst[i].cpu_addr); 231 if (r) { 232 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 233 return r; 234 } 235 236 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr + 237 bo_size - fw_shared_size; 238 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr + 239 bo_size - fw_shared_size; 240 241 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size; 242 243 if (amdgpu_vcnfw_log) { 244 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 245 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 246 adev->vcn.inst[i].fw_shared.log_offset = log_offset; 247 } 248 249 if (adev->vcn.inst[i].indirect_sram) { 250 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 251 AMDGPU_GEM_DOMAIN_VRAM | 252 AMDGPU_GEM_DOMAIN_GTT, 253 &adev->vcn.inst[i].dpg_sram_bo, 254 &adev->vcn.inst[i].dpg_sram_gpu_addr, 255 &adev->vcn.inst[i].dpg_sram_cpu_addr); 256 if (r) { 257 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 258 return r; 259 } 260 } 261 262 return 0; 263 } 264 265 void amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int i) 266 { 267 int j; 268 269 if (adev->vcn.harvest_config & (1 << i)) 270 return; 271 272 amdgpu_bo_free_kernel( 273 &adev->vcn.inst[i].dpg_sram_bo, 274 &adev->vcn.inst[i].dpg_sram_gpu_addr, 275 (void **)&adev->vcn.inst[i].dpg_sram_cpu_addr); 276 277 kvfree(adev->vcn.inst[i].saved_bo); 278 279 amdgpu_bo_free_kernel(&adev->vcn.inst[i].vcpu_bo, 280 &adev->vcn.inst[i].gpu_addr, 281 (void **)&adev->vcn.inst[i].cpu_addr); 282 283 amdgpu_ring_fini(&adev->vcn.inst[i].ring_dec); 284 285 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) 286 amdgpu_ring_fini(&adev->vcn.inst[i].ring_enc[j]); 287 288 if (adev->vcn.per_inst_fw) { 289 amdgpu_ucode_release(&adev->vcn.inst[i].fw); 290 } else { 291 amdgpu_ucode_release(&adev->vcn.inst[0].fw); 292 adev->vcn.inst[i].fw = NULL; 293 } 294 295 if (adev->vcn.reg_list) 296 amdgpu_vcn_reg_dump_fini(adev); 297 298 mutex_destroy(&adev->vcn.inst[i].vcn_pg_lock); 299 mutex_destroy(&adev->vcn.inst[i].vcn1_jpeg1_workaround); 300 } 301 302 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 303 { 304 bool ret = false; 305 int vcn_config = adev->vcn.inst[vcn_instance].vcn_config; 306 307 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) 308 ret = true; 309 else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) 310 ret = true; 311 else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) 312 ret = true; 313 314 return ret; 315 } 316 317 static int amdgpu_vcn_save_vcpu_bo_inst(struct amdgpu_device *adev, int i) 318 { 319 unsigned int size; 320 void *ptr; 321 int idx; 322 323 if (adev->vcn.harvest_config & (1 << i)) 324 return 0; 325 if (adev->vcn.inst[i].vcpu_bo == NULL) 326 return 0; 327 328 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 329 ptr = adev->vcn.inst[i].cpu_addr; 330 331 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 332 if (!adev->vcn.inst[i].saved_bo) 333 return -ENOMEM; 334 335 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 336 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 337 drm_dev_exit(idx); 338 } 339 340 return 0; 341 } 342 343 int amdgpu_vcn_save_vcpu_bo(struct amdgpu_device *adev) 344 { 345 int ret, i; 346 347 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 348 ret = amdgpu_vcn_save_vcpu_bo_inst(adev, i); 349 if (ret) 350 return ret; 351 } 352 353 return 0; 354 } 355 356 int amdgpu_vcn_suspend(struct amdgpu_device *adev, int i) 357 { 358 bool in_ras_intr = amdgpu_ras_intr_triggered(); 359 360 if (adev->vcn.harvest_config & (1 << i)) 361 return 0; 362 363 /* err_event_athub and dpc recovery will corrupt VCPU buffer, so we need to 364 * restore fw data and clear buffer in amdgpu_vcn_resume() */ 365 if (in_ras_intr || amdgpu_reset_in_dpc(adev)) 366 return 0; 367 368 return amdgpu_vcn_save_vcpu_bo_inst(adev, i); 369 } 370 371 int amdgpu_vcn_resume(struct amdgpu_device *adev, int i) 372 { 373 unsigned int size; 374 void *ptr; 375 int idx; 376 377 if (adev->vcn.harvest_config & (1 << i)) 378 return 0; 379 if (adev->vcn.inst[i].vcpu_bo == NULL) 380 return -EINVAL; 381 382 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 383 ptr = adev->vcn.inst[i].cpu_addr; 384 385 if (adev->vcn.inst[i].saved_bo != NULL) { 386 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 387 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 388 drm_dev_exit(idx); 389 } 390 kvfree(adev->vcn.inst[i].saved_bo); 391 adev->vcn.inst[i].saved_bo = NULL; 392 } else { 393 const struct common_firmware_header *hdr; 394 unsigned int offset; 395 396 hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data; 397 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 398 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 399 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 400 memcpy_toio(adev->vcn.inst[i].cpu_addr, 401 adev->vcn.inst[i].fw->data + offset, 402 le32_to_cpu(hdr->ucode_size_bytes)); 403 drm_dev_exit(idx); 404 } 405 size -= le32_to_cpu(hdr->ucode_size_bytes); 406 ptr += le32_to_cpu(hdr->ucode_size_bytes); 407 } 408 memset_io(ptr, 0, size); 409 } 410 411 return 0; 412 } 413 414 void amdgpu_vcn_get_profile(struct amdgpu_device *adev) 415 { 416 int r; 417 418 mutex_lock(&adev->vcn.workload_profile_mutex); 419 420 if (adev->vcn.workload_profile_active) { 421 mutex_unlock(&adev->vcn.workload_profile_mutex); 422 return; 423 } 424 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 425 true); 426 if (r) 427 dev_warn(adev->dev, 428 "(%d) failed to enable video power profile mode\n", r); 429 else 430 adev->vcn.workload_profile_active = true; 431 mutex_unlock(&adev->vcn.workload_profile_mutex); 432 } 433 434 void amdgpu_vcn_put_profile(struct amdgpu_device *adev) 435 { 436 bool pg = true; 437 int r, i; 438 439 mutex_lock(&adev->vcn.workload_profile_mutex); 440 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 441 if (adev->vcn.inst[i].cur_state != AMD_PG_STATE_GATE) { 442 pg = false; 443 break; 444 } 445 } 446 447 if (pg) { 448 r = amdgpu_dpm_switch_power_profile( 449 adev, PP_SMC_POWER_PROFILE_VIDEO, false); 450 if (r) 451 dev_warn( 452 adev->dev, 453 "(%d) failed to disable video power profile mode\n", 454 r); 455 else 456 adev->vcn.workload_profile_active = false; 457 } 458 459 mutex_unlock(&adev->vcn.workload_profile_mutex); 460 } 461 462 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 463 { 464 struct amdgpu_vcn_inst *vcn_inst = 465 container_of(work, struct amdgpu_vcn_inst, idle_work.work); 466 struct amdgpu_device *adev = vcn_inst->adev; 467 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 468 unsigned int i = vcn_inst->inst, j; 469 470 if (adev->vcn.harvest_config & (1 << i)) 471 return; 472 473 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) 474 fence[i] += amdgpu_fence_count_emitted(&vcn_inst->ring_enc[j]); 475 476 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 477 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 478 !adev->vcn.inst[i].using_unified_queue) { 479 struct dpg_pause_state new_state; 480 481 if (fence[i] || 482 unlikely(atomic_read(&vcn_inst->dpg_enc_submission_cnt))) 483 new_state.fw_based = VCN_DPG_STATE__PAUSE; 484 else 485 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 486 487 adev->vcn.inst[i].pause_dpg_mode(vcn_inst, &new_state); 488 } 489 490 fence[i] += amdgpu_fence_count_emitted(&vcn_inst->ring_dec); 491 fences += fence[i]; 492 493 if (!fences && !atomic_read(&vcn_inst->total_submission_cnt)) { 494 mutex_lock(&vcn_inst->vcn_pg_lock); 495 vcn_inst->set_pg_state(vcn_inst, AMD_PG_STATE_GATE); 496 mutex_unlock(&vcn_inst->vcn_pg_lock); 497 amdgpu_vcn_put_profile(adev); 498 499 } else { 500 schedule_delayed_work(&vcn_inst->idle_work, VCN_IDLE_TIMEOUT); 501 } 502 } 503 504 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 505 { 506 struct amdgpu_device *adev = ring->adev; 507 struct amdgpu_vcn_inst *vcn_inst = &adev->vcn.inst[ring->me]; 508 509 if (!atomic_fetch_inc(&vcn_inst->total_submission_cnt)) 510 cancel_delayed_work_sync(&vcn_inst->idle_work); 511 512 mutex_lock(&vcn_inst->vcn_pg_lock); 513 vcn_inst->set_pg_state(vcn_inst, AMD_PG_STATE_UNGATE); 514 515 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 516 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 517 !vcn_inst->using_unified_queue) { 518 struct dpg_pause_state new_state; 519 520 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 521 atomic_inc(&vcn_inst->dpg_enc_submission_cnt); 522 new_state.fw_based = VCN_DPG_STATE__PAUSE; 523 } else { 524 unsigned int fences = 0; 525 unsigned int i; 526 527 for (i = 0; i < vcn_inst->num_enc_rings; ++i) 528 fences += amdgpu_fence_count_emitted(&vcn_inst->ring_enc[i]); 529 530 if (fences || atomic_read(&vcn_inst->dpg_enc_submission_cnt)) 531 new_state.fw_based = VCN_DPG_STATE__PAUSE; 532 else 533 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 534 } 535 536 vcn_inst->pause_dpg_mode(vcn_inst, &new_state); 537 } 538 mutex_unlock(&vcn_inst->vcn_pg_lock); 539 amdgpu_vcn_get_profile(adev); 540 } 541 542 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 543 { 544 struct amdgpu_device *adev = ring->adev; 545 546 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 547 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 548 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC && 549 !adev->vcn.inst[ring->me].using_unified_queue) 550 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 551 552 if (atomic_dec_and_test(&ring->adev->vcn.inst[ring->me].total_submission_cnt)) 553 schedule_delayed_work(&ring->adev->vcn.inst[ring->me].idle_work, 554 VCN_IDLE_TIMEOUT); 555 } 556 557 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 558 { 559 struct amdgpu_device *adev = ring->adev; 560 uint32_t tmp = 0; 561 unsigned int i; 562 int r; 563 564 /* VCN in SRIOV does not support direct register read/write */ 565 if (amdgpu_sriov_vf(adev)) 566 return 0; 567 568 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 569 r = amdgpu_ring_alloc(ring, 3); 570 if (r) 571 return r; 572 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.scratch9, 0)); 573 amdgpu_ring_write(ring, 0xDEADBEEF); 574 amdgpu_ring_commit(ring); 575 for (i = 0; i < adev->usec_timeout; i++) { 576 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 577 if (tmp == 0xDEADBEEF) 578 break; 579 udelay(1); 580 } 581 582 if (i >= adev->usec_timeout) 583 r = -ETIMEDOUT; 584 585 return r; 586 } 587 588 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 589 { 590 struct amdgpu_device *adev = ring->adev; 591 uint32_t rptr; 592 unsigned int i; 593 int r; 594 595 if (amdgpu_sriov_vf(adev)) 596 return 0; 597 598 r = amdgpu_ring_alloc(ring, 16); 599 if (r) 600 return r; 601 602 rptr = amdgpu_ring_get_rptr(ring); 603 604 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 605 amdgpu_ring_commit(ring); 606 607 for (i = 0; i < adev->usec_timeout; i++) { 608 if (amdgpu_ring_get_rptr(ring) != rptr) 609 break; 610 udelay(1); 611 } 612 613 if (i >= adev->usec_timeout) 614 r = -ETIMEDOUT; 615 616 return r; 617 } 618 619 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 620 struct amdgpu_ib *ib_msg, 621 struct dma_fence **fence) 622 { 623 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 624 struct amdgpu_device *adev = ring->adev; 625 struct dma_fence *f = NULL; 626 struct amdgpu_job *job; 627 struct amdgpu_ib *ib; 628 int i, r; 629 630 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 631 64, AMDGPU_IB_POOL_DIRECT, 632 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST, 633 &job); 634 if (r) 635 goto err; 636 637 ib = &job->ibs[0]; 638 ib->ptr[0] = PACKET0(adev->vcn.inst[ring->me].internal.data0, 0); 639 ib->ptr[1] = addr; 640 ib->ptr[2] = PACKET0(adev->vcn.inst[ring->me].internal.data1, 0); 641 ib->ptr[3] = addr >> 32; 642 ib->ptr[4] = PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0); 643 ib->ptr[5] = 0; 644 for (i = 6; i < 16; i += 2) { 645 ib->ptr[i] = PACKET0(adev->vcn.inst[ring->me].internal.nop, 0); 646 ib->ptr[i+1] = 0; 647 } 648 ib->length_dw = 16; 649 650 r = amdgpu_job_submit_direct(job, ring, &f); 651 if (r) 652 goto err_free; 653 654 amdgpu_ib_free(ib_msg, f); 655 656 if (fence) 657 *fence = dma_fence_get(f); 658 dma_fence_put(f); 659 660 return 0; 661 662 err_free: 663 amdgpu_job_free(job); 664 err: 665 amdgpu_ib_free(ib_msg, f); 666 return r; 667 } 668 669 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 670 struct amdgpu_ib *ib) 671 { 672 struct amdgpu_device *adev = ring->adev; 673 uint32_t *msg; 674 int r, i; 675 676 memset(ib, 0, sizeof(*ib)); 677 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 678 AMDGPU_IB_POOL_DIRECT, 679 ib); 680 if (r) 681 return r; 682 683 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 684 msg[0] = cpu_to_le32(0x00000028); 685 msg[1] = cpu_to_le32(0x00000038); 686 msg[2] = cpu_to_le32(0x00000001); 687 msg[3] = cpu_to_le32(0x00000000); 688 msg[4] = cpu_to_le32(handle); 689 msg[5] = cpu_to_le32(0x00000000); 690 msg[6] = cpu_to_le32(0x00000001); 691 msg[7] = cpu_to_le32(0x00000028); 692 msg[8] = cpu_to_le32(0x00000010); 693 msg[9] = cpu_to_le32(0x00000000); 694 msg[10] = cpu_to_le32(0x00000007); 695 msg[11] = cpu_to_le32(0x00000000); 696 msg[12] = cpu_to_le32(0x00000780); 697 msg[13] = cpu_to_le32(0x00000440); 698 for (i = 14; i < 1024; ++i) 699 msg[i] = cpu_to_le32(0x0); 700 701 return 0; 702 } 703 704 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 705 struct amdgpu_ib *ib) 706 { 707 struct amdgpu_device *adev = ring->adev; 708 uint32_t *msg; 709 int r, i; 710 711 memset(ib, 0, sizeof(*ib)); 712 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 713 AMDGPU_IB_POOL_DIRECT, 714 ib); 715 if (r) 716 return r; 717 718 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 719 msg[0] = cpu_to_le32(0x00000028); 720 msg[1] = cpu_to_le32(0x00000018); 721 msg[2] = cpu_to_le32(0x00000000); 722 msg[3] = cpu_to_le32(0x00000002); 723 msg[4] = cpu_to_le32(handle); 724 msg[5] = cpu_to_le32(0x00000000); 725 for (i = 6; i < 1024; ++i) 726 msg[i] = cpu_to_le32(0x0); 727 728 return 0; 729 } 730 731 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 732 { 733 struct dma_fence *fence = NULL; 734 struct amdgpu_ib ib; 735 long r; 736 737 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 738 if (r) 739 goto error; 740 741 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 742 if (r) 743 goto error; 744 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 745 if (r) 746 goto error; 747 748 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 749 if (r) 750 goto error; 751 752 r = dma_fence_wait_timeout(fence, false, timeout); 753 if (r == 0) 754 r = -ETIMEDOUT; 755 else if (r > 0) 756 r = 0; 757 758 dma_fence_put(fence); 759 error: 760 return r; 761 } 762 763 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, 764 uint32_t ib_pack_in_dw, bool enc) 765 { 766 uint32_t *ib_checksum; 767 768 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */ 769 ib->ptr[ib->length_dw++] = 0x30000002; 770 ib_checksum = &ib->ptr[ib->length_dw++]; 771 ib->ptr[ib->length_dw++] = ib_pack_in_dw; 772 773 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */ 774 ib->ptr[ib->length_dw++] = 0x30000001; 775 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3; 776 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t); 777 778 return ib_checksum; 779 } 780 781 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum, 782 uint32_t ib_pack_in_dw) 783 { 784 uint32_t i; 785 uint32_t checksum = 0; 786 787 for (i = 0; i < ib_pack_in_dw; i++) 788 checksum += *(*ib_checksum + 2 + i); 789 790 **ib_checksum = checksum; 791 } 792 793 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 794 struct amdgpu_ib *ib_msg, 795 struct dma_fence **fence) 796 { 797 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 798 unsigned int ib_size_dw = 64; 799 struct amdgpu_device *adev = ring->adev; 800 struct dma_fence *f = NULL; 801 struct amdgpu_job *job; 802 struct amdgpu_ib *ib; 803 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 804 uint32_t *ib_checksum; 805 uint32_t ib_pack_in_dw; 806 int i, r; 807 808 if (adev->vcn.inst[ring->me].using_unified_queue) 809 ib_size_dw += 8; 810 811 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 812 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 813 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST, 814 &job); 815 if (r) 816 goto err; 817 818 ib = &job->ibs[0]; 819 ib->length_dw = 0; 820 821 /* single queue headers */ 822 if (adev->vcn.inst[ring->me].using_unified_queue) { 823 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t) 824 + 4 + 2; /* engine info + decoding ib in dw */ 825 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false); 826 } 827 828 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 829 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 830 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 831 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 832 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 833 834 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 835 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 836 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 837 838 for (i = ib->length_dw; i < ib_size_dw; ++i) 839 ib->ptr[i] = 0x0; 840 841 if (adev->vcn.inst[ring->me].using_unified_queue) 842 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw); 843 844 r = amdgpu_job_submit_direct(job, ring, &f); 845 if (r) 846 goto err_free; 847 848 amdgpu_ib_free(ib_msg, f); 849 850 if (fence) 851 *fence = dma_fence_get(f); 852 dma_fence_put(f); 853 854 return 0; 855 856 err_free: 857 amdgpu_job_free(job); 858 err: 859 amdgpu_ib_free(ib_msg, f); 860 return r; 861 } 862 863 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 864 { 865 struct dma_fence *fence = NULL; 866 struct amdgpu_ib ib; 867 long r; 868 869 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 870 if (r) 871 goto error; 872 873 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 874 if (r) 875 goto error; 876 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 877 if (r) 878 goto error; 879 880 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 881 if (r) 882 goto error; 883 884 r = dma_fence_wait_timeout(fence, false, timeout); 885 if (r == 0) 886 r = -ETIMEDOUT; 887 else if (r > 0) 888 r = 0; 889 890 dma_fence_put(fence); 891 error: 892 return r; 893 } 894 895 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 896 { 897 struct amdgpu_device *adev = ring->adev; 898 uint32_t rptr; 899 unsigned int i; 900 int r; 901 902 if (amdgpu_sriov_vf(adev)) 903 return 0; 904 905 r = amdgpu_ring_alloc(ring, 16); 906 if (r) 907 return r; 908 909 rptr = amdgpu_ring_get_rptr(ring); 910 911 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 912 amdgpu_ring_commit(ring); 913 914 for (i = 0; i < adev->usec_timeout; i++) { 915 if (amdgpu_ring_get_rptr(ring) != rptr) 916 break; 917 udelay(1); 918 } 919 920 if (i >= adev->usec_timeout) 921 r = -ETIMEDOUT; 922 923 return r; 924 } 925 926 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 927 struct amdgpu_ib *ib_msg, 928 struct dma_fence **fence) 929 { 930 unsigned int ib_size_dw = 16; 931 struct amdgpu_device *adev = ring->adev; 932 struct amdgpu_job *job; 933 struct amdgpu_ib *ib; 934 struct dma_fence *f = NULL; 935 uint32_t *ib_checksum = NULL; 936 uint64_t addr; 937 int i, r; 938 939 if (adev->vcn.inst[ring->me].using_unified_queue) 940 ib_size_dw += 8; 941 942 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 943 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 944 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST, 945 &job); 946 if (r) 947 return r; 948 949 ib = &job->ibs[0]; 950 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 951 952 ib->length_dw = 0; 953 954 if (adev->vcn.inst[ring->me].using_unified_queue) 955 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 956 957 ib->ptr[ib->length_dw++] = 0x00000018; 958 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 959 ib->ptr[ib->length_dw++] = handle; 960 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 961 ib->ptr[ib->length_dw++] = addr; 962 ib->ptr[ib->length_dw++] = 0x00000000; 963 964 ib->ptr[ib->length_dw++] = 0x00000014; 965 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 966 ib->ptr[ib->length_dw++] = 0x0000001c; 967 ib->ptr[ib->length_dw++] = 0x00000000; 968 ib->ptr[ib->length_dw++] = 0x00000000; 969 970 ib->ptr[ib->length_dw++] = 0x00000008; 971 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 972 973 for (i = ib->length_dw; i < ib_size_dw; ++i) 974 ib->ptr[i] = 0x0; 975 976 if (adev->vcn.inst[ring->me].using_unified_queue) 977 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 978 979 r = amdgpu_job_submit_direct(job, ring, &f); 980 if (r) 981 goto err; 982 983 if (fence) 984 *fence = dma_fence_get(f); 985 dma_fence_put(f); 986 987 return 0; 988 989 err: 990 amdgpu_job_free(job); 991 return r; 992 } 993 994 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 995 struct amdgpu_ib *ib_msg, 996 struct dma_fence **fence) 997 { 998 unsigned int ib_size_dw = 16; 999 struct amdgpu_device *adev = ring->adev; 1000 struct amdgpu_job *job; 1001 struct amdgpu_ib *ib; 1002 struct dma_fence *f = NULL; 1003 uint32_t *ib_checksum = NULL; 1004 uint64_t addr; 1005 int i, r; 1006 1007 if (adev->vcn.inst[ring->me].using_unified_queue) 1008 ib_size_dw += 8; 1009 1010 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 1011 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 1012 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST, 1013 &job); 1014 if (r) 1015 return r; 1016 1017 ib = &job->ibs[0]; 1018 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 1019 1020 ib->length_dw = 0; 1021 1022 if (adev->vcn.inst[ring->me].using_unified_queue) 1023 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 1024 1025 ib->ptr[ib->length_dw++] = 0x00000018; 1026 ib->ptr[ib->length_dw++] = 0x00000001; 1027 ib->ptr[ib->length_dw++] = handle; 1028 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1029 ib->ptr[ib->length_dw++] = addr; 1030 ib->ptr[ib->length_dw++] = 0x00000000; 1031 1032 ib->ptr[ib->length_dw++] = 0x00000014; 1033 ib->ptr[ib->length_dw++] = 0x00000002; 1034 ib->ptr[ib->length_dw++] = 0x0000001c; 1035 ib->ptr[ib->length_dw++] = 0x00000000; 1036 ib->ptr[ib->length_dw++] = 0x00000000; 1037 1038 ib->ptr[ib->length_dw++] = 0x00000008; 1039 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 1040 1041 for (i = ib->length_dw; i < ib_size_dw; ++i) 1042 ib->ptr[i] = 0x0; 1043 1044 if (adev->vcn.inst[ring->me].using_unified_queue) 1045 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 1046 1047 r = amdgpu_job_submit_direct(job, ring, &f); 1048 if (r) 1049 goto err; 1050 1051 if (fence) 1052 *fence = dma_fence_get(f); 1053 dma_fence_put(f); 1054 1055 return 0; 1056 1057 err: 1058 amdgpu_job_free(job); 1059 return r; 1060 } 1061 1062 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1063 { 1064 struct amdgpu_device *adev = ring->adev; 1065 struct dma_fence *fence = NULL; 1066 struct amdgpu_ib ib; 1067 long r; 1068 1069 memset(&ib, 0, sizeof(ib)); 1070 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 1071 AMDGPU_IB_POOL_DIRECT, 1072 &ib); 1073 if (r) 1074 return r; 1075 1076 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 1077 if (r) 1078 goto error; 1079 1080 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 1081 if (r) 1082 goto error; 1083 1084 r = dma_fence_wait_timeout(fence, false, timeout); 1085 if (r == 0) 1086 r = -ETIMEDOUT; 1087 else if (r > 0) 1088 r = 0; 1089 1090 error: 1091 amdgpu_ib_free(&ib, fence); 1092 dma_fence_put(fence); 1093 1094 return r; 1095 } 1096 1097 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1098 { 1099 struct amdgpu_device *adev = ring->adev; 1100 long r; 1101 1102 if ((amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(4, 0, 3)) && 1103 (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(5, 0, 1)) && 1104 (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(5, 0, 2))) { 1105 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout); 1106 if (r) 1107 goto error; 1108 } 1109 1110 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout); 1111 1112 error: 1113 return r; 1114 } 1115 1116 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 1117 { 1118 switch (ring) { 1119 case 0: 1120 return AMDGPU_RING_PRIO_0; 1121 case 1: 1122 return AMDGPU_RING_PRIO_1; 1123 case 2: 1124 return AMDGPU_RING_PRIO_2; 1125 default: 1126 return AMDGPU_RING_PRIO_0; 1127 } 1128 } 1129 1130 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev, int i) 1131 { 1132 unsigned int idx; 1133 1134 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1135 const struct common_firmware_header *hdr; 1136 1137 if (adev->vcn.harvest_config & (1 << i)) 1138 return; 1139 1140 if ((amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 3) || 1141 amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(5, 0, 1) || 1142 amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(5, 0, 2)) 1143 && (i > 0)) 1144 return; 1145 1146 hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data; 1147 /* currently only support 2 FW instances */ 1148 if (i >= 2) { 1149 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 1150 return; 1151 } 1152 idx = AMDGPU_UCODE_ID_VCN + i; 1153 adev->firmware.ucode[idx].ucode_id = idx; 1154 adev->firmware.ucode[idx].fw = adev->vcn.inst[i].fw; 1155 adev->firmware.fw_size += 1156 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 1157 } 1158 } 1159 1160 /* 1161 * debugfs for mapping vcn firmware log buffer. 1162 */ 1163 #if defined(CONFIG_DEBUG_FS) 1164 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf, 1165 size_t size, loff_t *pos) 1166 { 1167 struct amdgpu_vcn_inst *vcn; 1168 void *log_buf; 1169 struct amdgpu_vcn_fwlog *plog; 1170 unsigned int read_pos, write_pos, available, i, read_bytes = 0; 1171 unsigned int read_num[2] = {0}; 1172 1173 vcn = file_inode(f)->i_private; 1174 if (!vcn) 1175 return -ENODEV; 1176 1177 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log) 1178 return -EFAULT; 1179 1180 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1181 1182 plog = (struct amdgpu_vcn_fwlog *)log_buf; 1183 read_pos = plog->rptr; 1184 write_pos = plog->wptr; 1185 1186 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE) 1187 return -EFAULT; 1188 1189 if (!size || (read_pos == write_pos)) 1190 return 0; 1191 1192 if (write_pos > read_pos) { 1193 available = write_pos - read_pos; 1194 read_num[0] = min_t(size_t, size, available); 1195 } else { 1196 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos; 1197 available = read_num[0] + write_pos - plog->header_size; 1198 if (size > available) 1199 read_num[1] = write_pos - plog->header_size; 1200 else if (size > read_num[0]) 1201 read_num[1] = size - read_num[0]; 1202 else 1203 read_num[0] = size; 1204 } 1205 1206 for (i = 0; i < 2; i++) { 1207 if (read_num[i]) { 1208 if (read_pos == AMDGPU_VCNFW_LOG_SIZE) 1209 read_pos = plog->header_size; 1210 if (read_num[i] == copy_to_user((buf + read_bytes), 1211 (log_buf + read_pos), read_num[i])) 1212 return -EFAULT; 1213 1214 read_bytes += read_num[i]; 1215 read_pos += read_num[i]; 1216 } 1217 } 1218 1219 plog->rptr = read_pos; 1220 *pos += read_bytes; 1221 return read_bytes; 1222 } 1223 1224 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = { 1225 .owner = THIS_MODULE, 1226 .read = amdgpu_debugfs_vcn_fwlog_read, 1227 .llseek = default_llseek 1228 }; 1229 #endif 1230 1231 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i, 1232 struct amdgpu_vcn_inst *vcn) 1233 { 1234 #if defined(CONFIG_DEBUG_FS) 1235 struct drm_minor *minor = adev_to_drm(adev)->primary; 1236 struct dentry *root = minor->debugfs_root; 1237 char name[32]; 1238 1239 sprintf(name, "amdgpu_vcn_%d_fwlog", i); 1240 debugfs_create_file_size(name, S_IFREG | 0444, root, vcn, 1241 &amdgpu_debugfs_vcnfwlog_fops, 1242 AMDGPU_VCNFW_LOG_SIZE); 1243 #endif 1244 } 1245 1246 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn) 1247 { 1248 #if defined(CONFIG_DEBUG_FS) 1249 uint32_t *flag = vcn->fw_shared.cpu_addr; 1250 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1251 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size; 1252 struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr; 1253 struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr 1254 + vcn->fw_shared.log_offset; 1255 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG); 1256 fw_log->is_enabled = 1; 1257 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF); 1258 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32); 1259 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE); 1260 1261 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog); 1262 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE; 1263 log_buf->rptr = log_buf->header_size; 1264 log_buf->wptr = log_buf->header_size; 1265 log_buf->wrapped = 0; 1266 #endif 1267 } 1268 1269 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, 1270 struct amdgpu_irq_src *source, 1271 struct amdgpu_iv_entry *entry) 1272 { 1273 struct ras_common_if *ras_if = adev->vcn.ras_if; 1274 struct ras_dispatch_if ih_data = { 1275 .entry = entry, 1276 }; 1277 1278 if (!ras_if) 1279 return 0; 1280 1281 if (!amdgpu_sriov_vf(adev)) { 1282 ih_data.head = *ras_if; 1283 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 1284 } else { 1285 if (adev->virt.ops && adev->virt.ops->ras_poison_handler) 1286 adev->virt.ops->ras_poison_handler(adev, ras_if->block); 1287 else 1288 dev_warn(adev->dev, 1289 "No ras_poison_handler interface in SRIOV for VCN!\n"); 1290 } 1291 1292 return 0; 1293 } 1294 1295 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1296 { 1297 int r, i; 1298 1299 r = amdgpu_ras_block_late_init(adev, ras_block); 1300 if (r) 1301 return r; 1302 1303 if (amdgpu_ras_is_supported(adev, ras_block->block)) { 1304 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1305 if (adev->vcn.harvest_config & (1 << i) || 1306 !adev->vcn.inst[i].ras_poison_irq.funcs) 1307 continue; 1308 1309 r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0); 1310 if (r) 1311 goto late_fini; 1312 } 1313 } 1314 return 0; 1315 1316 late_fini: 1317 amdgpu_ras_block_late_fini(adev, ras_block); 1318 return r; 1319 } 1320 1321 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev) 1322 { 1323 int err; 1324 struct amdgpu_vcn_ras *ras; 1325 1326 if (!adev->vcn.ras) 1327 return 0; 1328 1329 ras = adev->vcn.ras; 1330 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 1331 if (err) { 1332 dev_err(adev->dev, "Failed to register vcn ras block!\n"); 1333 return err; 1334 } 1335 1336 strcpy(ras->ras_block.ras_comm.name, "vcn"); 1337 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; 1338 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; 1339 adev->vcn.ras_if = &ras->ras_block.ras_comm; 1340 1341 if (!ras->ras_block.ras_late_init) 1342 ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init; 1343 1344 return 0; 1345 } 1346 1347 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, 1348 enum AMDGPU_UCODE_ID ucode_id) 1349 { 1350 struct amdgpu_firmware_info ucode = { 1351 .ucode_id = (ucode_id ? ucode_id : 1352 (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 1353 AMDGPU_UCODE_ID_VCN0_RAM)), 1354 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1355 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1356 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr), 1357 }; 1358 1359 return psp_execute_ip_fw_load(&adev->psp, &ucode); 1360 } 1361 1362 static ssize_t amdgpu_get_vcn_reset_mask(struct device *dev, 1363 struct device_attribute *attr, 1364 char *buf) 1365 { 1366 struct drm_device *ddev = dev_get_drvdata(dev); 1367 struct amdgpu_device *adev = drm_to_adev(ddev); 1368 1369 if (!adev) 1370 return -ENODEV; 1371 1372 return amdgpu_show_reset_mask(buf, adev->vcn.supported_reset); 1373 } 1374 1375 static DEVICE_ATTR(vcn_reset_mask, 0444, 1376 amdgpu_get_vcn_reset_mask, NULL); 1377 1378 int amdgpu_vcn_sysfs_reset_mask_init(struct amdgpu_device *adev) 1379 { 1380 int r = 0; 1381 1382 if (adev->vcn.num_vcn_inst) { 1383 r = device_create_file(adev->dev, &dev_attr_vcn_reset_mask); 1384 if (r) 1385 return r; 1386 } 1387 1388 return r; 1389 } 1390 1391 void amdgpu_vcn_sysfs_reset_mask_fini(struct amdgpu_device *adev) 1392 { 1393 if (adev->dev->kobj.sd) { 1394 if (adev->vcn.num_vcn_inst) 1395 device_remove_file(adev->dev, &dev_attr_vcn_reset_mask); 1396 } 1397 } 1398 1399 /* 1400 * debugfs to enable/disable vcn job submission to specific core or 1401 * instance. It is created only if the queue type is unified. 1402 */ 1403 #if defined(CONFIG_DEBUG_FS) 1404 static int amdgpu_debugfs_vcn_sched_mask_set(void *data, u64 val) 1405 { 1406 struct amdgpu_device *adev = (struct amdgpu_device *)data; 1407 u32 i; 1408 u64 mask; 1409 struct amdgpu_ring *ring; 1410 1411 if (!adev) 1412 return -ENODEV; 1413 1414 mask = (1ULL << adev->vcn.num_vcn_inst) - 1; 1415 if ((val & mask) == 0) 1416 return -EINVAL; 1417 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1418 ring = &adev->vcn.inst[i].ring_enc[0]; 1419 if (val & (1ULL << i)) 1420 ring->sched.ready = true; 1421 else 1422 ring->sched.ready = false; 1423 } 1424 /* publish sched.ready flag update effective immediately across smp */ 1425 smp_rmb(); 1426 return 0; 1427 } 1428 1429 static int amdgpu_debugfs_vcn_sched_mask_get(void *data, u64 *val) 1430 { 1431 struct amdgpu_device *adev = (struct amdgpu_device *)data; 1432 u32 i; 1433 u64 mask = 0; 1434 struct amdgpu_ring *ring; 1435 1436 if (!adev) 1437 return -ENODEV; 1438 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1439 ring = &adev->vcn.inst[i].ring_enc[0]; 1440 if (ring->sched.ready) 1441 mask |= 1ULL << i; 1442 } 1443 *val = mask; 1444 return 0; 1445 } 1446 1447 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_vcn_sched_mask_fops, 1448 amdgpu_debugfs_vcn_sched_mask_get, 1449 amdgpu_debugfs_vcn_sched_mask_set, "%llx\n"); 1450 #endif 1451 1452 void amdgpu_debugfs_vcn_sched_mask_init(struct amdgpu_device *adev) 1453 { 1454 #if defined(CONFIG_DEBUG_FS) 1455 struct drm_minor *minor = adev_to_drm(adev)->primary; 1456 struct dentry *root = minor->debugfs_root; 1457 char name[32]; 1458 1459 if (adev->vcn.num_vcn_inst <= 1 || !adev->vcn.inst[0].using_unified_queue) 1460 return; 1461 sprintf(name, "amdgpu_vcn_sched_mask"); 1462 debugfs_create_file(name, 0600, root, adev, 1463 &amdgpu_debugfs_vcn_sched_mask_fops); 1464 #endif 1465 } 1466 1467 /** 1468 * vcn_set_powergating_state - set VCN block powergating state 1469 * 1470 * @ip_block: amdgpu_ip_block pointer 1471 * @state: power gating state 1472 * 1473 * Set VCN block powergating state 1474 */ 1475 int vcn_set_powergating_state(struct amdgpu_ip_block *ip_block, 1476 enum amd_powergating_state state) 1477 { 1478 struct amdgpu_device *adev = ip_block->adev; 1479 int ret = 0, i; 1480 1481 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1482 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1483 1484 ret |= vinst->set_pg_state(vinst, state); 1485 } 1486 1487 return ret; 1488 } 1489 1490 static struct amdgpu_fence * 1491 amdgpu_vcn_ring_reset_begin_helper(struct amdgpu_ring *ring, 1492 struct amdgpu_ring *guilty_ring, 1493 struct amdgpu_fence *timedout_fence) 1494 { 1495 struct amdgpu_fence *fence; 1496 1497 drm_sched_wqueue_stop(&ring->sched); 1498 if (ring == guilty_ring) 1499 fence = timedout_fence; 1500 else 1501 fence = amdgpu_ring_find_guilty_fence(ring); 1502 amdgpu_ring_reset_helper_begin(ring, fence); 1503 1504 return fence; 1505 } 1506 1507 static int 1508 amdgpu_vcn_ring_reset_end_helper(struct amdgpu_ring *ring, 1509 struct amdgpu_fence *fence) 1510 { 1511 int r; 1512 1513 r = amdgpu_ring_reset_helper_end(ring, fence); 1514 if (r) 1515 return r; 1516 1517 drm_sched_wqueue_start(&ring->sched); 1518 return 0; 1519 } 1520 1521 /** 1522 * amdgpu_vcn_ring_reset - Reset a VCN ring 1523 * @ring: ring to reset 1524 * @vmid: vmid of guilty job 1525 * @timedout_fence: fence of timed out job 1526 * 1527 * This helper is for VCN blocks without unified queues because 1528 * resetting the engine resets all queues in that case. With 1529 * unified queues we have one queue per engine. 1530 * Returns: 0 on success, or a negative error code on failure. 1531 */ 1532 int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring, 1533 unsigned int vmid, 1534 struct amdgpu_fence *timedout_fence) 1535 { 1536 struct amdgpu_device *adev = ring->adev; 1537 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1538 struct amdgpu_fence *dec_fence; 1539 struct amdgpu_fence *enc_fence[AMDGPU_VCN_MAX_ENC_RINGS]; 1540 int r, i; 1541 1542 if (adev->vcn.inst[ring->me].using_unified_queue) 1543 return -EINVAL; 1544 1545 mutex_lock(&vinst->engine_reset_mutex); 1546 dec_fence = amdgpu_vcn_ring_reset_begin_helper(&vinst->ring_dec, ring, 1547 timedout_fence); 1548 for (i = 0; i < vinst->num_enc_rings; i++) 1549 enc_fence[i] = amdgpu_vcn_ring_reset_begin_helper(&vinst->ring_enc[i], ring, 1550 timedout_fence); 1551 1552 /* Perform the VCN reset for the specified instance */ 1553 r = vinst->reset(vinst); 1554 if (r) 1555 goto unlock; 1556 1557 r = amdgpu_vcn_ring_reset_end_helper(&vinst->ring_dec, dec_fence); 1558 if (r) 1559 goto unlock; 1560 for (i = 0; i < vinst->num_enc_rings; i++) { 1561 r = amdgpu_vcn_ring_reset_end_helper(&vinst->ring_enc[i], enc_fence[i]); 1562 if (r) 1563 goto unlock; 1564 } 1565 unlock: 1566 mutex_unlock(&vinst->engine_reset_mutex); 1567 1568 return r; 1569 } 1570 1571 int amdgpu_vcn_reg_dump_init(struct amdgpu_device *adev, 1572 const struct amdgpu_hwip_reg_entry *reg, u32 count) 1573 { 1574 adev->vcn.ip_dump = kcalloc(adev->vcn.num_vcn_inst * count, 1575 sizeof(uint32_t), GFP_KERNEL); 1576 if (!adev->vcn.ip_dump) 1577 return -ENOMEM; 1578 adev->vcn.reg_list = reg; 1579 adev->vcn.reg_count = count; 1580 1581 return 0; 1582 } 1583 1584 static void amdgpu_vcn_reg_dump_fini(struct amdgpu_device *adev) 1585 { 1586 kfree(adev->vcn.ip_dump); 1587 adev->vcn.ip_dump = NULL; 1588 adev->vcn.reg_list = NULL; 1589 adev->vcn.reg_count = 0; 1590 } 1591 1592 void amdgpu_vcn_dump_ip_state(struct amdgpu_ip_block *ip_block) 1593 { 1594 struct amdgpu_device *adev = ip_block->adev; 1595 int i, j; 1596 bool is_powered; 1597 u32 inst_off; 1598 1599 if (!adev->vcn.ip_dump) 1600 return; 1601 1602 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1603 if (adev->vcn.harvest_config & (1 << i)) 1604 continue; 1605 1606 inst_off = i * adev->vcn.reg_count; 1607 /* mmUVD_POWER_STATUS is always readable and is the first in reg_list */ 1608 adev->vcn.ip_dump[inst_off] = 1609 RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->vcn.reg_list[0], i)); 1610 is_powered = (adev->vcn.ip_dump[inst_off] & 1611 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF) != 1612 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 1613 1614 if (is_powered) 1615 for (j = 1; j < adev->vcn.reg_count; j++) 1616 adev->vcn.ip_dump[inst_off + j] = 1617 RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->vcn.reg_list[j], i)); 1618 } 1619 } 1620 1621 void amdgpu_vcn_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1622 { 1623 struct amdgpu_device *adev = ip_block->adev; 1624 int i, j; 1625 bool is_powered; 1626 u32 inst_off; 1627 1628 if (!adev->vcn.ip_dump) 1629 return; 1630 1631 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 1632 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1633 if (adev->vcn.harvest_config & (1 << i)) { 1634 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 1635 continue; 1636 } 1637 1638 inst_off = i * adev->vcn.reg_count; 1639 is_powered = (adev->vcn.ip_dump[inst_off] & 1640 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF) != 1641 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 1642 1643 if (is_powered) { 1644 drm_printf(p, "\nActive Instance:VCN%d\n", i); 1645 for (j = 0; j < adev->vcn.reg_count; j++) 1646 drm_printf(p, "%-50s \t 0x%08x\n", adev->vcn.reg_list[j].reg_name, 1647 adev->vcn.ip_dump[inst_off + j]); 1648 } else { 1649 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 1650 } 1651 } 1652 } 1653