1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/dmi.h> 30 #include <linux/pci.h> 31 #include <linux/debugfs.h> 32 #include <drm/drm_drv.h> 33 34 #include "amdgpu.h" 35 #include "amdgpu_pm.h" 36 #include "amdgpu_vcn.h" 37 #include "soc15d.h" 38 39 /* Firmware Names */ 40 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 41 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 42 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 43 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 44 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 45 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 46 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 47 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 48 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 49 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 50 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 51 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 52 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 53 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 54 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 55 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 56 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin" 57 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin" 58 #define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin" 59 #define FIRMWARE_VCN4_0_3 "amdgpu/vcn_4_0_3.bin" 60 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin" 61 #define FIRMWARE_VCN4_0_5 "amdgpu/vcn_4_0_5.bin" 62 #define FIRMWARE_VCN4_0_6 "amdgpu/vcn_4_0_6.bin" 63 #define FIRMWARE_VCN4_0_6_1 "amdgpu/vcn_4_0_6_1.bin" 64 #define FIRMWARE_VCN5_0_0 "amdgpu/vcn_5_0_0.bin" 65 66 MODULE_FIRMWARE(FIRMWARE_RAVEN); 67 MODULE_FIRMWARE(FIRMWARE_PICASSO); 68 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 69 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 70 MODULE_FIRMWARE(FIRMWARE_RENOIR); 71 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 72 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 73 MODULE_FIRMWARE(FIRMWARE_NAVI10); 74 MODULE_FIRMWARE(FIRMWARE_NAVI14); 75 MODULE_FIRMWARE(FIRMWARE_NAVI12); 76 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 77 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 78 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 79 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 80 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 81 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 82 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2); 83 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0); 84 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2); 85 MODULE_FIRMWARE(FIRMWARE_VCN4_0_3); 86 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4); 87 MODULE_FIRMWARE(FIRMWARE_VCN4_0_5); 88 MODULE_FIRMWARE(FIRMWARE_VCN4_0_6); 89 MODULE_FIRMWARE(FIRMWARE_VCN4_0_6_1); 90 MODULE_FIRMWARE(FIRMWARE_VCN5_0_0); 91 92 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 93 94 int amdgpu_vcn_early_init(struct amdgpu_device *adev) 95 { 96 char ucode_prefix[25]; 97 int r, i; 98 99 amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix)); 100 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 101 if (i == 1 && amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6)) 102 r = amdgpu_ucode_request(adev, &adev->vcn.fw[i], "amdgpu/%s_%d.bin", ucode_prefix, i); 103 else 104 r = amdgpu_ucode_request(adev, &adev->vcn.fw[i], "amdgpu/%s.bin", ucode_prefix); 105 if (r) { 106 amdgpu_ucode_release(&adev->vcn.fw[i]); 107 return r; 108 } 109 } 110 return r; 111 } 112 113 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 114 { 115 unsigned long bo_size; 116 const struct common_firmware_header *hdr; 117 unsigned char fw_check; 118 unsigned int fw_shared_size, log_offset; 119 int i, r; 120 121 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 122 mutex_init(&adev->vcn.vcn_pg_lock); 123 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 124 atomic_set(&adev->vcn.total_submission_cnt, 0); 125 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 126 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 127 128 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 129 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 130 adev->vcn.indirect_sram = true; 131 132 /* 133 * Some Steam Deck's BIOS versions are incompatible with the 134 * indirect SRAM mode, leading to amdgpu being unable to get 135 * properly probed (and even potentially crashing the kernel). 136 * Hence, check for these versions here - notice this is 137 * restricted to Vangogh (Deck's APU). 138 */ 139 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 0, 2)) { 140 const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION); 141 142 if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) || 143 !strncmp("F7A0114", bios_ver, 7))) { 144 adev->vcn.indirect_sram = false; 145 dev_info(adev->dev, 146 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver); 147 } 148 } 149 150 hdr = (const struct common_firmware_header *)adev->vcn.fw[0]->data; 151 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 152 153 /* Bit 20-23, it is encode major and non-zero for new naming convention. 154 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 155 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 156 * is zero in old naming convention, this field is always zero so far. 157 * These four bits are used to tell which naming convention is present. 158 */ 159 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 160 if (fw_check) { 161 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 162 163 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 164 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 165 enc_major = fw_check; 166 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 167 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 168 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 169 enc_major, enc_minor, dec_ver, vep, fw_rev); 170 } else { 171 unsigned int version_major, version_minor, family_id; 172 173 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 174 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 175 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 176 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 177 version_major, version_minor, family_id); 178 } 179 180 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 181 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 182 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 183 184 if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(5, 0, 0)) { 185 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)); 186 log_offset = offsetof(struct amdgpu_vcn5_fw_shared, fw_log); 187 } else if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) { 188 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); 189 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log); 190 } else { 191 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 192 log_offset = offsetof(struct amdgpu_fw_shared, fw_log); 193 } 194 195 bo_size += fw_shared_size; 196 197 if (amdgpu_vcnfw_log) 198 bo_size += AMDGPU_VCNFW_LOG_SIZE; 199 200 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 201 if (adev->vcn.harvest_config & (1 << i)) 202 continue; 203 204 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 205 AMDGPU_GEM_DOMAIN_VRAM | 206 AMDGPU_GEM_DOMAIN_GTT, 207 &adev->vcn.inst[i].vcpu_bo, 208 &adev->vcn.inst[i].gpu_addr, 209 &adev->vcn.inst[i].cpu_addr); 210 if (r) { 211 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 212 return r; 213 } 214 215 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr + 216 bo_size - fw_shared_size; 217 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr + 218 bo_size - fw_shared_size; 219 220 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size; 221 222 if (amdgpu_vcnfw_log) { 223 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 224 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 225 adev->vcn.inst[i].fw_shared.log_offset = log_offset; 226 } 227 228 if (adev->vcn.indirect_sram) { 229 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 230 AMDGPU_GEM_DOMAIN_VRAM | 231 AMDGPU_GEM_DOMAIN_GTT, 232 &adev->vcn.inst[i].dpg_sram_bo, 233 &adev->vcn.inst[i].dpg_sram_gpu_addr, 234 &adev->vcn.inst[i].dpg_sram_cpu_addr); 235 if (r) { 236 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 237 return r; 238 } 239 } 240 } 241 242 return 0; 243 } 244 245 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 246 { 247 int i, j; 248 249 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 250 if (adev->vcn.harvest_config & (1 << j)) 251 continue; 252 253 amdgpu_bo_free_kernel( 254 &adev->vcn.inst[j].dpg_sram_bo, 255 &adev->vcn.inst[j].dpg_sram_gpu_addr, 256 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 257 258 kvfree(adev->vcn.inst[j].saved_bo); 259 260 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 261 &adev->vcn.inst[j].gpu_addr, 262 (void **)&adev->vcn.inst[j].cpu_addr); 263 264 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 265 266 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 267 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 268 269 amdgpu_ucode_release(&adev->vcn.fw[j]); 270 } 271 272 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 273 mutex_destroy(&adev->vcn.vcn_pg_lock); 274 275 return 0; 276 } 277 278 /* from vcn4 and above, only unified queue is used */ 279 static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring) 280 { 281 struct amdgpu_device *adev = ring->adev; 282 bool ret = false; 283 284 if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) 285 ret = true; 286 287 return ret; 288 } 289 290 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 291 { 292 bool ret = false; 293 int vcn_config = adev->vcn.vcn_config[vcn_instance]; 294 295 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) 296 ret = true; 297 else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) 298 ret = true; 299 else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) 300 ret = true; 301 302 return ret; 303 } 304 305 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 306 { 307 unsigned int size; 308 void *ptr; 309 int i, idx; 310 311 bool in_ras_intr = amdgpu_ras_intr_triggered(); 312 313 cancel_delayed_work_sync(&adev->vcn.idle_work); 314 315 /* err_event_athub will corrupt VCPU buffer, so we need to 316 * restore fw data and clear buffer in amdgpu_vcn_resume() */ 317 if (in_ras_intr) 318 return 0; 319 320 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 321 if (adev->vcn.harvest_config & (1 << i)) 322 continue; 323 if (adev->vcn.inst[i].vcpu_bo == NULL) 324 return 0; 325 326 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 327 ptr = adev->vcn.inst[i].cpu_addr; 328 329 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 330 if (!adev->vcn.inst[i].saved_bo) 331 return -ENOMEM; 332 333 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 334 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 335 drm_dev_exit(idx); 336 } 337 } 338 return 0; 339 } 340 341 int amdgpu_vcn_resume(struct amdgpu_device *adev) 342 { 343 unsigned int size; 344 void *ptr; 345 int i, idx; 346 347 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 348 if (adev->vcn.harvest_config & (1 << i)) 349 continue; 350 if (adev->vcn.inst[i].vcpu_bo == NULL) 351 return -EINVAL; 352 353 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 354 ptr = adev->vcn.inst[i].cpu_addr; 355 356 if (adev->vcn.inst[i].saved_bo != NULL) { 357 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 358 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 359 drm_dev_exit(idx); 360 } 361 kvfree(adev->vcn.inst[i].saved_bo); 362 adev->vcn.inst[i].saved_bo = NULL; 363 } else { 364 const struct common_firmware_header *hdr; 365 unsigned int offset; 366 367 hdr = (const struct common_firmware_header *)adev->vcn.fw[i]->data; 368 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 369 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 370 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 371 memcpy_toio(adev->vcn.inst[i].cpu_addr, 372 adev->vcn.fw[i]->data + offset, 373 le32_to_cpu(hdr->ucode_size_bytes)); 374 drm_dev_exit(idx); 375 } 376 size -= le32_to_cpu(hdr->ucode_size_bytes); 377 ptr += le32_to_cpu(hdr->ucode_size_bytes); 378 } 379 memset_io(ptr, 0, size); 380 } 381 } 382 return 0; 383 } 384 385 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 386 { 387 struct amdgpu_device *adev = 388 container_of(work, struct amdgpu_device, vcn.idle_work.work); 389 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 390 unsigned int i, j; 391 int r = 0; 392 393 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 394 if (adev->vcn.harvest_config & (1 << j)) 395 continue; 396 397 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 398 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 399 400 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 401 struct dpg_pause_state new_state; 402 403 if (fence[j] || 404 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 405 new_state.fw_based = VCN_DPG_STATE__PAUSE; 406 else 407 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 408 409 adev->vcn.pause_dpg_mode(adev, j, &new_state); 410 } 411 412 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 413 fences += fence[j]; 414 } 415 416 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 417 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 418 AMD_PG_STATE_GATE); 419 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 420 false); 421 if (r) 422 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 423 } else { 424 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 425 } 426 } 427 428 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 429 { 430 struct amdgpu_device *adev = ring->adev; 431 int r = 0; 432 433 atomic_inc(&adev->vcn.total_submission_cnt); 434 435 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 436 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 437 true); 438 if (r) 439 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 440 } 441 442 mutex_lock(&adev->vcn.vcn_pg_lock); 443 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 444 AMD_PG_STATE_UNGATE); 445 446 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 447 struct dpg_pause_state new_state; 448 449 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 450 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 451 new_state.fw_based = VCN_DPG_STATE__PAUSE; 452 } else { 453 unsigned int fences = 0; 454 unsigned int i; 455 456 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 457 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 458 459 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 460 new_state.fw_based = VCN_DPG_STATE__PAUSE; 461 else 462 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 463 } 464 465 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 466 } 467 mutex_unlock(&adev->vcn.vcn_pg_lock); 468 } 469 470 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 471 { 472 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 473 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 474 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 475 476 atomic_dec(&ring->adev->vcn.total_submission_cnt); 477 478 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 479 } 480 481 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 482 { 483 struct amdgpu_device *adev = ring->adev; 484 uint32_t tmp = 0; 485 unsigned int i; 486 int r; 487 488 /* VCN in SRIOV does not support direct register read/write */ 489 if (amdgpu_sriov_vf(adev)) 490 return 0; 491 492 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 493 r = amdgpu_ring_alloc(ring, 3); 494 if (r) 495 return r; 496 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 497 amdgpu_ring_write(ring, 0xDEADBEEF); 498 amdgpu_ring_commit(ring); 499 for (i = 0; i < adev->usec_timeout; i++) { 500 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 501 if (tmp == 0xDEADBEEF) 502 break; 503 udelay(1); 504 } 505 506 if (i >= adev->usec_timeout) 507 r = -ETIMEDOUT; 508 509 return r; 510 } 511 512 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 513 { 514 struct amdgpu_device *adev = ring->adev; 515 uint32_t rptr; 516 unsigned int i; 517 int r; 518 519 if (amdgpu_sriov_vf(adev)) 520 return 0; 521 522 r = amdgpu_ring_alloc(ring, 16); 523 if (r) 524 return r; 525 526 rptr = amdgpu_ring_get_rptr(ring); 527 528 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 529 amdgpu_ring_commit(ring); 530 531 for (i = 0; i < adev->usec_timeout; i++) { 532 if (amdgpu_ring_get_rptr(ring) != rptr) 533 break; 534 udelay(1); 535 } 536 537 if (i >= adev->usec_timeout) 538 r = -ETIMEDOUT; 539 540 return r; 541 } 542 543 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 544 struct amdgpu_ib *ib_msg, 545 struct dma_fence **fence) 546 { 547 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 548 struct amdgpu_device *adev = ring->adev; 549 struct dma_fence *f = NULL; 550 struct amdgpu_job *job; 551 struct amdgpu_ib *ib; 552 int i, r; 553 554 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 555 64, AMDGPU_IB_POOL_DIRECT, 556 &job); 557 if (r) 558 goto err; 559 560 ib = &job->ibs[0]; 561 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 562 ib->ptr[1] = addr; 563 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 564 ib->ptr[3] = addr >> 32; 565 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 566 ib->ptr[5] = 0; 567 for (i = 6; i < 16; i += 2) { 568 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 569 ib->ptr[i+1] = 0; 570 } 571 ib->length_dw = 16; 572 573 r = amdgpu_job_submit_direct(job, ring, &f); 574 if (r) 575 goto err_free; 576 577 amdgpu_ib_free(adev, ib_msg, f); 578 579 if (fence) 580 *fence = dma_fence_get(f); 581 dma_fence_put(f); 582 583 return 0; 584 585 err_free: 586 amdgpu_job_free(job); 587 err: 588 amdgpu_ib_free(adev, ib_msg, f); 589 return r; 590 } 591 592 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 593 struct amdgpu_ib *ib) 594 { 595 struct amdgpu_device *adev = ring->adev; 596 uint32_t *msg; 597 int r, i; 598 599 memset(ib, 0, sizeof(*ib)); 600 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 601 AMDGPU_IB_POOL_DIRECT, 602 ib); 603 if (r) 604 return r; 605 606 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 607 msg[0] = cpu_to_le32(0x00000028); 608 msg[1] = cpu_to_le32(0x00000038); 609 msg[2] = cpu_to_le32(0x00000001); 610 msg[3] = cpu_to_le32(0x00000000); 611 msg[4] = cpu_to_le32(handle); 612 msg[5] = cpu_to_le32(0x00000000); 613 msg[6] = cpu_to_le32(0x00000001); 614 msg[7] = cpu_to_le32(0x00000028); 615 msg[8] = cpu_to_le32(0x00000010); 616 msg[9] = cpu_to_le32(0x00000000); 617 msg[10] = cpu_to_le32(0x00000007); 618 msg[11] = cpu_to_le32(0x00000000); 619 msg[12] = cpu_to_le32(0x00000780); 620 msg[13] = cpu_to_le32(0x00000440); 621 for (i = 14; i < 1024; ++i) 622 msg[i] = cpu_to_le32(0x0); 623 624 return 0; 625 } 626 627 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 628 struct amdgpu_ib *ib) 629 { 630 struct amdgpu_device *adev = ring->adev; 631 uint32_t *msg; 632 int r, i; 633 634 memset(ib, 0, sizeof(*ib)); 635 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 636 AMDGPU_IB_POOL_DIRECT, 637 ib); 638 if (r) 639 return r; 640 641 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 642 msg[0] = cpu_to_le32(0x00000028); 643 msg[1] = cpu_to_le32(0x00000018); 644 msg[2] = cpu_to_le32(0x00000000); 645 msg[3] = cpu_to_le32(0x00000002); 646 msg[4] = cpu_to_le32(handle); 647 msg[5] = cpu_to_le32(0x00000000); 648 for (i = 6; i < 1024; ++i) 649 msg[i] = cpu_to_le32(0x0); 650 651 return 0; 652 } 653 654 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 655 { 656 struct dma_fence *fence = NULL; 657 struct amdgpu_ib ib; 658 long r; 659 660 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 661 if (r) 662 goto error; 663 664 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 665 if (r) 666 goto error; 667 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 668 if (r) 669 goto error; 670 671 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 672 if (r) 673 goto error; 674 675 r = dma_fence_wait_timeout(fence, false, timeout); 676 if (r == 0) 677 r = -ETIMEDOUT; 678 else if (r > 0) 679 r = 0; 680 681 dma_fence_put(fence); 682 error: 683 return r; 684 } 685 686 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, 687 uint32_t ib_pack_in_dw, bool enc) 688 { 689 uint32_t *ib_checksum; 690 691 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */ 692 ib->ptr[ib->length_dw++] = 0x30000002; 693 ib_checksum = &ib->ptr[ib->length_dw++]; 694 ib->ptr[ib->length_dw++] = ib_pack_in_dw; 695 696 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */ 697 ib->ptr[ib->length_dw++] = 0x30000001; 698 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3; 699 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t); 700 701 return ib_checksum; 702 } 703 704 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum, 705 uint32_t ib_pack_in_dw) 706 { 707 uint32_t i; 708 uint32_t checksum = 0; 709 710 for (i = 0; i < ib_pack_in_dw; i++) 711 checksum += *(*ib_checksum + 2 + i); 712 713 **ib_checksum = checksum; 714 } 715 716 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 717 struct amdgpu_ib *ib_msg, 718 struct dma_fence **fence) 719 { 720 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 721 unsigned int ib_size_dw = 64; 722 struct amdgpu_device *adev = ring->adev; 723 struct dma_fence *f = NULL; 724 struct amdgpu_job *job; 725 struct amdgpu_ib *ib; 726 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 727 bool sq = amdgpu_vcn_using_unified_queue(ring); 728 uint32_t *ib_checksum; 729 uint32_t ib_pack_in_dw; 730 int i, r; 731 732 if (sq) 733 ib_size_dw += 8; 734 735 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 736 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 737 &job); 738 if (r) 739 goto err; 740 741 ib = &job->ibs[0]; 742 ib->length_dw = 0; 743 744 /* single queue headers */ 745 if (sq) { 746 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t) 747 + 4 + 2; /* engine info + decoding ib in dw */ 748 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false); 749 } 750 751 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 752 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 753 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 754 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 755 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 756 757 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 758 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 759 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 760 761 for (i = ib->length_dw; i < ib_size_dw; ++i) 762 ib->ptr[i] = 0x0; 763 764 if (sq) 765 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw); 766 767 r = amdgpu_job_submit_direct(job, ring, &f); 768 if (r) 769 goto err_free; 770 771 amdgpu_ib_free(adev, ib_msg, f); 772 773 if (fence) 774 *fence = dma_fence_get(f); 775 dma_fence_put(f); 776 777 return 0; 778 779 err_free: 780 amdgpu_job_free(job); 781 err: 782 amdgpu_ib_free(adev, ib_msg, f); 783 return r; 784 } 785 786 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 787 { 788 struct dma_fence *fence = NULL; 789 struct amdgpu_ib ib; 790 long r; 791 792 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 793 if (r) 794 goto error; 795 796 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 797 if (r) 798 goto error; 799 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 800 if (r) 801 goto error; 802 803 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 804 if (r) 805 goto error; 806 807 r = dma_fence_wait_timeout(fence, false, timeout); 808 if (r == 0) 809 r = -ETIMEDOUT; 810 else if (r > 0) 811 r = 0; 812 813 dma_fence_put(fence); 814 error: 815 return r; 816 } 817 818 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 819 { 820 struct amdgpu_device *adev = ring->adev; 821 uint32_t rptr; 822 unsigned int i; 823 int r; 824 825 if (amdgpu_sriov_vf(adev)) 826 return 0; 827 828 r = amdgpu_ring_alloc(ring, 16); 829 if (r) 830 return r; 831 832 rptr = amdgpu_ring_get_rptr(ring); 833 834 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 835 amdgpu_ring_commit(ring); 836 837 for (i = 0; i < adev->usec_timeout; i++) { 838 if (amdgpu_ring_get_rptr(ring) != rptr) 839 break; 840 udelay(1); 841 } 842 843 if (i >= adev->usec_timeout) 844 r = -ETIMEDOUT; 845 846 return r; 847 } 848 849 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 850 struct amdgpu_ib *ib_msg, 851 struct dma_fence **fence) 852 { 853 unsigned int ib_size_dw = 16; 854 struct amdgpu_job *job; 855 struct amdgpu_ib *ib; 856 struct dma_fence *f = NULL; 857 uint32_t *ib_checksum = NULL; 858 uint64_t addr; 859 bool sq = amdgpu_vcn_using_unified_queue(ring); 860 int i, r; 861 862 if (sq) 863 ib_size_dw += 8; 864 865 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 866 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 867 &job); 868 if (r) 869 return r; 870 871 ib = &job->ibs[0]; 872 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 873 874 ib->length_dw = 0; 875 876 if (sq) 877 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 878 879 ib->ptr[ib->length_dw++] = 0x00000018; 880 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 881 ib->ptr[ib->length_dw++] = handle; 882 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 883 ib->ptr[ib->length_dw++] = addr; 884 ib->ptr[ib->length_dw++] = 0x00000000; 885 886 ib->ptr[ib->length_dw++] = 0x00000014; 887 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 888 ib->ptr[ib->length_dw++] = 0x0000001c; 889 ib->ptr[ib->length_dw++] = 0x00000000; 890 ib->ptr[ib->length_dw++] = 0x00000000; 891 892 ib->ptr[ib->length_dw++] = 0x00000008; 893 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 894 895 for (i = ib->length_dw; i < ib_size_dw; ++i) 896 ib->ptr[i] = 0x0; 897 898 if (sq) 899 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 900 901 r = amdgpu_job_submit_direct(job, ring, &f); 902 if (r) 903 goto err; 904 905 if (fence) 906 *fence = dma_fence_get(f); 907 dma_fence_put(f); 908 909 return 0; 910 911 err: 912 amdgpu_job_free(job); 913 return r; 914 } 915 916 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 917 struct amdgpu_ib *ib_msg, 918 struct dma_fence **fence) 919 { 920 unsigned int ib_size_dw = 16; 921 struct amdgpu_job *job; 922 struct amdgpu_ib *ib; 923 struct dma_fence *f = NULL; 924 uint32_t *ib_checksum = NULL; 925 uint64_t addr; 926 bool sq = amdgpu_vcn_using_unified_queue(ring); 927 int i, r; 928 929 if (sq) 930 ib_size_dw += 8; 931 932 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 933 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 934 &job); 935 if (r) 936 return r; 937 938 ib = &job->ibs[0]; 939 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 940 941 ib->length_dw = 0; 942 943 if (sq) 944 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 945 946 ib->ptr[ib->length_dw++] = 0x00000018; 947 ib->ptr[ib->length_dw++] = 0x00000001; 948 ib->ptr[ib->length_dw++] = handle; 949 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 950 ib->ptr[ib->length_dw++] = addr; 951 ib->ptr[ib->length_dw++] = 0x00000000; 952 953 ib->ptr[ib->length_dw++] = 0x00000014; 954 ib->ptr[ib->length_dw++] = 0x00000002; 955 ib->ptr[ib->length_dw++] = 0x0000001c; 956 ib->ptr[ib->length_dw++] = 0x00000000; 957 ib->ptr[ib->length_dw++] = 0x00000000; 958 959 ib->ptr[ib->length_dw++] = 0x00000008; 960 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 961 962 for (i = ib->length_dw; i < ib_size_dw; ++i) 963 ib->ptr[i] = 0x0; 964 965 if (sq) 966 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 967 968 r = amdgpu_job_submit_direct(job, ring, &f); 969 if (r) 970 goto err; 971 972 if (fence) 973 *fence = dma_fence_get(f); 974 dma_fence_put(f); 975 976 return 0; 977 978 err: 979 amdgpu_job_free(job); 980 return r; 981 } 982 983 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 984 { 985 struct amdgpu_device *adev = ring->adev; 986 struct dma_fence *fence = NULL; 987 struct amdgpu_ib ib; 988 long r; 989 990 memset(&ib, 0, sizeof(ib)); 991 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 992 AMDGPU_IB_POOL_DIRECT, 993 &ib); 994 if (r) 995 return r; 996 997 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 998 if (r) 999 goto error; 1000 1001 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 1002 if (r) 1003 goto error; 1004 1005 r = dma_fence_wait_timeout(fence, false, timeout); 1006 if (r == 0) 1007 r = -ETIMEDOUT; 1008 else if (r > 0) 1009 r = 0; 1010 1011 error: 1012 amdgpu_ib_free(adev, &ib, fence); 1013 dma_fence_put(fence); 1014 1015 return r; 1016 } 1017 1018 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1019 { 1020 struct amdgpu_device *adev = ring->adev; 1021 long r; 1022 1023 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(4, 0, 3)) { 1024 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout); 1025 if (r) 1026 goto error; 1027 } 1028 1029 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout); 1030 1031 error: 1032 return r; 1033 } 1034 1035 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 1036 { 1037 switch (ring) { 1038 case 0: 1039 return AMDGPU_RING_PRIO_0; 1040 case 1: 1041 return AMDGPU_RING_PRIO_1; 1042 case 2: 1043 return AMDGPU_RING_PRIO_2; 1044 default: 1045 return AMDGPU_RING_PRIO_0; 1046 } 1047 } 1048 1049 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev) 1050 { 1051 int i; 1052 unsigned int idx; 1053 1054 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1055 const struct common_firmware_header *hdr; 1056 1057 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1058 if (adev->vcn.harvest_config & (1 << i)) 1059 continue; 1060 1061 hdr = (const struct common_firmware_header *)adev->vcn.fw[i]->data; 1062 /* currently only support 2 FW instances */ 1063 if (i >= 2) { 1064 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 1065 break; 1066 } 1067 idx = AMDGPU_UCODE_ID_VCN + i; 1068 adev->firmware.ucode[idx].ucode_id = idx; 1069 adev->firmware.ucode[idx].fw = adev->vcn.fw[i]; 1070 adev->firmware.fw_size += 1071 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 1072 1073 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == 1074 IP_VERSION(4, 0, 3)) 1075 break; 1076 } 1077 } 1078 } 1079 1080 /* 1081 * debugfs for mapping vcn firmware log buffer. 1082 */ 1083 #if defined(CONFIG_DEBUG_FS) 1084 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf, 1085 size_t size, loff_t *pos) 1086 { 1087 struct amdgpu_vcn_inst *vcn; 1088 void *log_buf; 1089 volatile struct amdgpu_vcn_fwlog *plog; 1090 unsigned int read_pos, write_pos, available, i, read_bytes = 0; 1091 unsigned int read_num[2] = {0}; 1092 1093 vcn = file_inode(f)->i_private; 1094 if (!vcn) 1095 return -ENODEV; 1096 1097 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log) 1098 return -EFAULT; 1099 1100 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1101 1102 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf; 1103 read_pos = plog->rptr; 1104 write_pos = plog->wptr; 1105 1106 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE) 1107 return -EFAULT; 1108 1109 if (!size || (read_pos == write_pos)) 1110 return 0; 1111 1112 if (write_pos > read_pos) { 1113 available = write_pos - read_pos; 1114 read_num[0] = min_t(size_t, size, available); 1115 } else { 1116 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos; 1117 available = read_num[0] + write_pos - plog->header_size; 1118 if (size > available) 1119 read_num[1] = write_pos - plog->header_size; 1120 else if (size > read_num[0]) 1121 read_num[1] = size - read_num[0]; 1122 else 1123 read_num[0] = size; 1124 } 1125 1126 for (i = 0; i < 2; i++) { 1127 if (read_num[i]) { 1128 if (read_pos == AMDGPU_VCNFW_LOG_SIZE) 1129 read_pos = plog->header_size; 1130 if (read_num[i] == copy_to_user((buf + read_bytes), 1131 (log_buf + read_pos), read_num[i])) 1132 return -EFAULT; 1133 1134 read_bytes += read_num[i]; 1135 read_pos += read_num[i]; 1136 } 1137 } 1138 1139 plog->rptr = read_pos; 1140 *pos += read_bytes; 1141 return read_bytes; 1142 } 1143 1144 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = { 1145 .owner = THIS_MODULE, 1146 .read = amdgpu_debugfs_vcn_fwlog_read, 1147 .llseek = default_llseek 1148 }; 1149 #endif 1150 1151 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i, 1152 struct amdgpu_vcn_inst *vcn) 1153 { 1154 #if defined(CONFIG_DEBUG_FS) 1155 struct drm_minor *minor = adev_to_drm(adev)->primary; 1156 struct dentry *root = minor->debugfs_root; 1157 char name[32]; 1158 1159 sprintf(name, "amdgpu_vcn_%d_fwlog", i); 1160 debugfs_create_file_size(name, S_IFREG | 0444, root, vcn, 1161 &amdgpu_debugfs_vcnfwlog_fops, 1162 AMDGPU_VCNFW_LOG_SIZE); 1163 #endif 1164 } 1165 1166 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn) 1167 { 1168 #if defined(CONFIG_DEBUG_FS) 1169 volatile uint32_t *flag = vcn->fw_shared.cpu_addr; 1170 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1171 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size; 1172 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr; 1173 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr 1174 + vcn->fw_shared.log_offset; 1175 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG); 1176 fw_log->is_enabled = 1; 1177 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF); 1178 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32); 1179 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE); 1180 1181 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog); 1182 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE; 1183 log_buf->rptr = log_buf->header_size; 1184 log_buf->wptr = log_buf->header_size; 1185 log_buf->wrapped = 0; 1186 #endif 1187 } 1188 1189 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, 1190 struct amdgpu_irq_src *source, 1191 struct amdgpu_iv_entry *entry) 1192 { 1193 struct ras_common_if *ras_if = adev->vcn.ras_if; 1194 struct ras_dispatch_if ih_data = { 1195 .entry = entry, 1196 }; 1197 1198 if (!ras_if) 1199 return 0; 1200 1201 if (!amdgpu_sriov_vf(adev)) { 1202 ih_data.head = *ras_if; 1203 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 1204 } else { 1205 if (adev->virt.ops && adev->virt.ops->ras_poison_handler) 1206 adev->virt.ops->ras_poison_handler(adev, ras_if->block); 1207 else 1208 dev_warn(adev->dev, 1209 "No ras_poison_handler interface in SRIOV for VCN!\n"); 1210 } 1211 1212 return 0; 1213 } 1214 1215 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1216 { 1217 int r, i; 1218 1219 r = amdgpu_ras_block_late_init(adev, ras_block); 1220 if (r) 1221 return r; 1222 1223 if (amdgpu_ras_is_supported(adev, ras_block->block)) { 1224 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1225 if (adev->vcn.harvest_config & (1 << i) || 1226 !adev->vcn.inst[i].ras_poison_irq.funcs) 1227 continue; 1228 1229 r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0); 1230 if (r) 1231 goto late_fini; 1232 } 1233 } 1234 return 0; 1235 1236 late_fini: 1237 amdgpu_ras_block_late_fini(adev, ras_block); 1238 return r; 1239 } 1240 1241 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev) 1242 { 1243 int err; 1244 struct amdgpu_vcn_ras *ras; 1245 1246 if (!adev->vcn.ras) 1247 return 0; 1248 1249 ras = adev->vcn.ras; 1250 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 1251 if (err) { 1252 dev_err(adev->dev, "Failed to register vcn ras block!\n"); 1253 return err; 1254 } 1255 1256 strcpy(ras->ras_block.ras_comm.name, "vcn"); 1257 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; 1258 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; 1259 adev->vcn.ras_if = &ras->ras_block.ras_comm; 1260 1261 if (!ras->ras_block.ras_late_init) 1262 ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init; 1263 1264 return 0; 1265 } 1266 1267 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, 1268 enum AMDGPU_UCODE_ID ucode_id) 1269 { 1270 struct amdgpu_firmware_info ucode = { 1271 .ucode_id = (ucode_id ? ucode_id : 1272 (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 1273 AMDGPU_UCODE_ID_VCN0_RAM)), 1274 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1275 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1276 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr), 1277 }; 1278 1279 return psp_execute_ip_fw_load(&adev->psp, &ucode); 1280 } 1281