1 /* 2 * Copyright 2016-2024 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/dmi.h> 30 #include <linux/pci.h> 31 #include <linux/debugfs.h> 32 #include <drm/drm_drv.h> 33 34 #include "amdgpu.h" 35 #include "amdgpu_pm.h" 36 #include "amdgpu_vcn.h" 37 #include "soc15d.h" 38 39 /* Firmware Names */ 40 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 41 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 42 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 43 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 44 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 45 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 46 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 47 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 48 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 49 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 50 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 51 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 52 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 53 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 54 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 55 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 56 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin" 57 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin" 58 #define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin" 59 #define FIRMWARE_VCN4_0_3 "amdgpu/vcn_4_0_3.bin" 60 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin" 61 #define FIRMWARE_VCN4_0_5 "amdgpu/vcn_4_0_5.bin" 62 #define FIRMWARE_VCN4_0_6 "amdgpu/vcn_4_0_6.bin" 63 #define FIRMWARE_VCN4_0_6_1 "amdgpu/vcn_4_0_6_1.bin" 64 #define FIRMWARE_VCN5_0_0 "amdgpu/vcn_5_0_0.bin" 65 #define FIRMWARE_VCN5_0_1 "amdgpu/vcn_5_0_1.bin" 66 67 MODULE_FIRMWARE(FIRMWARE_RAVEN); 68 MODULE_FIRMWARE(FIRMWARE_PICASSO); 69 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 70 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 71 MODULE_FIRMWARE(FIRMWARE_RENOIR); 72 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 73 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 74 MODULE_FIRMWARE(FIRMWARE_NAVI10); 75 MODULE_FIRMWARE(FIRMWARE_NAVI14); 76 MODULE_FIRMWARE(FIRMWARE_NAVI12); 77 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 78 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 79 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 80 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 81 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 82 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 83 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2); 84 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0); 85 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2); 86 MODULE_FIRMWARE(FIRMWARE_VCN4_0_3); 87 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4); 88 MODULE_FIRMWARE(FIRMWARE_VCN4_0_5); 89 MODULE_FIRMWARE(FIRMWARE_VCN4_0_6); 90 MODULE_FIRMWARE(FIRMWARE_VCN4_0_6_1); 91 MODULE_FIRMWARE(FIRMWARE_VCN5_0_0); 92 MODULE_FIRMWARE(FIRMWARE_VCN5_0_1); 93 94 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 95 static void amdgpu_vcn_reg_dump_fini(struct amdgpu_device *adev); 96 97 int amdgpu_vcn_early_init(struct amdgpu_device *adev, int i) 98 { 99 char ucode_prefix[25]; 100 int r; 101 102 adev->vcn.inst[i].adev = adev; 103 adev->vcn.inst[i].inst = i; 104 amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix)); 105 106 if (i != 0 && adev->vcn.per_inst_fw) { 107 r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw, 108 AMDGPU_UCODE_REQUIRED, 109 "amdgpu/%s_%d.bin", ucode_prefix, i); 110 if (r) 111 amdgpu_ucode_release(&adev->vcn.inst[i].fw); 112 } else { 113 if (!adev->vcn.inst[0].fw) { 114 r = amdgpu_ucode_request(adev, &adev->vcn.inst[0].fw, 115 AMDGPU_UCODE_REQUIRED, 116 "amdgpu/%s.bin", ucode_prefix); 117 if (r) 118 amdgpu_ucode_release(&adev->vcn.inst[0].fw); 119 } else { 120 r = 0; 121 } 122 adev->vcn.inst[i].fw = adev->vcn.inst[0].fw; 123 } 124 125 return r; 126 } 127 128 int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int i) 129 { 130 unsigned long bo_size; 131 const struct common_firmware_header *hdr; 132 unsigned char fw_check; 133 unsigned int fw_shared_size, log_offset; 134 int r; 135 136 mutex_init(&adev->vcn.inst[i].vcn1_jpeg1_workaround); 137 mutex_init(&adev->vcn.inst[i].vcn_pg_lock); 138 mutex_init(&adev->vcn.inst[i].engine_reset_mutex); 139 atomic_set(&adev->vcn.inst[i].total_submission_cnt, 0); 140 INIT_DELAYED_WORK(&adev->vcn.inst[i].idle_work, amdgpu_vcn_idle_work_handler); 141 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 142 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 143 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 144 adev->vcn.inst[i].indirect_sram = true; 145 146 /* 147 * Some Steam Deck's BIOS versions are incompatible with the 148 * indirect SRAM mode, leading to amdgpu being unable to get 149 * properly probed (and even potentially crashing the kernel). 150 * Hence, check for these versions here - notice this is 151 * restricted to Vangogh (Deck's APU). 152 */ 153 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 0, 2)) { 154 const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION); 155 156 if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) || 157 !strncmp("F7A0114", bios_ver, 7))) { 158 adev->vcn.inst[i].indirect_sram = false; 159 dev_info(adev->dev, 160 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver); 161 } 162 } 163 164 /* from vcn4 and above, only unified queue is used */ 165 adev->vcn.inst[i].using_unified_queue = 166 amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0); 167 168 hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data; 169 adev->vcn.inst[i].fw_version = le32_to_cpu(hdr->ucode_version); 170 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 171 172 /* Bit 20-23, it is encode major and non-zero for new naming convention. 173 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 174 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 175 * is zero in old naming convention, this field is always zero so far. 176 * These four bits are used to tell which naming convention is present. 177 */ 178 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 179 if (fw_check) { 180 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 181 182 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 183 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 184 enc_major = fw_check; 185 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 186 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 187 dev_info(adev->dev, 188 "Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 189 enc_major, enc_minor, dec_ver, vep, fw_rev); 190 } else { 191 unsigned int version_major, version_minor, family_id; 192 193 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 194 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 195 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 196 dev_info(adev->dev, "Found VCN firmware Version: %u.%u Family ID: %u\n", 197 version_major, version_minor, family_id); 198 } 199 200 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 201 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 202 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 203 204 if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(5, 0, 0)) { 205 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)); 206 log_offset = offsetof(struct amdgpu_vcn5_fw_shared, fw_log); 207 } else if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) { 208 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); 209 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log); 210 } else { 211 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 212 log_offset = offsetof(struct amdgpu_fw_shared, fw_log); 213 } 214 215 bo_size += fw_shared_size; 216 217 if (amdgpu_vcnfw_log) 218 bo_size += AMDGPU_VCNFW_LOG_SIZE; 219 220 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 221 AMDGPU_GEM_DOMAIN_VRAM | 222 AMDGPU_GEM_DOMAIN_GTT, 223 &adev->vcn.inst[i].vcpu_bo, 224 &adev->vcn.inst[i].gpu_addr, 225 &adev->vcn.inst[i].cpu_addr); 226 if (r) { 227 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 228 return r; 229 } 230 231 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr + 232 bo_size - fw_shared_size; 233 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr + 234 bo_size - fw_shared_size; 235 236 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size; 237 238 if (amdgpu_vcnfw_log) { 239 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 240 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 241 adev->vcn.inst[i].fw_shared.log_offset = log_offset; 242 } 243 244 if (adev->vcn.inst[i].indirect_sram) { 245 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 246 AMDGPU_GEM_DOMAIN_VRAM | 247 AMDGPU_GEM_DOMAIN_GTT, 248 &adev->vcn.inst[i].dpg_sram_bo, 249 &adev->vcn.inst[i].dpg_sram_gpu_addr, 250 &adev->vcn.inst[i].dpg_sram_cpu_addr); 251 if (r) { 252 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 253 return r; 254 } 255 } 256 257 return 0; 258 } 259 260 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int i) 261 { 262 int j; 263 264 if (adev->vcn.harvest_config & (1 << i)) 265 return 0; 266 267 amdgpu_bo_free_kernel( 268 &adev->vcn.inst[i].dpg_sram_bo, 269 &adev->vcn.inst[i].dpg_sram_gpu_addr, 270 (void **)&adev->vcn.inst[i].dpg_sram_cpu_addr); 271 272 kvfree(adev->vcn.inst[i].saved_bo); 273 274 amdgpu_bo_free_kernel(&adev->vcn.inst[i].vcpu_bo, 275 &adev->vcn.inst[i].gpu_addr, 276 (void **)&adev->vcn.inst[i].cpu_addr); 277 278 amdgpu_ring_fini(&adev->vcn.inst[i].ring_dec); 279 280 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) 281 amdgpu_ring_fini(&adev->vcn.inst[i].ring_enc[j]); 282 283 if (adev->vcn.per_inst_fw) { 284 amdgpu_ucode_release(&adev->vcn.inst[i].fw); 285 } else { 286 amdgpu_ucode_release(&adev->vcn.inst[0].fw); 287 adev->vcn.inst[i].fw = NULL; 288 } 289 290 if (adev->vcn.reg_list) 291 amdgpu_vcn_reg_dump_fini(adev); 292 293 mutex_destroy(&adev->vcn.inst[i].vcn_pg_lock); 294 mutex_destroy(&adev->vcn.inst[i].vcn1_jpeg1_workaround); 295 296 return 0; 297 } 298 299 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 300 { 301 bool ret = false; 302 int vcn_config = adev->vcn.inst[vcn_instance].vcn_config; 303 304 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) 305 ret = true; 306 else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) 307 ret = true; 308 else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) 309 ret = true; 310 311 return ret; 312 } 313 314 static int amdgpu_vcn_save_vcpu_bo_inst(struct amdgpu_device *adev, int i) 315 { 316 unsigned int size; 317 void *ptr; 318 int idx; 319 320 if (adev->vcn.harvest_config & (1 << i)) 321 return 0; 322 if (adev->vcn.inst[i].vcpu_bo == NULL) 323 return 0; 324 325 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 326 ptr = adev->vcn.inst[i].cpu_addr; 327 328 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 329 if (!adev->vcn.inst[i].saved_bo) 330 return -ENOMEM; 331 332 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 333 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 334 drm_dev_exit(idx); 335 } 336 337 return 0; 338 } 339 340 int amdgpu_vcn_save_vcpu_bo(struct amdgpu_device *adev) 341 { 342 int ret, i; 343 344 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 345 ret = amdgpu_vcn_save_vcpu_bo_inst(adev, i); 346 if (ret) 347 return ret; 348 } 349 350 return 0; 351 } 352 353 int amdgpu_vcn_suspend(struct amdgpu_device *adev, int i) 354 { 355 bool in_ras_intr = amdgpu_ras_intr_triggered(); 356 357 if (adev->vcn.harvest_config & (1 << i)) 358 return 0; 359 360 /* err_event_athub and dpc recovery will corrupt VCPU buffer, so we need to 361 * restore fw data and clear buffer in amdgpu_vcn_resume() */ 362 if (in_ras_intr || adev->pcie_reset_ctx.in_link_reset) 363 return 0; 364 365 return amdgpu_vcn_save_vcpu_bo_inst(adev, i); 366 } 367 368 int amdgpu_vcn_resume(struct amdgpu_device *adev, int i) 369 { 370 unsigned int size; 371 void *ptr; 372 int idx; 373 374 if (adev->vcn.harvest_config & (1 << i)) 375 return 0; 376 if (adev->vcn.inst[i].vcpu_bo == NULL) 377 return -EINVAL; 378 379 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 380 ptr = adev->vcn.inst[i].cpu_addr; 381 382 if (adev->vcn.inst[i].saved_bo != NULL) { 383 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 384 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 385 drm_dev_exit(idx); 386 } 387 kvfree(adev->vcn.inst[i].saved_bo); 388 adev->vcn.inst[i].saved_bo = NULL; 389 } else { 390 const struct common_firmware_header *hdr; 391 unsigned int offset; 392 393 hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data; 394 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 395 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 396 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 397 memcpy_toio(adev->vcn.inst[i].cpu_addr, 398 adev->vcn.inst[i].fw->data + offset, 399 le32_to_cpu(hdr->ucode_size_bytes)); 400 drm_dev_exit(idx); 401 } 402 size -= le32_to_cpu(hdr->ucode_size_bytes); 403 ptr += le32_to_cpu(hdr->ucode_size_bytes); 404 } 405 memset_io(ptr, 0, size); 406 } 407 408 return 0; 409 } 410 411 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 412 { 413 struct amdgpu_vcn_inst *vcn_inst = 414 container_of(work, struct amdgpu_vcn_inst, idle_work.work); 415 struct amdgpu_device *adev = vcn_inst->adev; 416 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 417 unsigned int i = vcn_inst->inst, j; 418 int r = 0; 419 420 if (adev->vcn.harvest_config & (1 << i)) 421 return; 422 423 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) 424 fence[i] += amdgpu_fence_count_emitted(&vcn_inst->ring_enc[j]); 425 426 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 427 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 428 !adev->vcn.inst[i].using_unified_queue) { 429 struct dpg_pause_state new_state; 430 431 if (fence[i] || 432 unlikely(atomic_read(&vcn_inst->dpg_enc_submission_cnt))) 433 new_state.fw_based = VCN_DPG_STATE__PAUSE; 434 else 435 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 436 437 adev->vcn.inst[i].pause_dpg_mode(vcn_inst, &new_state); 438 } 439 440 fence[i] += amdgpu_fence_count_emitted(&vcn_inst->ring_dec); 441 fences += fence[i]; 442 443 if (!fences && !atomic_read(&vcn_inst->total_submission_cnt)) { 444 mutex_lock(&vcn_inst->vcn_pg_lock); 445 vcn_inst->set_pg_state(vcn_inst, AMD_PG_STATE_GATE); 446 mutex_unlock(&vcn_inst->vcn_pg_lock); 447 mutex_lock(&adev->vcn.workload_profile_mutex); 448 if (adev->vcn.workload_profile_active) { 449 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 450 false); 451 if (r) 452 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 453 adev->vcn.workload_profile_active = false; 454 } 455 mutex_unlock(&adev->vcn.workload_profile_mutex); 456 } else { 457 schedule_delayed_work(&vcn_inst->idle_work, VCN_IDLE_TIMEOUT); 458 } 459 } 460 461 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 462 { 463 struct amdgpu_device *adev = ring->adev; 464 struct amdgpu_vcn_inst *vcn_inst = &adev->vcn.inst[ring->me]; 465 int r = 0; 466 467 atomic_inc(&vcn_inst->total_submission_cnt); 468 469 cancel_delayed_work_sync(&vcn_inst->idle_work); 470 471 /* We can safely return early here because we've cancelled the 472 * the delayed work so there is no one else to set it to false 473 * and we don't care if someone else sets it to true. 474 */ 475 if (adev->vcn.workload_profile_active) 476 goto pg_lock; 477 478 mutex_lock(&adev->vcn.workload_profile_mutex); 479 if (!adev->vcn.workload_profile_active) { 480 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 481 true); 482 if (r) 483 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 484 adev->vcn.workload_profile_active = true; 485 } 486 mutex_unlock(&adev->vcn.workload_profile_mutex); 487 488 pg_lock: 489 mutex_lock(&vcn_inst->vcn_pg_lock); 490 vcn_inst->set_pg_state(vcn_inst, AMD_PG_STATE_UNGATE); 491 492 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 493 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 494 !vcn_inst->using_unified_queue) { 495 struct dpg_pause_state new_state; 496 497 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 498 atomic_inc(&vcn_inst->dpg_enc_submission_cnt); 499 new_state.fw_based = VCN_DPG_STATE__PAUSE; 500 } else { 501 unsigned int fences = 0; 502 unsigned int i; 503 504 for (i = 0; i < vcn_inst->num_enc_rings; ++i) 505 fences += amdgpu_fence_count_emitted(&vcn_inst->ring_enc[i]); 506 507 if (fences || atomic_read(&vcn_inst->dpg_enc_submission_cnt)) 508 new_state.fw_based = VCN_DPG_STATE__PAUSE; 509 else 510 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 511 } 512 513 vcn_inst->pause_dpg_mode(vcn_inst, &new_state); 514 } 515 mutex_unlock(&vcn_inst->vcn_pg_lock); 516 } 517 518 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 519 { 520 struct amdgpu_device *adev = ring->adev; 521 522 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 523 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 524 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC && 525 !adev->vcn.inst[ring->me].using_unified_queue) 526 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 527 528 atomic_dec(&ring->adev->vcn.inst[ring->me].total_submission_cnt); 529 530 schedule_delayed_work(&ring->adev->vcn.inst[ring->me].idle_work, 531 VCN_IDLE_TIMEOUT); 532 } 533 534 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 535 { 536 struct amdgpu_device *adev = ring->adev; 537 uint32_t tmp = 0; 538 unsigned int i; 539 int r; 540 541 /* VCN in SRIOV does not support direct register read/write */ 542 if (amdgpu_sriov_vf(adev)) 543 return 0; 544 545 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 546 r = amdgpu_ring_alloc(ring, 3); 547 if (r) 548 return r; 549 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.scratch9, 0)); 550 amdgpu_ring_write(ring, 0xDEADBEEF); 551 amdgpu_ring_commit(ring); 552 for (i = 0; i < adev->usec_timeout; i++) { 553 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 554 if (tmp == 0xDEADBEEF) 555 break; 556 udelay(1); 557 } 558 559 if (i >= adev->usec_timeout) 560 r = -ETIMEDOUT; 561 562 return r; 563 } 564 565 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 566 { 567 struct amdgpu_device *adev = ring->adev; 568 uint32_t rptr; 569 unsigned int i; 570 int r; 571 572 if (amdgpu_sriov_vf(adev)) 573 return 0; 574 575 r = amdgpu_ring_alloc(ring, 16); 576 if (r) 577 return r; 578 579 rptr = amdgpu_ring_get_rptr(ring); 580 581 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 582 amdgpu_ring_commit(ring); 583 584 for (i = 0; i < adev->usec_timeout; i++) { 585 if (amdgpu_ring_get_rptr(ring) != rptr) 586 break; 587 udelay(1); 588 } 589 590 if (i >= adev->usec_timeout) 591 r = -ETIMEDOUT; 592 593 return r; 594 } 595 596 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 597 struct amdgpu_ib *ib_msg, 598 struct dma_fence **fence) 599 { 600 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 601 struct amdgpu_device *adev = ring->adev; 602 struct dma_fence *f = NULL; 603 struct amdgpu_job *job; 604 struct amdgpu_ib *ib; 605 int i, r; 606 607 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 608 64, AMDGPU_IB_POOL_DIRECT, 609 &job); 610 if (r) 611 goto err; 612 613 ib = &job->ibs[0]; 614 ib->ptr[0] = PACKET0(adev->vcn.inst[ring->me].internal.data0, 0); 615 ib->ptr[1] = addr; 616 ib->ptr[2] = PACKET0(adev->vcn.inst[ring->me].internal.data1, 0); 617 ib->ptr[3] = addr >> 32; 618 ib->ptr[4] = PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0); 619 ib->ptr[5] = 0; 620 for (i = 6; i < 16; i += 2) { 621 ib->ptr[i] = PACKET0(adev->vcn.inst[ring->me].internal.nop, 0); 622 ib->ptr[i+1] = 0; 623 } 624 ib->length_dw = 16; 625 626 r = amdgpu_job_submit_direct(job, ring, &f); 627 if (r) 628 goto err_free; 629 630 amdgpu_ib_free(ib_msg, f); 631 632 if (fence) 633 *fence = dma_fence_get(f); 634 dma_fence_put(f); 635 636 return 0; 637 638 err_free: 639 amdgpu_job_free(job); 640 err: 641 amdgpu_ib_free(ib_msg, f); 642 return r; 643 } 644 645 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 646 struct amdgpu_ib *ib) 647 { 648 struct amdgpu_device *adev = ring->adev; 649 uint32_t *msg; 650 int r, i; 651 652 memset(ib, 0, sizeof(*ib)); 653 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 654 AMDGPU_IB_POOL_DIRECT, 655 ib); 656 if (r) 657 return r; 658 659 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 660 msg[0] = cpu_to_le32(0x00000028); 661 msg[1] = cpu_to_le32(0x00000038); 662 msg[2] = cpu_to_le32(0x00000001); 663 msg[3] = cpu_to_le32(0x00000000); 664 msg[4] = cpu_to_le32(handle); 665 msg[5] = cpu_to_le32(0x00000000); 666 msg[6] = cpu_to_le32(0x00000001); 667 msg[7] = cpu_to_le32(0x00000028); 668 msg[8] = cpu_to_le32(0x00000010); 669 msg[9] = cpu_to_le32(0x00000000); 670 msg[10] = cpu_to_le32(0x00000007); 671 msg[11] = cpu_to_le32(0x00000000); 672 msg[12] = cpu_to_le32(0x00000780); 673 msg[13] = cpu_to_le32(0x00000440); 674 for (i = 14; i < 1024; ++i) 675 msg[i] = cpu_to_le32(0x0); 676 677 return 0; 678 } 679 680 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 681 struct amdgpu_ib *ib) 682 { 683 struct amdgpu_device *adev = ring->adev; 684 uint32_t *msg; 685 int r, i; 686 687 memset(ib, 0, sizeof(*ib)); 688 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 689 AMDGPU_IB_POOL_DIRECT, 690 ib); 691 if (r) 692 return r; 693 694 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 695 msg[0] = cpu_to_le32(0x00000028); 696 msg[1] = cpu_to_le32(0x00000018); 697 msg[2] = cpu_to_le32(0x00000000); 698 msg[3] = cpu_to_le32(0x00000002); 699 msg[4] = cpu_to_le32(handle); 700 msg[5] = cpu_to_le32(0x00000000); 701 for (i = 6; i < 1024; ++i) 702 msg[i] = cpu_to_le32(0x0); 703 704 return 0; 705 } 706 707 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 708 { 709 struct dma_fence *fence = NULL; 710 struct amdgpu_ib ib; 711 long r; 712 713 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 714 if (r) 715 goto error; 716 717 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 718 if (r) 719 goto error; 720 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 721 if (r) 722 goto error; 723 724 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 725 if (r) 726 goto error; 727 728 r = dma_fence_wait_timeout(fence, false, timeout); 729 if (r == 0) 730 r = -ETIMEDOUT; 731 else if (r > 0) 732 r = 0; 733 734 dma_fence_put(fence); 735 error: 736 return r; 737 } 738 739 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, 740 uint32_t ib_pack_in_dw, bool enc) 741 { 742 uint32_t *ib_checksum; 743 744 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */ 745 ib->ptr[ib->length_dw++] = 0x30000002; 746 ib_checksum = &ib->ptr[ib->length_dw++]; 747 ib->ptr[ib->length_dw++] = ib_pack_in_dw; 748 749 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */ 750 ib->ptr[ib->length_dw++] = 0x30000001; 751 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3; 752 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t); 753 754 return ib_checksum; 755 } 756 757 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum, 758 uint32_t ib_pack_in_dw) 759 { 760 uint32_t i; 761 uint32_t checksum = 0; 762 763 for (i = 0; i < ib_pack_in_dw; i++) 764 checksum += *(*ib_checksum + 2 + i); 765 766 **ib_checksum = checksum; 767 } 768 769 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 770 struct amdgpu_ib *ib_msg, 771 struct dma_fence **fence) 772 { 773 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 774 unsigned int ib_size_dw = 64; 775 struct amdgpu_device *adev = ring->adev; 776 struct dma_fence *f = NULL; 777 struct amdgpu_job *job; 778 struct amdgpu_ib *ib; 779 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 780 uint32_t *ib_checksum; 781 uint32_t ib_pack_in_dw; 782 int i, r; 783 784 if (adev->vcn.inst[ring->me].using_unified_queue) 785 ib_size_dw += 8; 786 787 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 788 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 789 &job); 790 if (r) 791 goto err; 792 793 ib = &job->ibs[0]; 794 ib->length_dw = 0; 795 796 /* single queue headers */ 797 if (adev->vcn.inst[ring->me].using_unified_queue) { 798 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t) 799 + 4 + 2; /* engine info + decoding ib in dw */ 800 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false); 801 } 802 803 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 804 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 805 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 806 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 807 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 808 809 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 810 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 811 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 812 813 for (i = ib->length_dw; i < ib_size_dw; ++i) 814 ib->ptr[i] = 0x0; 815 816 if (adev->vcn.inst[ring->me].using_unified_queue) 817 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw); 818 819 r = amdgpu_job_submit_direct(job, ring, &f); 820 if (r) 821 goto err_free; 822 823 amdgpu_ib_free(ib_msg, f); 824 825 if (fence) 826 *fence = dma_fence_get(f); 827 dma_fence_put(f); 828 829 return 0; 830 831 err_free: 832 amdgpu_job_free(job); 833 err: 834 amdgpu_ib_free(ib_msg, f); 835 return r; 836 } 837 838 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 839 { 840 struct dma_fence *fence = NULL; 841 struct amdgpu_ib ib; 842 long r; 843 844 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 845 if (r) 846 goto error; 847 848 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 849 if (r) 850 goto error; 851 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 852 if (r) 853 goto error; 854 855 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 856 if (r) 857 goto error; 858 859 r = dma_fence_wait_timeout(fence, false, timeout); 860 if (r == 0) 861 r = -ETIMEDOUT; 862 else if (r > 0) 863 r = 0; 864 865 dma_fence_put(fence); 866 error: 867 return r; 868 } 869 870 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 871 { 872 struct amdgpu_device *adev = ring->adev; 873 uint32_t rptr; 874 unsigned int i; 875 int r; 876 877 if (amdgpu_sriov_vf(adev)) 878 return 0; 879 880 r = amdgpu_ring_alloc(ring, 16); 881 if (r) 882 return r; 883 884 rptr = amdgpu_ring_get_rptr(ring); 885 886 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 887 amdgpu_ring_commit(ring); 888 889 for (i = 0; i < adev->usec_timeout; i++) { 890 if (amdgpu_ring_get_rptr(ring) != rptr) 891 break; 892 udelay(1); 893 } 894 895 if (i >= adev->usec_timeout) 896 r = -ETIMEDOUT; 897 898 return r; 899 } 900 901 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 902 struct amdgpu_ib *ib_msg, 903 struct dma_fence **fence) 904 { 905 unsigned int ib_size_dw = 16; 906 struct amdgpu_device *adev = ring->adev; 907 struct amdgpu_job *job; 908 struct amdgpu_ib *ib; 909 struct dma_fence *f = NULL; 910 uint32_t *ib_checksum = NULL; 911 uint64_t addr; 912 int i, r; 913 914 if (adev->vcn.inst[ring->me].using_unified_queue) 915 ib_size_dw += 8; 916 917 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 918 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 919 &job); 920 if (r) 921 return r; 922 923 ib = &job->ibs[0]; 924 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 925 926 ib->length_dw = 0; 927 928 if (adev->vcn.inst[ring->me].using_unified_queue) 929 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 930 931 ib->ptr[ib->length_dw++] = 0x00000018; 932 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 933 ib->ptr[ib->length_dw++] = handle; 934 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 935 ib->ptr[ib->length_dw++] = addr; 936 ib->ptr[ib->length_dw++] = 0x00000000; 937 938 ib->ptr[ib->length_dw++] = 0x00000014; 939 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 940 ib->ptr[ib->length_dw++] = 0x0000001c; 941 ib->ptr[ib->length_dw++] = 0x00000000; 942 ib->ptr[ib->length_dw++] = 0x00000000; 943 944 ib->ptr[ib->length_dw++] = 0x00000008; 945 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 946 947 for (i = ib->length_dw; i < ib_size_dw; ++i) 948 ib->ptr[i] = 0x0; 949 950 if (adev->vcn.inst[ring->me].using_unified_queue) 951 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 952 953 r = amdgpu_job_submit_direct(job, ring, &f); 954 if (r) 955 goto err; 956 957 if (fence) 958 *fence = dma_fence_get(f); 959 dma_fence_put(f); 960 961 return 0; 962 963 err: 964 amdgpu_job_free(job); 965 return r; 966 } 967 968 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 969 struct amdgpu_ib *ib_msg, 970 struct dma_fence **fence) 971 { 972 unsigned int ib_size_dw = 16; 973 struct amdgpu_device *adev = ring->adev; 974 struct amdgpu_job *job; 975 struct amdgpu_ib *ib; 976 struct dma_fence *f = NULL; 977 uint32_t *ib_checksum = NULL; 978 uint64_t addr; 979 int i, r; 980 981 if (adev->vcn.inst[ring->me].using_unified_queue) 982 ib_size_dw += 8; 983 984 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 985 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 986 &job); 987 if (r) 988 return r; 989 990 ib = &job->ibs[0]; 991 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 992 993 ib->length_dw = 0; 994 995 if (adev->vcn.inst[ring->me].using_unified_queue) 996 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 997 998 ib->ptr[ib->length_dw++] = 0x00000018; 999 ib->ptr[ib->length_dw++] = 0x00000001; 1000 ib->ptr[ib->length_dw++] = handle; 1001 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1002 ib->ptr[ib->length_dw++] = addr; 1003 ib->ptr[ib->length_dw++] = 0x00000000; 1004 1005 ib->ptr[ib->length_dw++] = 0x00000014; 1006 ib->ptr[ib->length_dw++] = 0x00000002; 1007 ib->ptr[ib->length_dw++] = 0x0000001c; 1008 ib->ptr[ib->length_dw++] = 0x00000000; 1009 ib->ptr[ib->length_dw++] = 0x00000000; 1010 1011 ib->ptr[ib->length_dw++] = 0x00000008; 1012 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 1013 1014 for (i = ib->length_dw; i < ib_size_dw; ++i) 1015 ib->ptr[i] = 0x0; 1016 1017 if (adev->vcn.inst[ring->me].using_unified_queue) 1018 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 1019 1020 r = amdgpu_job_submit_direct(job, ring, &f); 1021 if (r) 1022 goto err; 1023 1024 if (fence) 1025 *fence = dma_fence_get(f); 1026 dma_fence_put(f); 1027 1028 return 0; 1029 1030 err: 1031 amdgpu_job_free(job); 1032 return r; 1033 } 1034 1035 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1036 { 1037 struct amdgpu_device *adev = ring->adev; 1038 struct dma_fence *fence = NULL; 1039 struct amdgpu_ib ib; 1040 long r; 1041 1042 memset(&ib, 0, sizeof(ib)); 1043 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 1044 AMDGPU_IB_POOL_DIRECT, 1045 &ib); 1046 if (r) 1047 return r; 1048 1049 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 1050 if (r) 1051 goto error; 1052 1053 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 1054 if (r) 1055 goto error; 1056 1057 r = dma_fence_wait_timeout(fence, false, timeout); 1058 if (r == 0) 1059 r = -ETIMEDOUT; 1060 else if (r > 0) 1061 r = 0; 1062 1063 error: 1064 amdgpu_ib_free(&ib, fence); 1065 dma_fence_put(fence); 1066 1067 return r; 1068 } 1069 1070 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1071 { 1072 struct amdgpu_device *adev = ring->adev; 1073 long r; 1074 1075 if ((amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(4, 0, 3)) && 1076 (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(5, 0, 1))) { 1077 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout); 1078 if (r) 1079 goto error; 1080 } 1081 1082 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout); 1083 1084 error: 1085 return r; 1086 } 1087 1088 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 1089 { 1090 switch (ring) { 1091 case 0: 1092 return AMDGPU_RING_PRIO_0; 1093 case 1: 1094 return AMDGPU_RING_PRIO_1; 1095 case 2: 1096 return AMDGPU_RING_PRIO_2; 1097 default: 1098 return AMDGPU_RING_PRIO_0; 1099 } 1100 } 1101 1102 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev, int i) 1103 { 1104 unsigned int idx; 1105 1106 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1107 const struct common_firmware_header *hdr; 1108 1109 if (adev->vcn.harvest_config & (1 << i)) 1110 return; 1111 1112 if ((amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 3) || 1113 amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(5, 0, 1)) 1114 && (i > 0)) 1115 return; 1116 1117 hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data; 1118 /* currently only support 2 FW instances */ 1119 if (i >= 2) { 1120 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 1121 return; 1122 } 1123 idx = AMDGPU_UCODE_ID_VCN + i; 1124 adev->firmware.ucode[idx].ucode_id = idx; 1125 adev->firmware.ucode[idx].fw = adev->vcn.inst[i].fw; 1126 adev->firmware.fw_size += 1127 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 1128 } 1129 } 1130 1131 /* 1132 * debugfs for mapping vcn firmware log buffer. 1133 */ 1134 #if defined(CONFIG_DEBUG_FS) 1135 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf, 1136 size_t size, loff_t *pos) 1137 { 1138 struct amdgpu_vcn_inst *vcn; 1139 void *log_buf; 1140 volatile struct amdgpu_vcn_fwlog *plog; 1141 unsigned int read_pos, write_pos, available, i, read_bytes = 0; 1142 unsigned int read_num[2] = {0}; 1143 1144 vcn = file_inode(f)->i_private; 1145 if (!vcn) 1146 return -ENODEV; 1147 1148 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log) 1149 return -EFAULT; 1150 1151 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1152 1153 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf; 1154 read_pos = plog->rptr; 1155 write_pos = plog->wptr; 1156 1157 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE) 1158 return -EFAULT; 1159 1160 if (!size || (read_pos == write_pos)) 1161 return 0; 1162 1163 if (write_pos > read_pos) { 1164 available = write_pos - read_pos; 1165 read_num[0] = min_t(size_t, size, available); 1166 } else { 1167 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos; 1168 available = read_num[0] + write_pos - plog->header_size; 1169 if (size > available) 1170 read_num[1] = write_pos - plog->header_size; 1171 else if (size > read_num[0]) 1172 read_num[1] = size - read_num[0]; 1173 else 1174 read_num[0] = size; 1175 } 1176 1177 for (i = 0; i < 2; i++) { 1178 if (read_num[i]) { 1179 if (read_pos == AMDGPU_VCNFW_LOG_SIZE) 1180 read_pos = plog->header_size; 1181 if (read_num[i] == copy_to_user((buf + read_bytes), 1182 (log_buf + read_pos), read_num[i])) 1183 return -EFAULT; 1184 1185 read_bytes += read_num[i]; 1186 read_pos += read_num[i]; 1187 } 1188 } 1189 1190 plog->rptr = read_pos; 1191 *pos += read_bytes; 1192 return read_bytes; 1193 } 1194 1195 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = { 1196 .owner = THIS_MODULE, 1197 .read = amdgpu_debugfs_vcn_fwlog_read, 1198 .llseek = default_llseek 1199 }; 1200 #endif 1201 1202 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i, 1203 struct amdgpu_vcn_inst *vcn) 1204 { 1205 #if defined(CONFIG_DEBUG_FS) 1206 struct drm_minor *minor = adev_to_drm(adev)->primary; 1207 struct dentry *root = minor->debugfs_root; 1208 char name[32]; 1209 1210 sprintf(name, "amdgpu_vcn_%d_fwlog", i); 1211 debugfs_create_file_size(name, S_IFREG | 0444, root, vcn, 1212 &amdgpu_debugfs_vcnfwlog_fops, 1213 AMDGPU_VCNFW_LOG_SIZE); 1214 #endif 1215 } 1216 1217 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn) 1218 { 1219 #if defined(CONFIG_DEBUG_FS) 1220 volatile uint32_t *flag = vcn->fw_shared.cpu_addr; 1221 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1222 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size; 1223 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr; 1224 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr 1225 + vcn->fw_shared.log_offset; 1226 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG); 1227 fw_log->is_enabled = 1; 1228 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF); 1229 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32); 1230 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE); 1231 1232 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog); 1233 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE; 1234 log_buf->rptr = log_buf->header_size; 1235 log_buf->wptr = log_buf->header_size; 1236 log_buf->wrapped = 0; 1237 #endif 1238 } 1239 1240 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, 1241 struct amdgpu_irq_src *source, 1242 struct amdgpu_iv_entry *entry) 1243 { 1244 struct ras_common_if *ras_if = adev->vcn.ras_if; 1245 struct ras_dispatch_if ih_data = { 1246 .entry = entry, 1247 }; 1248 1249 if (!ras_if) 1250 return 0; 1251 1252 if (!amdgpu_sriov_vf(adev)) { 1253 ih_data.head = *ras_if; 1254 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 1255 } else { 1256 if (adev->virt.ops && adev->virt.ops->ras_poison_handler) 1257 adev->virt.ops->ras_poison_handler(adev, ras_if->block); 1258 else 1259 dev_warn(adev->dev, 1260 "No ras_poison_handler interface in SRIOV for VCN!\n"); 1261 } 1262 1263 return 0; 1264 } 1265 1266 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1267 { 1268 int r, i; 1269 1270 r = amdgpu_ras_block_late_init(adev, ras_block); 1271 if (r) 1272 return r; 1273 1274 if (amdgpu_ras_is_supported(adev, ras_block->block)) { 1275 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1276 if (adev->vcn.harvest_config & (1 << i) || 1277 !adev->vcn.inst[i].ras_poison_irq.funcs) 1278 continue; 1279 1280 r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0); 1281 if (r) 1282 goto late_fini; 1283 } 1284 } 1285 return 0; 1286 1287 late_fini: 1288 amdgpu_ras_block_late_fini(adev, ras_block); 1289 return r; 1290 } 1291 1292 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev) 1293 { 1294 int err; 1295 struct amdgpu_vcn_ras *ras; 1296 1297 if (!adev->vcn.ras) 1298 return 0; 1299 1300 ras = adev->vcn.ras; 1301 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 1302 if (err) { 1303 dev_err(adev->dev, "Failed to register vcn ras block!\n"); 1304 return err; 1305 } 1306 1307 strcpy(ras->ras_block.ras_comm.name, "vcn"); 1308 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; 1309 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; 1310 adev->vcn.ras_if = &ras->ras_block.ras_comm; 1311 1312 if (!ras->ras_block.ras_late_init) 1313 ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init; 1314 1315 return 0; 1316 } 1317 1318 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, 1319 enum AMDGPU_UCODE_ID ucode_id) 1320 { 1321 struct amdgpu_firmware_info ucode = { 1322 .ucode_id = (ucode_id ? ucode_id : 1323 (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 1324 AMDGPU_UCODE_ID_VCN0_RAM)), 1325 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1326 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1327 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr), 1328 }; 1329 1330 return psp_execute_ip_fw_load(&adev->psp, &ucode); 1331 } 1332 1333 static ssize_t amdgpu_get_vcn_reset_mask(struct device *dev, 1334 struct device_attribute *attr, 1335 char *buf) 1336 { 1337 struct drm_device *ddev = dev_get_drvdata(dev); 1338 struct amdgpu_device *adev = drm_to_adev(ddev); 1339 1340 if (!adev) 1341 return -ENODEV; 1342 1343 return amdgpu_show_reset_mask(buf, adev->vcn.supported_reset); 1344 } 1345 1346 static DEVICE_ATTR(vcn_reset_mask, 0444, 1347 amdgpu_get_vcn_reset_mask, NULL); 1348 1349 int amdgpu_vcn_sysfs_reset_mask_init(struct amdgpu_device *adev) 1350 { 1351 int r = 0; 1352 1353 if (adev->vcn.num_vcn_inst) { 1354 r = device_create_file(adev->dev, &dev_attr_vcn_reset_mask); 1355 if (r) 1356 return r; 1357 } 1358 1359 return r; 1360 } 1361 1362 void amdgpu_vcn_sysfs_reset_mask_fini(struct amdgpu_device *adev) 1363 { 1364 if (adev->dev->kobj.sd) { 1365 if (adev->vcn.num_vcn_inst) 1366 device_remove_file(adev->dev, &dev_attr_vcn_reset_mask); 1367 } 1368 } 1369 1370 /* 1371 * debugfs to enable/disable vcn job submission to specific core or 1372 * instance. It is created only if the queue type is unified. 1373 */ 1374 #if defined(CONFIG_DEBUG_FS) 1375 static int amdgpu_debugfs_vcn_sched_mask_set(void *data, u64 val) 1376 { 1377 struct amdgpu_device *adev = (struct amdgpu_device *)data; 1378 u32 i; 1379 u64 mask; 1380 struct amdgpu_ring *ring; 1381 1382 if (!adev) 1383 return -ENODEV; 1384 1385 mask = (1ULL << adev->vcn.num_vcn_inst) - 1; 1386 if ((val & mask) == 0) 1387 return -EINVAL; 1388 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1389 ring = &adev->vcn.inst[i].ring_enc[0]; 1390 if (val & (1ULL << i)) 1391 ring->sched.ready = true; 1392 else 1393 ring->sched.ready = false; 1394 } 1395 /* publish sched.ready flag update effective immediately across smp */ 1396 smp_rmb(); 1397 return 0; 1398 } 1399 1400 static int amdgpu_debugfs_vcn_sched_mask_get(void *data, u64 *val) 1401 { 1402 struct amdgpu_device *adev = (struct amdgpu_device *)data; 1403 u32 i; 1404 u64 mask = 0; 1405 struct amdgpu_ring *ring; 1406 1407 if (!adev) 1408 return -ENODEV; 1409 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1410 ring = &adev->vcn.inst[i].ring_enc[0]; 1411 if (ring->sched.ready) 1412 mask |= 1ULL << i; 1413 } 1414 *val = mask; 1415 return 0; 1416 } 1417 1418 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_vcn_sched_mask_fops, 1419 amdgpu_debugfs_vcn_sched_mask_get, 1420 amdgpu_debugfs_vcn_sched_mask_set, "%llx\n"); 1421 #endif 1422 1423 void amdgpu_debugfs_vcn_sched_mask_init(struct amdgpu_device *adev) 1424 { 1425 #if defined(CONFIG_DEBUG_FS) 1426 struct drm_minor *minor = adev_to_drm(adev)->primary; 1427 struct dentry *root = minor->debugfs_root; 1428 char name[32]; 1429 1430 if (adev->vcn.num_vcn_inst <= 1 || !adev->vcn.inst[0].using_unified_queue) 1431 return; 1432 sprintf(name, "amdgpu_vcn_sched_mask"); 1433 debugfs_create_file(name, 0600, root, adev, 1434 &amdgpu_debugfs_vcn_sched_mask_fops); 1435 #endif 1436 } 1437 1438 /** 1439 * vcn_set_powergating_state - set VCN block powergating state 1440 * 1441 * @ip_block: amdgpu_ip_block pointer 1442 * @state: power gating state 1443 * 1444 * Set VCN block powergating state 1445 */ 1446 int vcn_set_powergating_state(struct amdgpu_ip_block *ip_block, 1447 enum amd_powergating_state state) 1448 { 1449 struct amdgpu_device *adev = ip_block->adev; 1450 int ret = 0, i; 1451 1452 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1453 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1454 1455 ret |= vinst->set_pg_state(vinst, state); 1456 } 1457 1458 return ret; 1459 } 1460 1461 /** 1462 * amdgpu_vcn_reset_engine - Reset a specific VCN engine 1463 * @adev: Pointer to the AMDGPU device 1464 * @instance_id: VCN engine instance to reset 1465 * 1466 * Returns: 0 on success, or a negative error code on failure. 1467 */ 1468 static int amdgpu_vcn_reset_engine(struct amdgpu_device *adev, 1469 uint32_t instance_id) 1470 { 1471 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[instance_id]; 1472 int r, i; 1473 1474 mutex_lock(&vinst->engine_reset_mutex); 1475 /* Stop the scheduler's work queue for the dec and enc rings if they are running. 1476 * This ensures that no new tasks are submitted to the queues while 1477 * the reset is in progress. 1478 */ 1479 drm_sched_wqueue_stop(&vinst->ring_dec.sched); 1480 for (i = 0; i < vinst->num_enc_rings; i++) 1481 drm_sched_wqueue_stop(&vinst->ring_enc[i].sched); 1482 1483 /* Perform the VCN reset for the specified instance */ 1484 r = vinst->reset(vinst); 1485 if (r) 1486 goto unlock; 1487 r = amdgpu_ring_test_ring(&vinst->ring_dec); 1488 if (r) 1489 goto unlock; 1490 for (i = 0; i < vinst->num_enc_rings; i++) { 1491 r = amdgpu_ring_test_ring(&vinst->ring_enc[i]); 1492 if (r) 1493 goto unlock; 1494 } 1495 amdgpu_fence_driver_force_completion(&vinst->ring_dec); 1496 for (i = 0; i < vinst->num_enc_rings; i++) 1497 amdgpu_fence_driver_force_completion(&vinst->ring_enc[i]); 1498 1499 /* Restart the scheduler's work queue for the dec and enc rings 1500 * if they were stopped by this function. This allows new tasks 1501 * to be submitted to the queues after the reset is complete. 1502 */ 1503 drm_sched_wqueue_start(&vinst->ring_dec.sched); 1504 for (i = 0; i < vinst->num_enc_rings; i++) 1505 drm_sched_wqueue_start(&vinst->ring_enc[i].sched); 1506 1507 unlock: 1508 mutex_unlock(&vinst->engine_reset_mutex); 1509 1510 return r; 1511 } 1512 1513 /** 1514 * amdgpu_vcn_ring_reset - Reset a VCN ring 1515 * @ring: ring to reset 1516 * @vmid: vmid of guilty job 1517 * @timedout_fence: fence of timed out job 1518 * 1519 * This helper is for VCN blocks without unified queues because 1520 * resetting the engine resets all queues in that case. With 1521 * unified queues we have one queue per engine. 1522 * Returns: 0 on success, or a negative error code on failure. 1523 */ 1524 int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring, 1525 unsigned int vmid, 1526 struct amdgpu_fence *timedout_fence) 1527 { 1528 struct amdgpu_device *adev = ring->adev; 1529 1530 if (adev->vcn.inst[ring->me].using_unified_queue) 1531 return -EINVAL; 1532 1533 return amdgpu_vcn_reset_engine(adev, ring->me); 1534 } 1535 1536 int amdgpu_vcn_reg_dump_init(struct amdgpu_device *adev, 1537 const struct amdgpu_hwip_reg_entry *reg, u32 count) 1538 { 1539 adev->vcn.ip_dump = kcalloc(adev->vcn.num_vcn_inst * count, 1540 sizeof(uint32_t), GFP_KERNEL); 1541 if (!adev->vcn.ip_dump) 1542 return -ENOMEM; 1543 adev->vcn.reg_list = reg; 1544 adev->vcn.reg_count = count; 1545 1546 return 0; 1547 } 1548 1549 static void amdgpu_vcn_reg_dump_fini(struct amdgpu_device *adev) 1550 { 1551 kfree(adev->vcn.ip_dump); 1552 adev->vcn.ip_dump = NULL; 1553 adev->vcn.reg_list = NULL; 1554 adev->vcn.reg_count = 0; 1555 } 1556 1557 void amdgpu_vcn_dump_ip_state(struct amdgpu_ip_block *ip_block) 1558 { 1559 struct amdgpu_device *adev = ip_block->adev; 1560 int i, j; 1561 bool is_powered; 1562 u32 inst_off; 1563 1564 if (!adev->vcn.ip_dump) 1565 return; 1566 1567 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1568 if (adev->vcn.harvest_config & (1 << i)) 1569 continue; 1570 1571 inst_off = i * adev->vcn.reg_count; 1572 /* mmUVD_POWER_STATUS is always readable and is the first in reg_list */ 1573 adev->vcn.ip_dump[inst_off] = 1574 RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->vcn.reg_list[0], i)); 1575 is_powered = (adev->vcn.ip_dump[inst_off] & 1576 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF) != 1577 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 1578 1579 if (is_powered) 1580 for (j = 1; j < adev->vcn.reg_count; j++) 1581 adev->vcn.ip_dump[inst_off + j] = 1582 RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->vcn.reg_list[j], i)); 1583 } 1584 } 1585 1586 void amdgpu_vcn_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1587 { 1588 struct amdgpu_device *adev = ip_block->adev; 1589 int i, j; 1590 bool is_powered; 1591 u32 inst_off; 1592 1593 if (!adev->vcn.ip_dump) 1594 return; 1595 1596 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 1597 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1598 if (adev->vcn.harvest_config & (1 << i)) { 1599 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 1600 continue; 1601 } 1602 1603 inst_off = i * adev->vcn.reg_count; 1604 is_powered = (adev->vcn.ip_dump[inst_off] & 1605 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF) != 1606 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 1607 1608 if (is_powered) { 1609 drm_printf(p, "\nActive Instance:VCN%d\n", i); 1610 for (j = 0; j < adev->vcn.reg_count; j++) 1611 drm_printf(p, "%-50s \t 0x%08x\n", adev->vcn.reg_list[j].reg_name, 1612 adev->vcn.ip_dump[inst_off + j]); 1613 } else { 1614 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 1615 } 1616 } 1617 } 1618