1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/dmi.h> 30 #include <linux/pci.h> 31 #include <linux/debugfs.h> 32 #include <drm/drm_drv.h> 33 34 #include "amdgpu.h" 35 #include "amdgpu_pm.h" 36 #include "amdgpu_vcn.h" 37 #include "soc15d.h" 38 39 /* Firmware Names */ 40 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 41 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 42 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 43 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 44 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 45 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 46 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 47 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 48 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 49 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 50 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 51 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 52 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 53 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 54 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 55 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 56 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin" 57 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin" 58 #define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin" 59 #define FIRMWARE_VCN4_0_3 "amdgpu/vcn_4_0_3.bin" 60 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin" 61 #define FIRMWARE_VCN4_0_5 "amdgpu/vcn_4_0_5.bin" 62 #define FIRMWARE_VCN4_0_6 "amdgpu/vcn_4_0_6.bin" 63 #define FIRMWARE_VCN4_0_6_1 "amdgpu/vcn_4_0_6_1.bin" 64 #define FIRMWARE_VCN5_0_0 "amdgpu/vcn_5_0_0.bin" 65 66 MODULE_FIRMWARE(FIRMWARE_RAVEN); 67 MODULE_FIRMWARE(FIRMWARE_PICASSO); 68 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 69 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 70 MODULE_FIRMWARE(FIRMWARE_RENOIR); 71 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 72 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 73 MODULE_FIRMWARE(FIRMWARE_NAVI10); 74 MODULE_FIRMWARE(FIRMWARE_NAVI14); 75 MODULE_FIRMWARE(FIRMWARE_NAVI12); 76 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 77 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 78 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 79 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 80 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 81 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 82 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2); 83 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0); 84 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2); 85 MODULE_FIRMWARE(FIRMWARE_VCN4_0_3); 86 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4); 87 MODULE_FIRMWARE(FIRMWARE_VCN4_0_5); 88 MODULE_FIRMWARE(FIRMWARE_VCN4_0_6); 89 MODULE_FIRMWARE(FIRMWARE_VCN4_0_6_1); 90 MODULE_FIRMWARE(FIRMWARE_VCN5_0_0); 91 92 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 93 94 int amdgpu_vcn_early_init(struct amdgpu_device *adev) 95 { 96 char ucode_prefix[25]; 97 char fw_name[40]; 98 int r, i; 99 100 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 101 amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix)); 102 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); 103 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6) && 104 i == 1) { 105 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_%d.bin", ucode_prefix, i); 106 } 107 108 r = amdgpu_ucode_request(adev, &adev->vcn.fw[i], fw_name); 109 if (r) { 110 amdgpu_ucode_release(&adev->vcn.fw[i]); 111 return r; 112 } 113 } 114 return r; 115 } 116 117 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 118 { 119 unsigned long bo_size; 120 const struct common_firmware_header *hdr; 121 unsigned char fw_check; 122 unsigned int fw_shared_size, log_offset; 123 int i, r; 124 125 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 126 mutex_init(&adev->vcn.vcn_pg_lock); 127 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 128 atomic_set(&adev->vcn.total_submission_cnt, 0); 129 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 130 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 131 132 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 133 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 134 adev->vcn.indirect_sram = true; 135 136 /* 137 * Some Steam Deck's BIOS versions are incompatible with the 138 * indirect SRAM mode, leading to amdgpu being unable to get 139 * properly probed (and even potentially crashing the kernel). 140 * Hence, check for these versions here - notice this is 141 * restricted to Vangogh (Deck's APU). 142 */ 143 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 0, 2)) { 144 const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION); 145 146 if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) || 147 !strncmp("F7A0114", bios_ver, 7))) { 148 adev->vcn.indirect_sram = false; 149 dev_info(adev->dev, 150 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver); 151 } 152 } 153 154 hdr = (const struct common_firmware_header *)adev->vcn.fw[0]->data; 155 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 156 157 /* Bit 20-23, it is encode major and non-zero for new naming convention. 158 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 159 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 160 * is zero in old naming convention, this field is always zero so far. 161 * These four bits are used to tell which naming convention is present. 162 */ 163 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 164 if (fw_check) { 165 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 166 167 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 168 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 169 enc_major = fw_check; 170 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 171 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 172 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 173 enc_major, enc_minor, dec_ver, vep, fw_rev); 174 } else { 175 unsigned int version_major, version_minor, family_id; 176 177 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 178 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 179 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 180 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 181 version_major, version_minor, family_id); 182 } 183 184 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 185 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 186 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 187 188 if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(5, 0, 0)) { 189 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)); 190 log_offset = offsetof(struct amdgpu_vcn5_fw_shared, fw_log); 191 } else if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) { 192 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); 193 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log); 194 } else { 195 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 196 log_offset = offsetof(struct amdgpu_fw_shared, fw_log); 197 } 198 199 bo_size += fw_shared_size; 200 201 if (amdgpu_vcnfw_log) 202 bo_size += AMDGPU_VCNFW_LOG_SIZE; 203 204 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 205 if (adev->vcn.harvest_config & (1 << i)) 206 continue; 207 208 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 209 AMDGPU_GEM_DOMAIN_VRAM | 210 AMDGPU_GEM_DOMAIN_GTT, 211 &adev->vcn.inst[i].vcpu_bo, 212 &adev->vcn.inst[i].gpu_addr, 213 &adev->vcn.inst[i].cpu_addr); 214 if (r) { 215 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 216 return r; 217 } 218 219 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr + 220 bo_size - fw_shared_size; 221 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr + 222 bo_size - fw_shared_size; 223 224 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size; 225 226 if (amdgpu_vcnfw_log) { 227 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 228 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 229 adev->vcn.inst[i].fw_shared.log_offset = log_offset; 230 } 231 232 if (adev->vcn.indirect_sram) { 233 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 234 AMDGPU_GEM_DOMAIN_VRAM | 235 AMDGPU_GEM_DOMAIN_GTT, 236 &adev->vcn.inst[i].dpg_sram_bo, 237 &adev->vcn.inst[i].dpg_sram_gpu_addr, 238 &adev->vcn.inst[i].dpg_sram_cpu_addr); 239 if (r) { 240 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 241 return r; 242 } 243 } 244 } 245 246 return 0; 247 } 248 249 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 250 { 251 int i, j; 252 253 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 254 if (adev->vcn.harvest_config & (1 << j)) 255 continue; 256 257 amdgpu_bo_free_kernel( 258 &adev->vcn.inst[j].dpg_sram_bo, 259 &adev->vcn.inst[j].dpg_sram_gpu_addr, 260 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 261 262 kvfree(adev->vcn.inst[j].saved_bo); 263 264 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 265 &adev->vcn.inst[j].gpu_addr, 266 (void **)&adev->vcn.inst[j].cpu_addr); 267 268 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 269 270 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 271 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 272 273 amdgpu_ucode_release(&adev->vcn.fw[j]); 274 } 275 276 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 277 mutex_destroy(&adev->vcn.vcn_pg_lock); 278 279 return 0; 280 } 281 282 /* from vcn4 and above, only unified queue is used */ 283 static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring) 284 { 285 struct amdgpu_device *adev = ring->adev; 286 bool ret = false; 287 288 if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) 289 ret = true; 290 291 return ret; 292 } 293 294 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 295 { 296 bool ret = false; 297 int vcn_config = adev->vcn.vcn_config[vcn_instance]; 298 299 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) 300 ret = true; 301 else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) 302 ret = true; 303 else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) 304 ret = true; 305 306 return ret; 307 } 308 309 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 310 { 311 unsigned int size; 312 void *ptr; 313 int i, idx; 314 315 bool in_ras_intr = amdgpu_ras_intr_triggered(); 316 317 cancel_delayed_work_sync(&adev->vcn.idle_work); 318 319 /* err_event_athub will corrupt VCPU buffer, so we need to 320 * restore fw data and clear buffer in amdgpu_vcn_resume() */ 321 if (in_ras_intr) 322 return 0; 323 324 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 325 if (adev->vcn.harvest_config & (1 << i)) 326 continue; 327 if (adev->vcn.inst[i].vcpu_bo == NULL) 328 return 0; 329 330 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 331 ptr = adev->vcn.inst[i].cpu_addr; 332 333 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 334 if (!adev->vcn.inst[i].saved_bo) 335 return -ENOMEM; 336 337 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 338 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 339 drm_dev_exit(idx); 340 } 341 } 342 return 0; 343 } 344 345 int amdgpu_vcn_resume(struct amdgpu_device *adev) 346 { 347 unsigned int size; 348 void *ptr; 349 int i, idx; 350 351 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 352 if (adev->vcn.harvest_config & (1 << i)) 353 continue; 354 if (adev->vcn.inst[i].vcpu_bo == NULL) 355 return -EINVAL; 356 357 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 358 ptr = adev->vcn.inst[i].cpu_addr; 359 360 if (adev->vcn.inst[i].saved_bo != NULL) { 361 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 362 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 363 drm_dev_exit(idx); 364 } 365 kvfree(adev->vcn.inst[i].saved_bo); 366 adev->vcn.inst[i].saved_bo = NULL; 367 } else { 368 const struct common_firmware_header *hdr; 369 unsigned int offset; 370 371 hdr = (const struct common_firmware_header *)adev->vcn.fw[i]->data; 372 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 373 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 374 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 375 memcpy_toio(adev->vcn.inst[i].cpu_addr, 376 adev->vcn.fw[i]->data + offset, 377 le32_to_cpu(hdr->ucode_size_bytes)); 378 drm_dev_exit(idx); 379 } 380 size -= le32_to_cpu(hdr->ucode_size_bytes); 381 ptr += le32_to_cpu(hdr->ucode_size_bytes); 382 } 383 memset_io(ptr, 0, size); 384 } 385 } 386 return 0; 387 } 388 389 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 390 { 391 struct amdgpu_device *adev = 392 container_of(work, struct amdgpu_device, vcn.idle_work.work); 393 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 394 unsigned int i, j; 395 int r = 0; 396 397 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 398 if (adev->vcn.harvest_config & (1 << j)) 399 continue; 400 401 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 402 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 403 404 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 405 struct dpg_pause_state new_state; 406 407 if (fence[j] || 408 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 409 new_state.fw_based = VCN_DPG_STATE__PAUSE; 410 else 411 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 412 413 adev->vcn.pause_dpg_mode(adev, j, &new_state); 414 } 415 416 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 417 fences += fence[j]; 418 } 419 420 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 421 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 422 AMD_PG_STATE_GATE); 423 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 424 false); 425 if (r) 426 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 427 } else { 428 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 429 } 430 } 431 432 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 433 { 434 struct amdgpu_device *adev = ring->adev; 435 int r = 0; 436 437 atomic_inc(&adev->vcn.total_submission_cnt); 438 439 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 440 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 441 true); 442 if (r) 443 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 444 } 445 446 mutex_lock(&adev->vcn.vcn_pg_lock); 447 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 448 AMD_PG_STATE_UNGATE); 449 450 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 451 struct dpg_pause_state new_state; 452 453 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 454 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 455 new_state.fw_based = VCN_DPG_STATE__PAUSE; 456 } else { 457 unsigned int fences = 0; 458 unsigned int i; 459 460 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 461 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 462 463 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 464 new_state.fw_based = VCN_DPG_STATE__PAUSE; 465 else 466 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 467 } 468 469 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 470 } 471 mutex_unlock(&adev->vcn.vcn_pg_lock); 472 } 473 474 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 475 { 476 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 477 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 478 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 479 480 atomic_dec(&ring->adev->vcn.total_submission_cnt); 481 482 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 483 } 484 485 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 486 { 487 struct amdgpu_device *adev = ring->adev; 488 uint32_t tmp = 0; 489 unsigned int i; 490 int r; 491 492 /* VCN in SRIOV does not support direct register read/write */ 493 if (amdgpu_sriov_vf(adev)) 494 return 0; 495 496 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 497 r = amdgpu_ring_alloc(ring, 3); 498 if (r) 499 return r; 500 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 501 amdgpu_ring_write(ring, 0xDEADBEEF); 502 amdgpu_ring_commit(ring); 503 for (i = 0; i < adev->usec_timeout; i++) { 504 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 505 if (tmp == 0xDEADBEEF) 506 break; 507 udelay(1); 508 } 509 510 if (i >= adev->usec_timeout) 511 r = -ETIMEDOUT; 512 513 return r; 514 } 515 516 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 517 { 518 struct amdgpu_device *adev = ring->adev; 519 uint32_t rptr; 520 unsigned int i; 521 int r; 522 523 if (amdgpu_sriov_vf(adev)) 524 return 0; 525 526 r = amdgpu_ring_alloc(ring, 16); 527 if (r) 528 return r; 529 530 rptr = amdgpu_ring_get_rptr(ring); 531 532 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 533 amdgpu_ring_commit(ring); 534 535 for (i = 0; i < adev->usec_timeout; i++) { 536 if (amdgpu_ring_get_rptr(ring) != rptr) 537 break; 538 udelay(1); 539 } 540 541 if (i >= adev->usec_timeout) 542 r = -ETIMEDOUT; 543 544 return r; 545 } 546 547 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 548 struct amdgpu_ib *ib_msg, 549 struct dma_fence **fence) 550 { 551 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 552 struct amdgpu_device *adev = ring->adev; 553 struct dma_fence *f = NULL; 554 struct amdgpu_job *job; 555 struct amdgpu_ib *ib; 556 int i, r; 557 558 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 559 64, AMDGPU_IB_POOL_DIRECT, 560 &job); 561 if (r) 562 goto err; 563 564 ib = &job->ibs[0]; 565 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 566 ib->ptr[1] = addr; 567 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 568 ib->ptr[3] = addr >> 32; 569 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 570 ib->ptr[5] = 0; 571 for (i = 6; i < 16; i += 2) { 572 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 573 ib->ptr[i+1] = 0; 574 } 575 ib->length_dw = 16; 576 577 r = amdgpu_job_submit_direct(job, ring, &f); 578 if (r) 579 goto err_free; 580 581 amdgpu_ib_free(adev, ib_msg, f); 582 583 if (fence) 584 *fence = dma_fence_get(f); 585 dma_fence_put(f); 586 587 return 0; 588 589 err_free: 590 amdgpu_job_free(job); 591 err: 592 amdgpu_ib_free(adev, ib_msg, f); 593 return r; 594 } 595 596 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 597 struct amdgpu_ib *ib) 598 { 599 struct amdgpu_device *adev = ring->adev; 600 uint32_t *msg; 601 int r, i; 602 603 memset(ib, 0, sizeof(*ib)); 604 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 605 AMDGPU_IB_POOL_DIRECT, 606 ib); 607 if (r) 608 return r; 609 610 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 611 msg[0] = cpu_to_le32(0x00000028); 612 msg[1] = cpu_to_le32(0x00000038); 613 msg[2] = cpu_to_le32(0x00000001); 614 msg[3] = cpu_to_le32(0x00000000); 615 msg[4] = cpu_to_le32(handle); 616 msg[5] = cpu_to_le32(0x00000000); 617 msg[6] = cpu_to_le32(0x00000001); 618 msg[7] = cpu_to_le32(0x00000028); 619 msg[8] = cpu_to_le32(0x00000010); 620 msg[9] = cpu_to_le32(0x00000000); 621 msg[10] = cpu_to_le32(0x00000007); 622 msg[11] = cpu_to_le32(0x00000000); 623 msg[12] = cpu_to_le32(0x00000780); 624 msg[13] = cpu_to_le32(0x00000440); 625 for (i = 14; i < 1024; ++i) 626 msg[i] = cpu_to_le32(0x0); 627 628 return 0; 629 } 630 631 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 632 struct amdgpu_ib *ib) 633 { 634 struct amdgpu_device *adev = ring->adev; 635 uint32_t *msg; 636 int r, i; 637 638 memset(ib, 0, sizeof(*ib)); 639 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 640 AMDGPU_IB_POOL_DIRECT, 641 ib); 642 if (r) 643 return r; 644 645 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 646 msg[0] = cpu_to_le32(0x00000028); 647 msg[1] = cpu_to_le32(0x00000018); 648 msg[2] = cpu_to_le32(0x00000000); 649 msg[3] = cpu_to_le32(0x00000002); 650 msg[4] = cpu_to_le32(handle); 651 msg[5] = cpu_to_le32(0x00000000); 652 for (i = 6; i < 1024; ++i) 653 msg[i] = cpu_to_le32(0x0); 654 655 return 0; 656 } 657 658 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 659 { 660 struct dma_fence *fence = NULL; 661 struct amdgpu_ib ib; 662 long r; 663 664 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 665 if (r) 666 goto error; 667 668 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 669 if (r) 670 goto error; 671 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 672 if (r) 673 goto error; 674 675 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 676 if (r) 677 goto error; 678 679 r = dma_fence_wait_timeout(fence, false, timeout); 680 if (r == 0) 681 r = -ETIMEDOUT; 682 else if (r > 0) 683 r = 0; 684 685 dma_fence_put(fence); 686 error: 687 return r; 688 } 689 690 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, 691 uint32_t ib_pack_in_dw, bool enc) 692 { 693 uint32_t *ib_checksum; 694 695 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */ 696 ib->ptr[ib->length_dw++] = 0x30000002; 697 ib_checksum = &ib->ptr[ib->length_dw++]; 698 ib->ptr[ib->length_dw++] = ib_pack_in_dw; 699 700 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */ 701 ib->ptr[ib->length_dw++] = 0x30000001; 702 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3; 703 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t); 704 705 return ib_checksum; 706 } 707 708 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum, 709 uint32_t ib_pack_in_dw) 710 { 711 uint32_t i; 712 uint32_t checksum = 0; 713 714 for (i = 0; i < ib_pack_in_dw; i++) 715 checksum += *(*ib_checksum + 2 + i); 716 717 **ib_checksum = checksum; 718 } 719 720 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 721 struct amdgpu_ib *ib_msg, 722 struct dma_fence **fence) 723 { 724 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 725 unsigned int ib_size_dw = 64; 726 struct amdgpu_device *adev = ring->adev; 727 struct dma_fence *f = NULL; 728 struct amdgpu_job *job; 729 struct amdgpu_ib *ib; 730 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 731 bool sq = amdgpu_vcn_using_unified_queue(ring); 732 uint32_t *ib_checksum; 733 uint32_t ib_pack_in_dw; 734 int i, r; 735 736 if (sq) 737 ib_size_dw += 8; 738 739 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 740 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 741 &job); 742 if (r) 743 goto err; 744 745 ib = &job->ibs[0]; 746 ib->length_dw = 0; 747 748 /* single queue headers */ 749 if (sq) { 750 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t) 751 + 4 + 2; /* engine info + decoding ib in dw */ 752 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false); 753 } 754 755 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 756 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 757 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 758 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 759 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 760 761 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 762 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 763 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 764 765 for (i = ib->length_dw; i < ib_size_dw; ++i) 766 ib->ptr[i] = 0x0; 767 768 if (sq) 769 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw); 770 771 r = amdgpu_job_submit_direct(job, ring, &f); 772 if (r) 773 goto err_free; 774 775 amdgpu_ib_free(adev, ib_msg, f); 776 777 if (fence) 778 *fence = dma_fence_get(f); 779 dma_fence_put(f); 780 781 return 0; 782 783 err_free: 784 amdgpu_job_free(job); 785 err: 786 amdgpu_ib_free(adev, ib_msg, f); 787 return r; 788 } 789 790 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 791 { 792 struct dma_fence *fence = NULL; 793 struct amdgpu_ib ib; 794 long r; 795 796 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 797 if (r) 798 goto error; 799 800 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 801 if (r) 802 goto error; 803 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 804 if (r) 805 goto error; 806 807 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 808 if (r) 809 goto error; 810 811 r = dma_fence_wait_timeout(fence, false, timeout); 812 if (r == 0) 813 r = -ETIMEDOUT; 814 else if (r > 0) 815 r = 0; 816 817 dma_fence_put(fence); 818 error: 819 return r; 820 } 821 822 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 823 { 824 struct amdgpu_device *adev = ring->adev; 825 uint32_t rptr; 826 unsigned int i; 827 int r; 828 829 if (amdgpu_sriov_vf(adev)) 830 return 0; 831 832 r = amdgpu_ring_alloc(ring, 16); 833 if (r) 834 return r; 835 836 rptr = amdgpu_ring_get_rptr(ring); 837 838 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 839 amdgpu_ring_commit(ring); 840 841 for (i = 0; i < adev->usec_timeout; i++) { 842 if (amdgpu_ring_get_rptr(ring) != rptr) 843 break; 844 udelay(1); 845 } 846 847 if (i >= adev->usec_timeout) 848 r = -ETIMEDOUT; 849 850 return r; 851 } 852 853 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 854 struct amdgpu_ib *ib_msg, 855 struct dma_fence **fence) 856 { 857 unsigned int ib_size_dw = 16; 858 struct amdgpu_job *job; 859 struct amdgpu_ib *ib; 860 struct dma_fence *f = NULL; 861 uint32_t *ib_checksum = NULL; 862 uint64_t addr; 863 bool sq = amdgpu_vcn_using_unified_queue(ring); 864 int i, r; 865 866 if (sq) 867 ib_size_dw += 8; 868 869 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 870 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 871 &job); 872 if (r) 873 return r; 874 875 ib = &job->ibs[0]; 876 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 877 878 ib->length_dw = 0; 879 880 if (sq) 881 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 882 883 ib->ptr[ib->length_dw++] = 0x00000018; 884 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 885 ib->ptr[ib->length_dw++] = handle; 886 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 887 ib->ptr[ib->length_dw++] = addr; 888 ib->ptr[ib->length_dw++] = 0x0000000b; 889 890 ib->ptr[ib->length_dw++] = 0x00000014; 891 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 892 ib->ptr[ib->length_dw++] = 0x0000001c; 893 ib->ptr[ib->length_dw++] = 0x00000000; 894 ib->ptr[ib->length_dw++] = 0x00000000; 895 896 ib->ptr[ib->length_dw++] = 0x00000008; 897 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 898 899 for (i = ib->length_dw; i < ib_size_dw; ++i) 900 ib->ptr[i] = 0x0; 901 902 if (sq) 903 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 904 905 r = amdgpu_job_submit_direct(job, ring, &f); 906 if (r) 907 goto err; 908 909 if (fence) 910 *fence = dma_fence_get(f); 911 dma_fence_put(f); 912 913 return 0; 914 915 err: 916 amdgpu_job_free(job); 917 return r; 918 } 919 920 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 921 struct amdgpu_ib *ib_msg, 922 struct dma_fence **fence) 923 { 924 unsigned int ib_size_dw = 16; 925 struct amdgpu_job *job; 926 struct amdgpu_ib *ib; 927 struct dma_fence *f = NULL; 928 uint32_t *ib_checksum = NULL; 929 uint64_t addr; 930 bool sq = amdgpu_vcn_using_unified_queue(ring); 931 int i, r; 932 933 if (sq) 934 ib_size_dw += 8; 935 936 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 937 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 938 &job); 939 if (r) 940 return r; 941 942 ib = &job->ibs[0]; 943 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 944 945 ib->length_dw = 0; 946 947 if (sq) 948 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 949 950 ib->ptr[ib->length_dw++] = 0x00000018; 951 ib->ptr[ib->length_dw++] = 0x00000001; 952 ib->ptr[ib->length_dw++] = handle; 953 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 954 ib->ptr[ib->length_dw++] = addr; 955 ib->ptr[ib->length_dw++] = 0x0000000b; 956 957 ib->ptr[ib->length_dw++] = 0x00000014; 958 ib->ptr[ib->length_dw++] = 0x00000002; 959 ib->ptr[ib->length_dw++] = 0x0000001c; 960 ib->ptr[ib->length_dw++] = 0x00000000; 961 ib->ptr[ib->length_dw++] = 0x00000000; 962 963 ib->ptr[ib->length_dw++] = 0x00000008; 964 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 965 966 for (i = ib->length_dw; i < ib_size_dw; ++i) 967 ib->ptr[i] = 0x0; 968 969 if (sq) 970 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 971 972 r = amdgpu_job_submit_direct(job, ring, &f); 973 if (r) 974 goto err; 975 976 if (fence) 977 *fence = dma_fence_get(f); 978 dma_fence_put(f); 979 980 return 0; 981 982 err: 983 amdgpu_job_free(job); 984 return r; 985 } 986 987 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 988 { 989 struct amdgpu_device *adev = ring->adev; 990 struct dma_fence *fence = NULL; 991 struct amdgpu_ib ib; 992 long r; 993 994 memset(&ib, 0, sizeof(ib)); 995 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 996 AMDGPU_IB_POOL_DIRECT, 997 &ib); 998 if (r) 999 return r; 1000 1001 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 1002 if (r) 1003 goto error; 1004 1005 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 1006 if (r) 1007 goto error; 1008 1009 r = dma_fence_wait_timeout(fence, false, timeout); 1010 if (r == 0) 1011 r = -ETIMEDOUT; 1012 else if (r > 0) 1013 r = 0; 1014 1015 error: 1016 amdgpu_ib_free(adev, &ib, fence); 1017 dma_fence_put(fence); 1018 1019 return r; 1020 } 1021 1022 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1023 { 1024 struct amdgpu_device *adev = ring->adev; 1025 long r; 1026 1027 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(4, 0, 3)) { 1028 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout); 1029 if (r) 1030 goto error; 1031 } 1032 1033 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout); 1034 1035 error: 1036 return r; 1037 } 1038 1039 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 1040 { 1041 switch (ring) { 1042 case 0: 1043 return AMDGPU_RING_PRIO_0; 1044 case 1: 1045 return AMDGPU_RING_PRIO_1; 1046 case 2: 1047 return AMDGPU_RING_PRIO_2; 1048 default: 1049 return AMDGPU_RING_PRIO_0; 1050 } 1051 } 1052 1053 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev) 1054 { 1055 int i; 1056 unsigned int idx; 1057 1058 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1059 const struct common_firmware_header *hdr; 1060 1061 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1062 if (adev->vcn.harvest_config & (1 << i)) 1063 continue; 1064 1065 hdr = (const struct common_firmware_header *)adev->vcn.fw[i]->data; 1066 /* currently only support 2 FW instances */ 1067 if (i >= 2) { 1068 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 1069 break; 1070 } 1071 idx = AMDGPU_UCODE_ID_VCN + i; 1072 adev->firmware.ucode[idx].ucode_id = idx; 1073 adev->firmware.ucode[idx].fw = adev->vcn.fw[i]; 1074 adev->firmware.fw_size += 1075 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 1076 1077 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == 1078 IP_VERSION(4, 0, 3)) 1079 break; 1080 } 1081 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 1082 } 1083 } 1084 1085 /* 1086 * debugfs for mapping vcn firmware log buffer. 1087 */ 1088 #if defined(CONFIG_DEBUG_FS) 1089 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf, 1090 size_t size, loff_t *pos) 1091 { 1092 struct amdgpu_vcn_inst *vcn; 1093 void *log_buf; 1094 volatile struct amdgpu_vcn_fwlog *plog; 1095 unsigned int read_pos, write_pos, available, i, read_bytes = 0; 1096 unsigned int read_num[2] = {0}; 1097 1098 vcn = file_inode(f)->i_private; 1099 if (!vcn) 1100 return -ENODEV; 1101 1102 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log) 1103 return -EFAULT; 1104 1105 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1106 1107 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf; 1108 read_pos = plog->rptr; 1109 write_pos = plog->wptr; 1110 1111 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE) 1112 return -EFAULT; 1113 1114 if (!size || (read_pos == write_pos)) 1115 return 0; 1116 1117 if (write_pos > read_pos) { 1118 available = write_pos - read_pos; 1119 read_num[0] = min_t(size_t, size, available); 1120 } else { 1121 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos; 1122 available = read_num[0] + write_pos - plog->header_size; 1123 if (size > available) 1124 read_num[1] = write_pos - plog->header_size; 1125 else if (size > read_num[0]) 1126 read_num[1] = size - read_num[0]; 1127 else 1128 read_num[0] = size; 1129 } 1130 1131 for (i = 0; i < 2; i++) { 1132 if (read_num[i]) { 1133 if (read_pos == AMDGPU_VCNFW_LOG_SIZE) 1134 read_pos = plog->header_size; 1135 if (read_num[i] == copy_to_user((buf + read_bytes), 1136 (log_buf + read_pos), read_num[i])) 1137 return -EFAULT; 1138 1139 read_bytes += read_num[i]; 1140 read_pos += read_num[i]; 1141 } 1142 } 1143 1144 plog->rptr = read_pos; 1145 *pos += read_bytes; 1146 return read_bytes; 1147 } 1148 1149 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = { 1150 .owner = THIS_MODULE, 1151 .read = amdgpu_debugfs_vcn_fwlog_read, 1152 .llseek = default_llseek 1153 }; 1154 #endif 1155 1156 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i, 1157 struct amdgpu_vcn_inst *vcn) 1158 { 1159 #if defined(CONFIG_DEBUG_FS) 1160 struct drm_minor *minor = adev_to_drm(adev)->primary; 1161 struct dentry *root = minor->debugfs_root; 1162 char name[32]; 1163 1164 sprintf(name, "amdgpu_vcn_%d_fwlog", i); 1165 debugfs_create_file_size(name, S_IFREG | 0444, root, vcn, 1166 &amdgpu_debugfs_vcnfwlog_fops, 1167 AMDGPU_VCNFW_LOG_SIZE); 1168 #endif 1169 } 1170 1171 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn) 1172 { 1173 #if defined(CONFIG_DEBUG_FS) 1174 volatile uint32_t *flag = vcn->fw_shared.cpu_addr; 1175 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1176 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size; 1177 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr; 1178 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr 1179 + vcn->fw_shared.log_offset; 1180 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG); 1181 fw_log->is_enabled = 1; 1182 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF); 1183 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32); 1184 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE); 1185 1186 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog); 1187 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE; 1188 log_buf->rptr = log_buf->header_size; 1189 log_buf->wptr = log_buf->header_size; 1190 log_buf->wrapped = 0; 1191 #endif 1192 } 1193 1194 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, 1195 struct amdgpu_irq_src *source, 1196 struct amdgpu_iv_entry *entry) 1197 { 1198 struct ras_common_if *ras_if = adev->vcn.ras_if; 1199 struct ras_dispatch_if ih_data = { 1200 .entry = entry, 1201 }; 1202 1203 if (!ras_if) 1204 return 0; 1205 1206 if (!amdgpu_sriov_vf(adev)) { 1207 ih_data.head = *ras_if; 1208 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 1209 } else { 1210 if (adev->virt.ops && adev->virt.ops->ras_poison_handler) 1211 adev->virt.ops->ras_poison_handler(adev, ras_if->block); 1212 else 1213 dev_warn(adev->dev, 1214 "No ras_poison_handler interface in SRIOV for VCN!\n"); 1215 } 1216 1217 return 0; 1218 } 1219 1220 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1221 { 1222 int r, i; 1223 1224 r = amdgpu_ras_block_late_init(adev, ras_block); 1225 if (r) 1226 return r; 1227 1228 if (amdgpu_ras_is_supported(adev, ras_block->block)) { 1229 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1230 if (adev->vcn.harvest_config & (1 << i) || 1231 !adev->vcn.inst[i].ras_poison_irq.funcs) 1232 continue; 1233 1234 r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0); 1235 if (r) 1236 goto late_fini; 1237 } 1238 } 1239 return 0; 1240 1241 late_fini: 1242 amdgpu_ras_block_late_fini(adev, ras_block); 1243 return r; 1244 } 1245 1246 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev) 1247 { 1248 int err; 1249 struct amdgpu_vcn_ras *ras; 1250 1251 if (!adev->vcn.ras) 1252 return 0; 1253 1254 ras = adev->vcn.ras; 1255 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 1256 if (err) { 1257 dev_err(adev->dev, "Failed to register vcn ras block!\n"); 1258 return err; 1259 } 1260 1261 strcpy(ras->ras_block.ras_comm.name, "vcn"); 1262 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; 1263 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; 1264 adev->vcn.ras_if = &ras->ras_block.ras_comm; 1265 1266 if (!ras->ras_block.ras_late_init) 1267 ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init; 1268 1269 return 0; 1270 } 1271 1272 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, 1273 enum AMDGPU_UCODE_ID ucode_id) 1274 { 1275 struct amdgpu_firmware_info ucode = { 1276 .ucode_id = (ucode_id ? ucode_id : 1277 (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 1278 AMDGPU_UCODE_ID_VCN0_RAM)), 1279 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1280 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1281 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr), 1282 }; 1283 1284 return psp_execute_ip_fw_load(&adev->psp, &ucode); 1285 } 1286