1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 34 #include <drm/drm.h> 35 #include <drm/drm_drv.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_pm.h" 39 #include "amdgpu_uvd.h" 40 #include "amdgpu_cs.h" 41 #include "cikd.h" 42 #include "uvd/uvd_4_2_d.h" 43 44 #include "amdgpu_ras.h" 45 46 /* 1 second timeout */ 47 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) 48 49 /* Firmware versions for VI */ 50 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) 51 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) 52 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) 53 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) 54 55 /* Polaris10/11 firmware version */ 56 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 57 58 /* Firmware Names */ 59 #ifdef CONFIG_DRM_AMDGPU_SI 60 #define FIRMWARE_TAHITI "amdgpu/tahiti_uvd.bin" 61 #define FIRMWARE_VERDE "amdgpu/verde_uvd.bin" 62 #define FIRMWARE_PITCAIRN "amdgpu/pitcairn_uvd.bin" 63 #define FIRMWARE_OLAND "amdgpu/oland_uvd.bin" 64 #endif 65 #ifdef CONFIG_DRM_AMDGPU_CIK 66 #define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin" 67 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin" 68 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin" 69 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin" 70 #define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin" 71 #endif 72 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 73 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 74 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 75 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 76 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 77 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 78 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" 79 #define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin" 80 81 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" 82 #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin" 83 #define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin" 84 85 /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */ 86 #define UVD_GPCOM_VCPU_CMD 0x03c3 87 #define UVD_GPCOM_VCPU_DATA0 0x03c4 88 #define UVD_GPCOM_VCPU_DATA1 0x03c5 89 #define UVD_NO_OP 0x03ff 90 #define UVD_BASE_SI 0x3800 91 92 /* 93 * amdgpu_uvd_cs_ctx - Command submission parser context 94 * 95 * Used for emulating virtual memory support on UVD 4.2. 96 */ 97 struct amdgpu_uvd_cs_ctx { 98 struct amdgpu_cs_parser *parser; 99 unsigned int reg, count; 100 unsigned int data0, data1; 101 unsigned int idx; 102 struct amdgpu_ib *ib; 103 104 /* does the IB has a msg command */ 105 bool has_msg_cmd; 106 107 /* minimum buffer sizes */ 108 unsigned int *buf_sizes; 109 }; 110 111 #ifdef CONFIG_DRM_AMDGPU_SI 112 MODULE_FIRMWARE(FIRMWARE_TAHITI); 113 MODULE_FIRMWARE(FIRMWARE_VERDE); 114 MODULE_FIRMWARE(FIRMWARE_PITCAIRN); 115 MODULE_FIRMWARE(FIRMWARE_OLAND); 116 #endif 117 #ifdef CONFIG_DRM_AMDGPU_CIK 118 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 119 MODULE_FIRMWARE(FIRMWARE_KABINI); 120 MODULE_FIRMWARE(FIRMWARE_KAVERI); 121 MODULE_FIRMWARE(FIRMWARE_HAWAII); 122 MODULE_FIRMWARE(FIRMWARE_MULLINS); 123 #endif 124 MODULE_FIRMWARE(FIRMWARE_TONGA); 125 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 126 MODULE_FIRMWARE(FIRMWARE_FIJI); 127 MODULE_FIRMWARE(FIRMWARE_STONEY); 128 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 129 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 130 MODULE_FIRMWARE(FIRMWARE_POLARIS12); 131 MODULE_FIRMWARE(FIRMWARE_VEGAM); 132 133 MODULE_FIRMWARE(FIRMWARE_VEGA10); 134 MODULE_FIRMWARE(FIRMWARE_VEGA12); 135 MODULE_FIRMWARE(FIRMWARE_VEGA20); 136 137 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 138 static void amdgpu_uvd_force_into_vcpu_segment(struct amdgpu_bo *abo); 139 140 static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev, 141 uint32_t size, 142 struct amdgpu_bo **bo_ptr) 143 { 144 struct ttm_operation_ctx ctx = { true, false }; 145 struct amdgpu_bo *bo = NULL; 146 void *addr; 147 int r; 148 149 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, 150 AMDGPU_GEM_DOMAIN_GTT, 151 &bo, NULL, &addr); 152 if (r) 153 return r; 154 155 if (adev->uvd.address_64_bit) 156 goto succ; 157 158 amdgpu_bo_kunmap(bo); 159 amdgpu_bo_unpin(bo); 160 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 161 amdgpu_uvd_force_into_vcpu_segment(bo); 162 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 163 if (r) 164 goto err; 165 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM); 166 if (r) 167 goto err_pin; 168 r = amdgpu_bo_kmap(bo, &addr); 169 if (r) 170 goto err_kmap; 171 succ: 172 amdgpu_bo_unreserve(bo); 173 *bo_ptr = bo; 174 return 0; 175 err_kmap: 176 amdgpu_bo_unpin(bo); 177 err_pin: 178 err: 179 amdgpu_bo_unreserve(bo); 180 amdgpu_bo_unref(&bo); 181 return r; 182 } 183 184 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 185 { 186 unsigned long bo_size; 187 const char *fw_name; 188 const struct common_firmware_header *hdr; 189 unsigned int family_id; 190 int i, j, r; 191 u32 vcpu_bo_domain; 192 193 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 194 195 switch (adev->asic_type) { 196 #ifdef CONFIG_DRM_AMDGPU_SI 197 case CHIP_TAHITI: 198 fw_name = FIRMWARE_TAHITI; 199 break; 200 case CHIP_VERDE: 201 fw_name = FIRMWARE_VERDE; 202 break; 203 case CHIP_PITCAIRN: 204 fw_name = FIRMWARE_PITCAIRN; 205 break; 206 case CHIP_OLAND: 207 fw_name = FIRMWARE_OLAND; 208 break; 209 #endif 210 #ifdef CONFIG_DRM_AMDGPU_CIK 211 case CHIP_BONAIRE: 212 fw_name = FIRMWARE_BONAIRE; 213 break; 214 case CHIP_KABINI: 215 fw_name = FIRMWARE_KABINI; 216 break; 217 case CHIP_KAVERI: 218 fw_name = FIRMWARE_KAVERI; 219 break; 220 case CHIP_HAWAII: 221 fw_name = FIRMWARE_HAWAII; 222 break; 223 case CHIP_MULLINS: 224 fw_name = FIRMWARE_MULLINS; 225 break; 226 #endif 227 case CHIP_TONGA: 228 fw_name = FIRMWARE_TONGA; 229 break; 230 case CHIP_FIJI: 231 fw_name = FIRMWARE_FIJI; 232 break; 233 case CHIP_CARRIZO: 234 fw_name = FIRMWARE_CARRIZO; 235 break; 236 case CHIP_STONEY: 237 fw_name = FIRMWARE_STONEY; 238 break; 239 case CHIP_POLARIS10: 240 fw_name = FIRMWARE_POLARIS10; 241 break; 242 case CHIP_POLARIS11: 243 fw_name = FIRMWARE_POLARIS11; 244 break; 245 case CHIP_POLARIS12: 246 fw_name = FIRMWARE_POLARIS12; 247 break; 248 case CHIP_VEGA10: 249 fw_name = FIRMWARE_VEGA10; 250 break; 251 case CHIP_VEGA12: 252 fw_name = FIRMWARE_VEGA12; 253 break; 254 case CHIP_VEGAM: 255 fw_name = FIRMWARE_VEGAM; 256 break; 257 case CHIP_VEGA20: 258 fw_name = FIRMWARE_VEGA20; 259 break; 260 default: 261 return -EINVAL; 262 } 263 264 r = amdgpu_ucode_request(adev, &adev->uvd.fw, AMDGPU_UCODE_REQUIRED, "%s", fw_name); 265 if (r) { 266 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 267 fw_name); 268 amdgpu_ucode_release(&adev->uvd.fw); 269 return r; 270 } 271 272 /* Set the default UVD handles that the firmware can handle */ 273 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 274 275 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 276 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 277 278 if (adev->asic_type < CHIP_VEGA20) { 279 unsigned int version_major, version_minor; 280 281 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 282 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 283 drm_info(adev_to_drm(adev), "Found UVD firmware Version: %u.%u Family ID: %u\n", 284 version_major, version_minor, family_id); 285 286 /* 287 * Limit the number of UVD handles depending on microcode major 288 * and minor versions. The firmware version which has 40 UVD 289 * instances support is 1.80. So all subsequent versions should 290 * also have the same support. 291 */ 292 if ((version_major > 0x01) || 293 ((version_major == 0x01) && (version_minor >= 0x50))) 294 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 295 296 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 297 (family_id << 8)); 298 299 if ((adev->asic_type == CHIP_POLARIS10 || 300 adev->asic_type == CHIP_POLARIS11) && 301 (adev->uvd.fw_version < FW_1_66_16)) 302 DRM_ERROR("POLARIS10/11 UVD firmware version %u.%u is too old.\n", 303 version_major, version_minor); 304 } else { 305 unsigned int enc_major, enc_minor, dec_minor; 306 307 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 308 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f; 309 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3; 310 drm_info(adev_to_drm(adev), "Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n", 311 enc_major, enc_minor, dec_minor, family_id); 312 313 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 314 315 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version); 316 } 317 318 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 319 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 320 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 321 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 322 323 /* UVD 5.0 and newer HW can use 64 bit addressing. */ 324 adev->uvd.address_64_bit = 325 !amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0); 326 327 vcpu_bo_domain = AMDGPU_GEM_DOMAIN_VRAM; 328 if (adev->uvd.address_64_bit) 329 vcpu_bo_domain |= AMDGPU_GEM_DOMAIN_GTT; 330 331 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 332 if (adev->uvd.harvest_config & (1 << j)) 333 continue; 334 335 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 336 vcpu_bo_domain, 337 &adev->uvd.inst[j].vcpu_bo, 338 &adev->uvd.inst[j].gpu_addr, 339 &adev->uvd.inst[j].cpu_addr); 340 if (r) { 341 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 342 return r; 343 } 344 } 345 346 for (i = 0; i < adev->uvd.max_handles; ++i) { 347 atomic_set(&adev->uvd.handles[i], 0); 348 adev->uvd.filp[i] = NULL; 349 } 350 351 r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo); 352 if (r) 353 return r; 354 355 switch (adev->asic_type) { 356 case CHIP_TONGA: 357 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; 358 break; 359 case CHIP_CARRIZO: 360 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; 361 break; 362 case CHIP_FIJI: 363 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; 364 break; 365 case CHIP_STONEY: 366 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; 367 break; 368 default: 369 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; 370 } 371 372 return 0; 373 } 374 375 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 376 { 377 void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo); 378 int i, j; 379 380 drm_sched_entity_destroy(&adev->uvd.entity); 381 382 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 383 if (adev->uvd.harvest_config & (1 << j)) 384 continue; 385 kvfree(adev->uvd.inst[j].saved_bo); 386 387 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo, 388 &adev->uvd.inst[j].gpu_addr, 389 (void **)&adev->uvd.inst[j].cpu_addr); 390 391 amdgpu_ring_fini(&adev->uvd.inst[j].ring); 392 393 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) 394 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 395 } 396 amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr); 397 amdgpu_ucode_release(&adev->uvd.fw); 398 399 return 0; 400 } 401 402 /** 403 * amdgpu_uvd_entity_init - init entity 404 * 405 * @adev: amdgpu_device pointer 406 * @ring: amdgpu_ring pointer to check 407 * 408 * Initialize the entity used for handle management in the kernel driver. 409 */ 410 int amdgpu_uvd_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring) 411 { 412 if (ring == &adev->uvd.inst[0].ring) { 413 struct drm_gpu_scheduler *sched = &ring->sched; 414 int r; 415 416 r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL, 417 &sched, 1, NULL); 418 if (r) { 419 DRM_ERROR("Failed setting up UVD kernel entity.\n"); 420 return r; 421 } 422 } 423 424 return 0; 425 } 426 427 int amdgpu_uvd_prepare_suspend(struct amdgpu_device *adev) 428 { 429 unsigned int size; 430 void *ptr; 431 int i, j, idx; 432 433 cancel_delayed_work_sync(&adev->uvd.idle_work); 434 435 /* only valid for physical mode */ 436 if (adev->asic_type < CHIP_POLARIS10) { 437 for (i = 0; i < adev->uvd.max_handles; ++i) 438 if (atomic_read(&adev->uvd.handles[i])) 439 break; 440 441 if (i == adev->uvd.max_handles) 442 return 0; 443 } 444 445 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 446 if (adev->uvd.harvest_config & (1 << j)) 447 continue; 448 if (adev->uvd.inst[j].vcpu_bo == NULL) 449 continue; 450 451 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo); 452 ptr = adev->uvd.inst[j].cpu_addr; 453 454 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL); 455 if (!adev->uvd.inst[j].saved_bo) 456 return -ENOMEM; 457 458 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 459 /* re-write 0 since err_event_athub will corrupt VCPU buffer */ 460 if (amdgpu_ras_intr_triggered()) 461 memset(adev->uvd.inst[j].saved_bo, 0, size); 462 else 463 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); 464 465 drm_dev_exit(idx); 466 } 467 } 468 469 return 0; 470 } 471 472 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 473 { 474 if (amdgpu_ras_intr_triggered()) 475 drm_warn(adev_to_drm(adev), 476 "UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n"); 477 478 return 0; 479 } 480 481 int amdgpu_uvd_resume(struct amdgpu_device *adev) 482 { 483 unsigned int size; 484 void *ptr; 485 int i, idx; 486 487 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 488 if (adev->uvd.harvest_config & (1 << i)) 489 continue; 490 if (adev->uvd.inst[i].vcpu_bo == NULL) 491 return -EINVAL; 492 493 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo); 494 ptr = adev->uvd.inst[i].cpu_addr; 495 496 if (adev->uvd.inst[i].saved_bo != NULL) { 497 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 498 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size); 499 drm_dev_exit(idx); 500 } 501 kvfree(adev->uvd.inst[i].saved_bo); 502 adev->uvd.inst[i].saved_bo = NULL; 503 } else { 504 const struct common_firmware_header *hdr; 505 unsigned int offset; 506 507 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 508 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 509 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 510 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 511 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, 512 le32_to_cpu(hdr->ucode_size_bytes)); 513 drm_dev_exit(idx); 514 } 515 size -= le32_to_cpu(hdr->ucode_size_bytes); 516 ptr += le32_to_cpu(hdr->ucode_size_bytes); 517 } 518 memset_io(ptr, 0, size); 519 /* to restore uvd fence seq */ 520 if (adev->uvd.inst[i].ring.fence_drv.initialized) 521 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring, NULL); 522 } 523 } 524 return 0; 525 } 526 527 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 528 { 529 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring; 530 int i, r; 531 532 for (i = 0; i < adev->uvd.max_handles; ++i) { 533 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 534 535 if (handle != 0 && adev->uvd.filp[i] == filp) { 536 struct dma_fence *fence; 537 538 r = amdgpu_uvd_get_destroy_msg(ring, handle, false, 539 &fence); 540 if (r) { 541 DRM_ERROR("Error destroying UVD %d!\n", r); 542 continue; 543 } 544 545 dma_fence_wait(fence, false); 546 dma_fence_put(fence); 547 548 adev->uvd.filp[i] = NULL; 549 atomic_set(&adev->uvd.handles[i], 0); 550 } 551 } 552 } 553 554 static void amdgpu_uvd_force_into_vcpu_segment(struct amdgpu_bo *bo) 555 { 556 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 557 struct amdgpu_bo *vcpu_bo = adev->uvd.inst[0].vcpu_bo; 558 struct amdgpu_res_cursor vcpu_cur; 559 560 amdgpu_res_first(vcpu_bo->tbo.resource, 0, 561 amdgpu_bo_size(vcpu_bo), &vcpu_cur); 562 563 bo->placement.num_placement = 1; 564 bo->placement.placement = &bo->placements[0]; 565 bo->placements[0].fpfn = ALIGN_DOWN(vcpu_cur.start, SZ_256M) >> PAGE_SHIFT; 566 bo->placements[0].lpfn = bo->placements[0].fpfn + (SZ_256M >> PAGE_SHIFT); 567 bo->placements[0].mem_type = vcpu_bo->tbo.resource->mem_type; 568 if (bo->placements[0].mem_type == TTM_PL_VRAM) 569 bo->placements[0].flags |= TTM_PL_FLAG_CONTIGUOUS; 570 } 571 572 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 573 { 574 int i; 575 576 for (i = 0; i < abo->placement.num_placement; ++i) { 577 abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 578 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 579 if (abo->placements[i].mem_type == TTM_PL_VRAM) 580 abo->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS; 581 } 582 } 583 584 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) 585 { 586 uint32_t lo, hi; 587 uint64_t addr; 588 589 lo = amdgpu_ib_get_value(ctx->ib, ctx->data0); 590 hi = amdgpu_ib_get_value(ctx->ib, ctx->data1); 591 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 592 593 return addr; 594 } 595 596 /** 597 * amdgpu_uvd_cs_pass1 - first parsing round 598 * 599 * @ctx: UVD parser context 600 * 601 * Make sure UVD message and feedback buffers are in VRAM and 602 * nobody is violating an 256MB boundary. 603 */ 604 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 605 { 606 struct ttm_operation_ctx tctx = { false, false }; 607 struct amdgpu_bo_va_mapping *mapping; 608 struct amdgpu_bo *bo; 609 uint32_t cmd; 610 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 611 int r = 0; 612 613 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 614 if (r) { 615 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 616 return r; 617 } 618 619 if (!ctx->parser->adev->uvd.address_64_bit) { 620 /* check if it's a message or feedback command */ 621 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1; 622 if (cmd == 0x0 || cmd == 0x3) 623 amdgpu_uvd_force_into_vcpu_segment(bo); 624 else 625 amdgpu_uvd_force_into_uvd_segment(bo); 626 627 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); 628 } 629 630 return r; 631 } 632 633 /** 634 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 635 * 636 * @adev: amdgpu_device pointer 637 * @msg: pointer to message structure 638 * @buf_sizes: placeholder to put the different buffer lengths 639 * 640 * Peek into the decode message and calculate the necessary buffer sizes. 641 */ 642 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 643 unsigned int buf_sizes[]) 644 { 645 unsigned int stream_type = msg[4]; 646 unsigned int width = msg[6]; 647 unsigned int height = msg[7]; 648 unsigned int dpb_size = msg[9]; 649 unsigned int pitch = msg[28]; 650 651 unsigned int width_in_mb = width / 16; 652 unsigned int height_in_mb = ALIGN(height / 16, 2); 653 654 unsigned int image_size, tmp, min_dpb_size, num_dpb_buffer; 655 unsigned int min_ctx_size = ~0; 656 657 /* Reject invalid dimensions */ 658 if (width < 16 || height < 16 || width > 4096 || height > 4096) { 659 dev_WARN_ONCE(adev->dev, 1, 660 "Invalid UVD decoding dimensions (%dx%d)!\n", 661 width, height); 662 return -EINVAL; 663 } 664 665 image_size = width * height; 666 image_size += image_size / 2; 667 image_size = ALIGN(image_size, 1024); 668 669 switch (stream_type) { 670 case 0: /* H264 */ 671 num_dpb_buffer = ((msg[61] >> 16) & 0xff) + 1; 672 if (num_dpb_buffer > 17) 673 return -EINVAL; 674 675 /* reference picture buffer */ 676 min_dpb_size = image_size * num_dpb_buffer; 677 678 /* macroblock context buffer */ 679 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 680 681 /* IT surface buffer */ 682 min_dpb_size += width_in_mb * height_in_mb * 32; 683 break; 684 685 case 1: /* VC1 */ 686 687 /* reference picture buffer */ 688 min_dpb_size = image_size * 3; 689 690 /* CONTEXT_BUFFER */ 691 min_dpb_size += width_in_mb * height_in_mb * 128; 692 693 /* IT surface buffer */ 694 min_dpb_size += width_in_mb * 64; 695 696 /* DB surface buffer */ 697 min_dpb_size += width_in_mb * 128; 698 699 /* BP */ 700 tmp = max(width_in_mb, height_in_mb); 701 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 702 break; 703 704 case 3: /* MPEG2 */ 705 706 /* reference picture buffer */ 707 min_dpb_size = image_size * 3; 708 break; 709 710 case 4: /* MPEG4 */ 711 712 /* reference picture buffer */ 713 min_dpb_size = image_size * 3; 714 715 /* CM */ 716 min_dpb_size += width_in_mb * height_in_mb * 64; 717 718 /* IT surface buffer */ 719 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 720 break; 721 722 case 7: /* H264 Perf */ 723 num_dpb_buffer = ((msg[61] >> 16) & 0xff) + 1; 724 if (num_dpb_buffer > 17) 725 return -EINVAL; 726 727 /* reference picture buffer */ 728 min_dpb_size = image_size * num_dpb_buffer; 729 730 if (!adev->uvd.use_ctx_buf) { 731 /* macroblock context buffer */ 732 min_dpb_size += 733 width_in_mb * height_in_mb * num_dpb_buffer * 192; 734 735 /* IT surface buffer */ 736 min_dpb_size += width_in_mb * height_in_mb * 32; 737 } else { 738 /* macroblock context buffer */ 739 min_ctx_size = 740 width_in_mb * height_in_mb * num_dpb_buffer * 192; 741 } 742 break; 743 744 case 8: /* MJPEG */ 745 min_dpb_size = 0; 746 break; 747 748 case 16: /* H265 */ 749 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 750 image_size = ALIGN(image_size, 256); 751 752 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 753 if (num_dpb_buffer > 17) 754 return -EINVAL; 755 756 min_dpb_size = image_size * num_dpb_buffer; 757 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 758 * 16 * num_dpb_buffer + 52 * 1024; 759 break; 760 761 default: 762 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 763 return -EINVAL; 764 } 765 766 if (width > pitch || pitch > 4096) { 767 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 768 return -EINVAL; 769 } 770 771 if (dpb_size < min_dpb_size) { 772 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 773 dpb_size, min_dpb_size); 774 return -EINVAL; 775 } 776 777 buf_sizes[0x1] = dpb_size; 778 buf_sizes[0x2] = (pitch * height) * 3 / 2; 779 buf_sizes[0x4] = min_ctx_size; 780 /* store image width to adjust nb memory pstate */ 781 adev->uvd.decode_image_width = width; 782 return 0; 783 } 784 785 /** 786 * amdgpu_uvd_cs_msg - handle UVD message 787 * 788 * @ctx: UVD parser context 789 * @bo: buffer object containing the message 790 * @offset: offset into the buffer object 791 * 792 * Peek into the UVD message and extract the session id. 793 * Make sure that we don't open up to many sessions. 794 */ 795 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 796 struct amdgpu_bo *bo, unsigned int offset) 797 { 798 struct amdgpu_device *adev = ctx->parser->adev; 799 int32_t *msg, msg_type, handle; 800 void *ptr; 801 long r; 802 int i; 803 804 if (offset & 0x3F) { 805 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 806 return -EINVAL; 807 } 808 809 r = amdgpu_bo_kmap(bo, &ptr); 810 if (r) { 811 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r); 812 return r; 813 } 814 815 msg = ptr + offset; 816 817 msg_type = msg[1]; 818 handle = msg[2]; 819 820 if (handle == 0) { 821 amdgpu_bo_kunmap(bo); 822 DRM_ERROR("Invalid UVD handle!\n"); 823 return -EINVAL; 824 } 825 826 switch (msg_type) { 827 case 0: 828 /* it's a create msg, calc image size (width * height) */ 829 amdgpu_bo_kunmap(bo); 830 831 /* try to alloc a new handle */ 832 for (i = 0; i < adev->uvd.max_handles; ++i) { 833 if (atomic_read(&adev->uvd.handles[i]) == handle) { 834 DRM_ERROR(")Handle 0x%x already in use!\n", 835 handle); 836 return -EINVAL; 837 } 838 839 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 840 adev->uvd.filp[i] = ctx->parser->filp; 841 return 0; 842 } 843 } 844 845 DRM_ERROR("No more free UVD handles!\n"); 846 return -ENOSPC; 847 848 case 1: 849 /* it's a decode msg, calc buffer sizes */ 850 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 851 amdgpu_bo_kunmap(bo); 852 if (r) 853 return r; 854 855 /* validate the handle */ 856 for (i = 0; i < adev->uvd.max_handles; ++i) { 857 if (atomic_read(&adev->uvd.handles[i]) == handle) { 858 if (adev->uvd.filp[i] != ctx->parser->filp) { 859 DRM_ERROR("UVD handle collision detected!\n"); 860 return -EINVAL; 861 } 862 return 0; 863 } 864 } 865 866 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 867 return -ENOENT; 868 869 case 2: 870 /* it's a destroy msg, free the handle */ 871 for (i = 0; i < adev->uvd.max_handles; ++i) 872 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 873 amdgpu_bo_kunmap(bo); 874 return 0; 875 876 default: 877 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 878 } 879 880 amdgpu_bo_kunmap(bo); 881 return -EINVAL; 882 } 883 884 /** 885 * amdgpu_uvd_cs_pass2 - second parsing round 886 * 887 * @ctx: UVD parser context 888 * 889 * Patch buffer addresses, make sure buffer sizes are correct. 890 */ 891 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 892 { 893 struct amdgpu_bo_va_mapping *mapping; 894 struct amdgpu_bo *bo; 895 uint32_t cmd; 896 uint64_t start, end; 897 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 898 int r; 899 900 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 901 if (r) { 902 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 903 return r; 904 } 905 906 start = amdgpu_bo_gpu_offset(bo); 907 908 end = (mapping->last + 1 - mapping->start); 909 end = end * AMDGPU_GPU_PAGE_SIZE + start; 910 911 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; 912 start += addr; 913 914 amdgpu_ib_set_value(ctx->ib, ctx->data0, lower_32_bits(start)); 915 amdgpu_ib_set_value(ctx->ib, ctx->data1, upper_32_bits(start)); 916 917 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1; 918 if (cmd < 0x4) { 919 if ((end - start) < ctx->buf_sizes[cmd]) { 920 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 921 (unsigned int)(end - start), 922 ctx->buf_sizes[cmd]); 923 return -EINVAL; 924 } 925 } else if (cmd == 0x204 || cmd == 0x206) { 926 unsigned int min_size = ctx->buf_sizes[cmd == 0x204 ? 5 : 4]; 927 928 if ((end - start) < min_size) { 929 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 930 (unsigned int)(end - start), 931 min_size); 932 return -EINVAL; 933 } 934 } else if ((cmd != 0x100)) { 935 DRM_ERROR("invalid UVD command %X!\n", cmd); 936 return -EINVAL; 937 } 938 939 if (!ctx->parser->adev->uvd.address_64_bit) { 940 if ((start >> 28) != ((end - 1) >> 28)) { 941 DRM_ERROR("reloc %llx-%llx crossing 256MB boundary!\n", 942 start, end); 943 return -EINVAL; 944 } 945 946 if ((cmd == 0 || cmd == 0x3) && 947 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) { 948 DRM_ERROR("msg/fb buffer %llx-%llx out of 256MB segment!\n", 949 start, end); 950 return -EINVAL; 951 } 952 } 953 954 if (cmd == 0) { 955 ctx->has_msg_cmd = true; 956 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 957 if (r) 958 return r; 959 } else if (!ctx->has_msg_cmd) { 960 DRM_ERROR("Message needed before other commands are send!\n"); 961 return -EINVAL; 962 } 963 964 return 0; 965 } 966 967 /** 968 * amdgpu_uvd_cs_reg - parse register writes 969 * 970 * @ctx: UVD parser context 971 * @cb: callback function 972 * 973 * Parse the register writes, call cb on each complete command. 974 */ 975 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 976 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 977 { 978 int i, r; 979 980 ctx->idx++; 981 for (i = 0; i <= ctx->count; ++i) { 982 unsigned int reg = ctx->reg + i; 983 984 if (ctx->idx >= ctx->ib->length_dw) { 985 DRM_ERROR("Register command after end of CS!\n"); 986 return -EINVAL; 987 } 988 989 switch (reg) { 990 case mmUVD_GPCOM_VCPU_DATA0: 991 ctx->data0 = ctx->idx; 992 break; 993 case mmUVD_GPCOM_VCPU_DATA1: 994 ctx->data1 = ctx->idx; 995 break; 996 case mmUVD_GPCOM_VCPU_CMD: 997 r = cb(ctx); 998 if (r) 999 return r; 1000 break; 1001 case mmUVD_ENGINE_CNTL: 1002 case mmUVD_NO_OP: 1003 break; 1004 default: 1005 DRM_ERROR("Invalid reg 0x%X!\n", reg); 1006 return -EINVAL; 1007 } 1008 ctx->idx++; 1009 } 1010 return 0; 1011 } 1012 1013 /** 1014 * amdgpu_uvd_cs_packets - parse UVD packets 1015 * 1016 * @ctx: UVD parser context 1017 * @cb: callback function 1018 * 1019 * Parse the command stream packets. 1020 */ 1021 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 1022 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 1023 { 1024 int r; 1025 1026 for (ctx->idx = 0 ; ctx->idx < ctx->ib->length_dw; ) { 1027 uint32_t cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx); 1028 unsigned int type = CP_PACKET_GET_TYPE(cmd); 1029 1030 switch (type) { 1031 case PACKET_TYPE0: 1032 ctx->reg = CP_PACKET0_GET_REG(cmd); 1033 ctx->count = CP_PACKET_GET_COUNT(cmd); 1034 r = amdgpu_uvd_cs_reg(ctx, cb); 1035 if (r) 1036 return r; 1037 break; 1038 case PACKET_TYPE2: 1039 ++ctx->idx; 1040 break; 1041 default: 1042 DRM_ERROR("Unknown packet type %d !\n", type); 1043 return -EINVAL; 1044 } 1045 } 1046 return 0; 1047 } 1048 1049 /** 1050 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 1051 * 1052 * @parser: Command submission parser context 1053 * @job: the job to parse 1054 * @ib: the IB to patch 1055 * 1056 * Parse the command stream, patch in addresses as necessary. 1057 */ 1058 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, 1059 struct amdgpu_job *job, 1060 struct amdgpu_ib *ib) 1061 { 1062 struct amdgpu_uvd_cs_ctx ctx = {}; 1063 unsigned int buf_sizes[] = { 1064 [0x00000000] = 3556, 1065 [0x00000001] = 0xFFFFFFFF, 1066 [0x00000002] = 0xFFFFFFFF, 1067 [0x00000003] = 2048, 1068 [0x00000004] = 0xFFFFFFFF, 1069 [0x00000005] = 992, 1070 }; 1071 int r; 1072 1073 job->vm = NULL; 1074 1075 if (ib->length_dw % 16) { 1076 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 1077 ib->length_dw); 1078 return -EINVAL; 1079 } 1080 1081 ctx.parser = parser; 1082 ctx.buf_sizes = buf_sizes; 1083 ctx.ib = ib; 1084 1085 /* first round only required on chips without UVD 64 bit address support */ 1086 if (!parser->adev->uvd.address_64_bit) { 1087 /* first round, make sure the buffers are actually in the UVD segment */ 1088 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 1089 if (r) 1090 return r; 1091 } 1092 1093 /* second round, patch buffer addresses into the command stream */ 1094 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 1095 if (r) 1096 return r; 1097 1098 if (!ctx.has_msg_cmd) { 1099 DRM_ERROR("UVD-IBs need a msg command!\n"); 1100 return -EINVAL; 1101 } 1102 1103 return 0; 1104 } 1105 1106 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 1107 bool direct, struct dma_fence **fence) 1108 { 1109 struct amdgpu_device *adev = ring->adev; 1110 struct dma_fence *f = NULL; 1111 uint32_t offset, data[4]; 1112 struct amdgpu_job *job; 1113 struct amdgpu_ib *ib; 1114 uint64_t addr; 1115 int i, r; 1116 1117 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->uvd.entity, 1118 AMDGPU_FENCE_OWNER_UNDEFINED, 1119 64, direct ? AMDGPU_IB_POOL_DIRECT : 1120 AMDGPU_IB_POOL_DELAYED, 1121 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST, 1122 &job); 1123 if (r) 1124 return r; 1125 1126 if (adev->asic_type >= CHIP_VEGA10) 1127 offset = adev->reg_offset[UVD_HWIP][ring->me][1]; 1128 else 1129 offset = UVD_BASE_SI; 1130 1131 data[0] = PACKET0(offset + UVD_GPCOM_VCPU_DATA0, 0); 1132 data[1] = PACKET0(offset + UVD_GPCOM_VCPU_DATA1, 0); 1133 data[2] = PACKET0(offset + UVD_GPCOM_VCPU_CMD, 0); 1134 data[3] = PACKET0(offset + UVD_NO_OP, 0); 1135 1136 ib = &job->ibs[0]; 1137 addr = amdgpu_bo_gpu_offset(bo); 1138 ib->ptr[0] = data[0]; 1139 ib->ptr[1] = addr; 1140 ib->ptr[2] = data[1]; 1141 ib->ptr[3] = addr >> 32; 1142 ib->ptr[4] = data[2]; 1143 ib->ptr[5] = 0; 1144 for (i = 6; i < 16; i += 2) { 1145 ib->ptr[i] = data[3]; 1146 ib->ptr[i+1] = 0; 1147 } 1148 ib->length_dw = 16; 1149 1150 if (direct) { 1151 r = amdgpu_job_submit_direct(job, ring, &f); 1152 if (r) 1153 goto err_free; 1154 } else { 1155 r = drm_sched_job_add_resv_dependencies(&job->base, 1156 bo->tbo.base.resv, 1157 DMA_RESV_USAGE_KERNEL); 1158 if (r) 1159 goto err_free; 1160 1161 f = amdgpu_job_submit(job); 1162 } 1163 1164 amdgpu_bo_reserve(bo, true); 1165 amdgpu_bo_fence(bo, f, false); 1166 amdgpu_bo_unreserve(bo); 1167 1168 if (fence) 1169 *fence = dma_fence_get(f); 1170 dma_fence_put(f); 1171 1172 return 0; 1173 1174 err_free: 1175 amdgpu_job_free(job); 1176 return r; 1177 } 1178 1179 /* multiple fence commands without any stream commands in between can 1180 * crash the vcpu so just try to emmit a dummy create/destroy msg to 1181 * avoid this 1182 */ 1183 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1184 struct dma_fence **fence) 1185 { 1186 struct amdgpu_device *adev = ring->adev; 1187 struct amdgpu_bo *bo = adev->uvd.ib_bo; 1188 uint32_t *msg; 1189 int i; 1190 1191 msg = amdgpu_bo_kptr(bo); 1192 /* stitch together an UVD create msg */ 1193 msg[0] = cpu_to_le32(0x00000de4); 1194 msg[1] = cpu_to_le32(0x00000000); 1195 msg[2] = cpu_to_le32(handle); 1196 msg[3] = cpu_to_le32(0x00000000); 1197 msg[4] = cpu_to_le32(0x00000000); 1198 msg[5] = cpu_to_le32(0x00000000); 1199 msg[6] = cpu_to_le32(0x00000000); 1200 msg[7] = cpu_to_le32(0x00000780); 1201 msg[8] = cpu_to_le32(0x00000440); 1202 msg[9] = cpu_to_le32(0x00000000); 1203 msg[10] = cpu_to_le32(0x01b37000); 1204 for (i = 11; i < 1024; ++i) 1205 msg[i] = cpu_to_le32(0x0); 1206 1207 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1208 1209 } 1210 1211 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1212 bool direct, struct dma_fence **fence) 1213 { 1214 struct amdgpu_device *adev = ring->adev; 1215 struct amdgpu_bo *bo = NULL; 1216 uint32_t *msg; 1217 int r, i; 1218 1219 if (direct) { 1220 bo = adev->uvd.ib_bo; 1221 } else { 1222 r = amdgpu_uvd_create_msg_bo_helper(adev, 4096, &bo); 1223 if (r) 1224 return r; 1225 } 1226 1227 msg = amdgpu_bo_kptr(bo); 1228 /* stitch together an UVD destroy msg */ 1229 msg[0] = cpu_to_le32(0x00000de4); 1230 msg[1] = cpu_to_le32(0x00000002); 1231 msg[2] = cpu_to_le32(handle); 1232 msg[3] = cpu_to_le32(0x00000000); 1233 for (i = 4; i < 1024; ++i) 1234 msg[i] = cpu_to_le32(0x0); 1235 1236 r = amdgpu_uvd_send_msg(ring, bo, direct, fence); 1237 1238 if (!direct) 1239 amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg); 1240 1241 return r; 1242 } 1243 1244 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1245 { 1246 struct amdgpu_device *adev = 1247 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1248 unsigned int fences = 0, i, j; 1249 1250 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1251 if (adev->uvd.harvest_config & (1 << i)) 1252 continue; 1253 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring); 1254 for (j = 0; j < adev->uvd.num_enc_rings; ++j) 1255 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]); 1256 } 1257 1258 if (fences == 0) { 1259 if (adev->pm.dpm_enabled) { 1260 amdgpu_dpm_enable_uvd(adev, false); 1261 } else { 1262 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1263 /* shutdown the UVD block */ 1264 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1265 AMD_PG_STATE_GATE); 1266 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1267 AMD_CG_STATE_GATE); 1268 } 1269 } else { 1270 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1271 } 1272 } 1273 1274 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 1275 { 1276 struct amdgpu_device *adev = ring->adev; 1277 bool set_clocks; 1278 1279 if (amdgpu_sriov_vf(adev)) 1280 return; 1281 1282 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1283 if (set_clocks) { 1284 if (adev->pm.dpm_enabled) { 1285 amdgpu_dpm_enable_uvd(adev, true); 1286 } else { 1287 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1288 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1289 AMD_CG_STATE_UNGATE); 1290 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1291 AMD_PG_STATE_UNGATE); 1292 } 1293 } 1294 } 1295 1296 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) 1297 { 1298 if (!amdgpu_sriov_vf(ring->adev)) 1299 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1300 } 1301 1302 /** 1303 * amdgpu_uvd_ring_test_ib - test ib execution 1304 * 1305 * @ring: amdgpu_ring pointer 1306 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1307 * 1308 * Test if we can successfully execute an IB 1309 */ 1310 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1311 { 1312 struct dma_fence *fence; 1313 long r; 1314 1315 r = amdgpu_uvd_get_create_msg(ring, 1, &fence); 1316 if (r) 1317 goto error; 1318 1319 r = dma_fence_wait_timeout(fence, false, timeout); 1320 dma_fence_put(fence); 1321 if (r == 0) 1322 r = -ETIMEDOUT; 1323 if (r < 0) 1324 goto error; 1325 1326 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 1327 if (r) 1328 goto error; 1329 1330 r = dma_fence_wait_timeout(fence, false, timeout); 1331 if (r == 0) 1332 r = -ETIMEDOUT; 1333 else if (r > 0) 1334 r = 0; 1335 1336 dma_fence_put(fence); 1337 1338 error: 1339 return r; 1340 } 1341 1342 /** 1343 * amdgpu_uvd_used_handles - returns used UVD handles 1344 * 1345 * @adev: amdgpu_device pointer 1346 * 1347 * Returns the number of UVD handles in use 1348 */ 1349 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) 1350 { 1351 unsigned int i; 1352 uint32_t used_handles = 0; 1353 1354 for (i = 0; i < adev->uvd.max_handles; ++i) { 1355 /* 1356 * Handles can be freed in any order, and not 1357 * necessarily linear. So we need to count 1358 * all non-zero handles. 1359 */ 1360 if (atomic_read(&adev->uvd.handles[i])) 1361 used_handles++; 1362 } 1363 1364 return used_handles; 1365 } 1366