1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 34 #include <drm/drm.h> 35 #include <drm/drm_drv.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_pm.h" 39 #include "amdgpu_uvd.h" 40 #include "amdgpu_cs.h" 41 #include "cikd.h" 42 #include "uvd/uvd_4_2_d.h" 43 44 #include "amdgpu_ras.h" 45 46 /* 1 second timeout */ 47 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) 48 49 /* Firmware versions for VI */ 50 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) 51 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) 52 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) 53 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) 54 55 /* Polaris10/11 firmware version */ 56 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 57 58 /* Firmware Names */ 59 #ifdef CONFIG_DRM_AMDGPU_SI 60 #define FIRMWARE_TAHITI "amdgpu/tahiti_uvd.bin" 61 #define FIRMWARE_VERDE "amdgpu/verde_uvd.bin" 62 #define FIRMWARE_PITCAIRN "amdgpu/pitcairn_uvd.bin" 63 #define FIRMWARE_OLAND "amdgpu/oland_uvd.bin" 64 #endif 65 #ifdef CONFIG_DRM_AMDGPU_CIK 66 #define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin" 67 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin" 68 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin" 69 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin" 70 #define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin" 71 #endif 72 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 73 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 74 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 75 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 76 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 77 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 78 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" 79 #define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin" 80 81 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" 82 #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin" 83 #define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin" 84 85 /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */ 86 #define UVD_GPCOM_VCPU_CMD 0x03c3 87 #define UVD_GPCOM_VCPU_DATA0 0x03c4 88 #define UVD_GPCOM_VCPU_DATA1 0x03c5 89 #define UVD_NO_OP 0x03ff 90 #define UVD_BASE_SI 0x3800 91 92 /* 93 * amdgpu_uvd_cs_ctx - Command submission parser context 94 * 95 * Used for emulating virtual memory support on UVD 4.2. 96 */ 97 struct amdgpu_uvd_cs_ctx { 98 struct amdgpu_cs_parser *parser; 99 unsigned int reg, count; 100 unsigned int data0, data1; 101 unsigned int idx; 102 struct amdgpu_ib *ib; 103 104 /* does the IB has a msg command */ 105 bool has_msg_cmd; 106 107 /* minimum buffer sizes */ 108 unsigned int *buf_sizes; 109 }; 110 111 #ifdef CONFIG_DRM_AMDGPU_SI 112 MODULE_FIRMWARE(FIRMWARE_TAHITI); 113 MODULE_FIRMWARE(FIRMWARE_VERDE); 114 MODULE_FIRMWARE(FIRMWARE_PITCAIRN); 115 MODULE_FIRMWARE(FIRMWARE_OLAND); 116 #endif 117 #ifdef CONFIG_DRM_AMDGPU_CIK 118 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 119 MODULE_FIRMWARE(FIRMWARE_KABINI); 120 MODULE_FIRMWARE(FIRMWARE_KAVERI); 121 MODULE_FIRMWARE(FIRMWARE_HAWAII); 122 MODULE_FIRMWARE(FIRMWARE_MULLINS); 123 #endif 124 MODULE_FIRMWARE(FIRMWARE_TONGA); 125 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 126 MODULE_FIRMWARE(FIRMWARE_FIJI); 127 MODULE_FIRMWARE(FIRMWARE_STONEY); 128 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 129 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 130 MODULE_FIRMWARE(FIRMWARE_POLARIS12); 131 MODULE_FIRMWARE(FIRMWARE_VEGAM); 132 133 MODULE_FIRMWARE(FIRMWARE_VEGA10); 134 MODULE_FIRMWARE(FIRMWARE_VEGA12); 135 MODULE_FIRMWARE(FIRMWARE_VEGA20); 136 137 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 138 static void amdgpu_uvd_force_into_vcpu_segment(struct amdgpu_bo *abo); 139 140 static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev, 141 uint32_t size, 142 struct amdgpu_bo **bo_ptr) 143 { 144 struct ttm_operation_ctx ctx = { true, false }; 145 struct amdgpu_bo *bo = NULL; 146 void *addr; 147 int r; 148 149 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, 150 AMDGPU_GEM_DOMAIN_GTT, 151 &bo, NULL, &addr); 152 if (r) 153 return r; 154 155 if (adev->uvd.address_64_bit) 156 goto succ; 157 158 amdgpu_bo_kunmap(bo); 159 amdgpu_bo_unpin(bo); 160 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 161 amdgpu_uvd_force_into_vcpu_segment(bo); 162 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 163 if (r) 164 goto err; 165 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM); 166 if (r) 167 goto err_pin; 168 r = amdgpu_bo_kmap(bo, &addr); 169 if (r) 170 goto err_kmap; 171 succ: 172 amdgpu_bo_unreserve(bo); 173 *bo_ptr = bo; 174 return 0; 175 err_kmap: 176 amdgpu_bo_unpin(bo); 177 err_pin: 178 err: 179 amdgpu_bo_unreserve(bo); 180 amdgpu_bo_unref(&bo); 181 return r; 182 } 183 184 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 185 { 186 unsigned long bo_size; 187 const char *fw_name; 188 const struct common_firmware_header *hdr; 189 unsigned int family_id; 190 int i, j, r; 191 u32 vcpu_bo_domain; 192 193 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 194 195 switch (adev->asic_type) { 196 #ifdef CONFIG_DRM_AMDGPU_SI 197 case CHIP_TAHITI: 198 fw_name = FIRMWARE_TAHITI; 199 break; 200 case CHIP_VERDE: 201 fw_name = FIRMWARE_VERDE; 202 break; 203 case CHIP_PITCAIRN: 204 fw_name = FIRMWARE_PITCAIRN; 205 break; 206 case CHIP_OLAND: 207 fw_name = FIRMWARE_OLAND; 208 break; 209 #endif 210 #ifdef CONFIG_DRM_AMDGPU_CIK 211 case CHIP_BONAIRE: 212 fw_name = FIRMWARE_BONAIRE; 213 break; 214 case CHIP_KABINI: 215 fw_name = FIRMWARE_KABINI; 216 break; 217 case CHIP_KAVERI: 218 fw_name = FIRMWARE_KAVERI; 219 break; 220 case CHIP_HAWAII: 221 fw_name = FIRMWARE_HAWAII; 222 break; 223 case CHIP_MULLINS: 224 fw_name = FIRMWARE_MULLINS; 225 break; 226 #endif 227 case CHIP_TONGA: 228 fw_name = FIRMWARE_TONGA; 229 break; 230 case CHIP_FIJI: 231 fw_name = FIRMWARE_FIJI; 232 break; 233 case CHIP_CARRIZO: 234 fw_name = FIRMWARE_CARRIZO; 235 break; 236 case CHIP_STONEY: 237 fw_name = FIRMWARE_STONEY; 238 break; 239 case CHIP_POLARIS10: 240 fw_name = FIRMWARE_POLARIS10; 241 break; 242 case CHIP_POLARIS11: 243 fw_name = FIRMWARE_POLARIS11; 244 break; 245 case CHIP_POLARIS12: 246 fw_name = FIRMWARE_POLARIS12; 247 break; 248 case CHIP_VEGA10: 249 fw_name = FIRMWARE_VEGA10; 250 break; 251 case CHIP_VEGA12: 252 fw_name = FIRMWARE_VEGA12; 253 break; 254 case CHIP_VEGAM: 255 fw_name = FIRMWARE_VEGAM; 256 break; 257 case CHIP_VEGA20: 258 fw_name = FIRMWARE_VEGA20; 259 break; 260 default: 261 return -EINVAL; 262 } 263 264 r = amdgpu_ucode_request(adev, &adev->uvd.fw, AMDGPU_UCODE_REQUIRED, "%s", fw_name); 265 if (r) { 266 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 267 fw_name); 268 amdgpu_ucode_release(&adev->uvd.fw); 269 return r; 270 } 271 272 /* Set the default UVD handles that the firmware can handle */ 273 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 274 275 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 276 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 277 278 if (adev->asic_type < CHIP_VEGA20) { 279 unsigned int version_major, version_minor; 280 281 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 282 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 283 drm_info(adev_to_drm(adev), "Found UVD firmware Version: %u.%u Family ID: %u\n", 284 version_major, version_minor, family_id); 285 286 /* 287 * Limit the number of UVD handles depending on microcode major 288 * and minor versions. The firmware version which has 40 UVD 289 * instances support is 1.80. So all subsequent versions should 290 * also have the same support. 291 */ 292 if ((version_major > 0x01) || 293 ((version_major == 0x01) && (version_minor >= 0x50))) 294 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 295 296 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 297 (family_id << 8)); 298 299 if ((adev->asic_type == CHIP_POLARIS10 || 300 adev->asic_type == CHIP_POLARIS11) && 301 (adev->uvd.fw_version < FW_1_66_16)) 302 DRM_ERROR("POLARIS10/11 UVD firmware version %u.%u is too old.\n", 303 version_major, version_minor); 304 } else { 305 unsigned int enc_major, enc_minor, dec_minor; 306 307 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 308 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f; 309 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3; 310 drm_info(adev_to_drm(adev), "Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n", 311 enc_major, enc_minor, dec_minor, family_id); 312 313 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 314 315 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version); 316 } 317 318 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 319 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 320 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 321 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 322 323 /* UVD 5.0 and newer HW can use 64 bit addressing. */ 324 adev->uvd.address_64_bit = 325 !amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0); 326 327 vcpu_bo_domain = AMDGPU_GEM_DOMAIN_VRAM; 328 if (adev->uvd.address_64_bit) 329 vcpu_bo_domain |= AMDGPU_GEM_DOMAIN_GTT; 330 331 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 332 if (adev->uvd.harvest_config & (1 << j)) 333 continue; 334 335 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 336 vcpu_bo_domain, 337 &adev->uvd.inst[j].vcpu_bo, 338 &adev->uvd.inst[j].gpu_addr, 339 &adev->uvd.inst[j].cpu_addr); 340 if (r) { 341 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 342 return r; 343 } 344 } 345 346 for (i = 0; i < adev->uvd.max_handles; ++i) { 347 atomic_set(&adev->uvd.handles[i], 0); 348 adev->uvd.filp[i] = NULL; 349 } 350 351 r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo); 352 if (r) 353 return r; 354 355 switch (adev->asic_type) { 356 case CHIP_TONGA: 357 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; 358 break; 359 case CHIP_CARRIZO: 360 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; 361 break; 362 case CHIP_FIJI: 363 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; 364 break; 365 case CHIP_STONEY: 366 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; 367 break; 368 default: 369 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; 370 } 371 372 return 0; 373 } 374 375 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 376 { 377 void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo); 378 int i, j; 379 380 drm_sched_entity_destroy(&adev->uvd.entity); 381 382 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 383 if (adev->uvd.harvest_config & (1 << j)) 384 continue; 385 kvfree(adev->uvd.inst[j].saved_bo); 386 387 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo, 388 &adev->uvd.inst[j].gpu_addr, 389 (void **)&adev->uvd.inst[j].cpu_addr); 390 391 amdgpu_ring_fini(&adev->uvd.inst[j].ring); 392 393 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) 394 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 395 } 396 amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr); 397 amdgpu_ucode_release(&adev->uvd.fw); 398 399 return 0; 400 } 401 402 /** 403 * amdgpu_uvd_entity_init - init entity 404 * 405 * @adev: amdgpu_device pointer 406 * @ring: amdgpu_ring pointer to check 407 * 408 * Initialize the entity used for handle management in the kernel driver. 409 */ 410 int amdgpu_uvd_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring) 411 { 412 if (ring == &adev->uvd.inst[0].ring) { 413 struct drm_gpu_scheduler *sched = &ring->sched; 414 int r; 415 416 r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL, 417 &sched, 1, NULL); 418 if (r) { 419 DRM_ERROR("Failed setting up UVD kernel entity.\n"); 420 return r; 421 } 422 } 423 424 return 0; 425 } 426 427 int amdgpu_uvd_prepare_suspend(struct amdgpu_device *adev) 428 { 429 unsigned int size; 430 void *ptr; 431 int i, j, idx; 432 433 cancel_delayed_work_sync(&adev->uvd.idle_work); 434 435 /* only valid for physical mode */ 436 if (adev->asic_type < CHIP_POLARIS10) { 437 for (i = 0; i < adev->uvd.max_handles; ++i) 438 if (atomic_read(&adev->uvd.handles[i])) 439 break; 440 441 if (i == adev->uvd.max_handles) 442 return 0; 443 } 444 445 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 446 if (adev->uvd.harvest_config & (1 << j)) 447 continue; 448 if (adev->uvd.inst[j].vcpu_bo == NULL) 449 continue; 450 451 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo); 452 ptr = adev->uvd.inst[j].cpu_addr; 453 454 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL); 455 if (!adev->uvd.inst[j].saved_bo) 456 return -ENOMEM; 457 458 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 459 /* re-write 0 since err_event_athub will corrupt VCPU buffer */ 460 if (amdgpu_ras_intr_triggered()) 461 memset(adev->uvd.inst[j].saved_bo, 0, size); 462 else 463 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); 464 465 drm_dev_exit(idx); 466 } 467 } 468 469 return 0; 470 } 471 472 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 473 { 474 if (amdgpu_ras_intr_triggered()) 475 drm_warn(adev_to_drm(adev), 476 "UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n"); 477 478 return 0; 479 } 480 481 int amdgpu_uvd_resume(struct amdgpu_device *adev) 482 { 483 unsigned int size; 484 void *ptr; 485 int i, idx; 486 487 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 488 if (adev->uvd.harvest_config & (1 << i)) 489 continue; 490 if (adev->uvd.inst[i].vcpu_bo == NULL) 491 return -EINVAL; 492 493 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo); 494 ptr = adev->uvd.inst[i].cpu_addr; 495 496 if (adev->uvd.inst[i].saved_bo != NULL) { 497 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 498 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size); 499 drm_dev_exit(idx); 500 } 501 kvfree(adev->uvd.inst[i].saved_bo); 502 adev->uvd.inst[i].saved_bo = NULL; 503 } else { 504 const struct common_firmware_header *hdr; 505 unsigned int offset; 506 507 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 508 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 509 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 510 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 511 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, 512 le32_to_cpu(hdr->ucode_size_bytes)); 513 drm_dev_exit(idx); 514 } 515 size -= le32_to_cpu(hdr->ucode_size_bytes); 516 ptr += le32_to_cpu(hdr->ucode_size_bytes); 517 } 518 memset_io(ptr, 0, size); 519 /* to restore uvd fence seq */ 520 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring, NULL); 521 } 522 } 523 return 0; 524 } 525 526 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 527 { 528 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring; 529 int i, r; 530 531 for (i = 0; i < adev->uvd.max_handles; ++i) { 532 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 533 534 if (handle != 0 && adev->uvd.filp[i] == filp) { 535 struct dma_fence *fence; 536 537 r = amdgpu_uvd_get_destroy_msg(ring, handle, false, 538 &fence); 539 if (r) { 540 DRM_ERROR("Error destroying UVD %d!\n", r); 541 continue; 542 } 543 544 dma_fence_wait(fence, false); 545 dma_fence_put(fence); 546 547 adev->uvd.filp[i] = NULL; 548 atomic_set(&adev->uvd.handles[i], 0); 549 } 550 } 551 } 552 553 static void amdgpu_uvd_force_into_vcpu_segment(struct amdgpu_bo *bo) 554 { 555 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 556 struct amdgpu_bo *vcpu_bo = adev->uvd.inst[0].vcpu_bo; 557 struct amdgpu_res_cursor vcpu_cur; 558 559 amdgpu_res_first(vcpu_bo->tbo.resource, 0, 560 amdgpu_bo_size(vcpu_bo), &vcpu_cur); 561 562 bo->placement.num_placement = 1; 563 bo->placement.placement = &bo->placements[0]; 564 bo->placements[0].fpfn = ALIGN_DOWN(vcpu_cur.start, SZ_256M) >> PAGE_SHIFT; 565 bo->placements[0].lpfn = bo->placements[0].fpfn + (SZ_256M >> PAGE_SHIFT); 566 bo->placements[0].mem_type = vcpu_bo->tbo.resource->mem_type; 567 if (bo->placements[0].mem_type == TTM_PL_VRAM) 568 bo->placements[0].flags |= TTM_PL_FLAG_CONTIGUOUS; 569 } 570 571 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 572 { 573 int i; 574 575 for (i = 0; i < abo->placement.num_placement; ++i) { 576 abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 577 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 578 if (abo->placements[i].mem_type == TTM_PL_VRAM) 579 abo->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS; 580 } 581 } 582 583 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) 584 { 585 uint32_t lo, hi; 586 uint64_t addr; 587 588 lo = amdgpu_ib_get_value(ctx->ib, ctx->data0); 589 hi = amdgpu_ib_get_value(ctx->ib, ctx->data1); 590 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 591 592 return addr; 593 } 594 595 /** 596 * amdgpu_uvd_cs_pass1 - first parsing round 597 * 598 * @ctx: UVD parser context 599 * 600 * Make sure UVD message and feedback buffers are in VRAM and 601 * nobody is violating an 256MB boundary. 602 */ 603 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 604 { 605 struct ttm_operation_ctx tctx = { false, false }; 606 struct amdgpu_bo_va_mapping *mapping; 607 struct amdgpu_bo *bo; 608 uint32_t cmd; 609 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 610 int r = 0; 611 612 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 613 if (r) { 614 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 615 return r; 616 } 617 618 if (!ctx->parser->adev->uvd.address_64_bit) { 619 /* check if it's a message or feedback command */ 620 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1; 621 if (cmd == 0x0 || cmd == 0x3) 622 amdgpu_uvd_force_into_vcpu_segment(bo); 623 else 624 amdgpu_uvd_force_into_uvd_segment(bo); 625 626 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); 627 } 628 629 return r; 630 } 631 632 /** 633 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 634 * 635 * @adev: amdgpu_device pointer 636 * @msg: pointer to message structure 637 * @buf_sizes: placeholder to put the different buffer lengths 638 * 639 * Peek into the decode message and calculate the necessary buffer sizes. 640 */ 641 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 642 unsigned int buf_sizes[]) 643 { 644 unsigned int stream_type = msg[4]; 645 unsigned int width = msg[6]; 646 unsigned int height = msg[7]; 647 unsigned int dpb_size = msg[9]; 648 unsigned int pitch = msg[28]; 649 unsigned int level = msg[57]; 650 651 unsigned int width_in_mb = width / 16; 652 unsigned int height_in_mb = ALIGN(height / 16, 2); 653 unsigned int fs_in_mb = width_in_mb * height_in_mb; 654 655 unsigned int image_size, tmp, min_dpb_size, num_dpb_buffer; 656 unsigned int min_ctx_size = ~0; 657 658 /* Reject invalid dimensions to prevent division by zero */ 659 if (width < 16 || height < 16) { 660 dev_WARN_ONCE(adev->dev, 1, 661 "Invalid UVD decoding dimensions (%dx%d)!\n", 662 width, height); 663 return -EINVAL; 664 } 665 666 image_size = width * height; 667 image_size += image_size / 2; 668 image_size = ALIGN(image_size, 1024); 669 670 switch (stream_type) { 671 case 0: /* H264 */ 672 switch (level) { 673 case 30: 674 num_dpb_buffer = 8100 / fs_in_mb; 675 break; 676 case 31: 677 num_dpb_buffer = 18000 / fs_in_mb; 678 break; 679 case 32: 680 num_dpb_buffer = 20480 / fs_in_mb; 681 break; 682 case 41: 683 num_dpb_buffer = 32768 / fs_in_mb; 684 break; 685 case 42: 686 num_dpb_buffer = 34816 / fs_in_mb; 687 break; 688 case 50: 689 num_dpb_buffer = 110400 / fs_in_mb; 690 break; 691 case 51: 692 num_dpb_buffer = 184320 / fs_in_mb; 693 break; 694 default: 695 num_dpb_buffer = 184320 / fs_in_mb; 696 break; 697 } 698 num_dpb_buffer++; 699 if (num_dpb_buffer > 17) 700 num_dpb_buffer = 17; 701 702 /* reference picture buffer */ 703 min_dpb_size = image_size * num_dpb_buffer; 704 705 /* macroblock context buffer */ 706 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 707 708 /* IT surface buffer */ 709 min_dpb_size += width_in_mb * height_in_mb * 32; 710 break; 711 712 case 1: /* VC1 */ 713 714 /* reference picture buffer */ 715 min_dpb_size = image_size * 3; 716 717 /* CONTEXT_BUFFER */ 718 min_dpb_size += width_in_mb * height_in_mb * 128; 719 720 /* IT surface buffer */ 721 min_dpb_size += width_in_mb * 64; 722 723 /* DB surface buffer */ 724 min_dpb_size += width_in_mb * 128; 725 726 /* BP */ 727 tmp = max(width_in_mb, height_in_mb); 728 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 729 break; 730 731 case 3: /* MPEG2 */ 732 733 /* reference picture buffer */ 734 min_dpb_size = image_size * 3; 735 break; 736 737 case 4: /* MPEG4 */ 738 739 /* reference picture buffer */ 740 min_dpb_size = image_size * 3; 741 742 /* CM */ 743 min_dpb_size += width_in_mb * height_in_mb * 64; 744 745 /* IT surface buffer */ 746 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 747 break; 748 749 case 7: /* H264 Perf */ 750 switch (level) { 751 case 30: 752 num_dpb_buffer = 8100 / fs_in_mb; 753 break; 754 case 31: 755 num_dpb_buffer = 18000 / fs_in_mb; 756 break; 757 case 32: 758 num_dpb_buffer = 20480 / fs_in_mb; 759 break; 760 case 41: 761 num_dpb_buffer = 32768 / fs_in_mb; 762 break; 763 case 42: 764 num_dpb_buffer = 34816 / fs_in_mb; 765 break; 766 case 50: 767 num_dpb_buffer = 110400 / fs_in_mb; 768 break; 769 case 51: 770 num_dpb_buffer = 184320 / fs_in_mb; 771 break; 772 default: 773 num_dpb_buffer = 184320 / fs_in_mb; 774 break; 775 } 776 num_dpb_buffer++; 777 if (num_dpb_buffer > 17) 778 num_dpb_buffer = 17; 779 780 /* reference picture buffer */ 781 min_dpb_size = image_size * num_dpb_buffer; 782 783 if (!adev->uvd.use_ctx_buf) { 784 /* macroblock context buffer */ 785 min_dpb_size += 786 width_in_mb * height_in_mb * num_dpb_buffer * 192; 787 788 /* IT surface buffer */ 789 min_dpb_size += width_in_mb * height_in_mb * 32; 790 } else { 791 /* macroblock context buffer */ 792 min_ctx_size = 793 width_in_mb * height_in_mb * num_dpb_buffer * 192; 794 } 795 break; 796 797 case 8: /* MJPEG */ 798 min_dpb_size = 0; 799 break; 800 801 case 16: /* H265 */ 802 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 803 image_size = ALIGN(image_size, 256); 804 805 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 806 min_dpb_size = image_size * num_dpb_buffer; 807 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 808 * 16 * num_dpb_buffer + 52 * 1024; 809 break; 810 811 default: 812 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 813 return -EINVAL; 814 } 815 816 if (width > pitch) { 817 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 818 return -EINVAL; 819 } 820 821 if (dpb_size < min_dpb_size) { 822 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 823 dpb_size, min_dpb_size); 824 return -EINVAL; 825 } 826 827 buf_sizes[0x1] = dpb_size; 828 buf_sizes[0x2] = image_size; 829 buf_sizes[0x4] = min_ctx_size; 830 /* store image width to adjust nb memory pstate */ 831 adev->uvd.decode_image_width = width; 832 return 0; 833 } 834 835 /** 836 * amdgpu_uvd_cs_msg - handle UVD message 837 * 838 * @ctx: UVD parser context 839 * @bo: buffer object containing the message 840 * @offset: offset into the buffer object 841 * 842 * Peek into the UVD message and extract the session id. 843 * Make sure that we don't open up to many sessions. 844 */ 845 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 846 struct amdgpu_bo *bo, unsigned int offset) 847 { 848 struct amdgpu_device *adev = ctx->parser->adev; 849 int32_t *msg, msg_type, handle; 850 void *ptr; 851 long r; 852 int i; 853 854 if (offset & 0x3F) { 855 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 856 return -EINVAL; 857 } 858 859 r = amdgpu_bo_kmap(bo, &ptr); 860 if (r) { 861 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r); 862 return r; 863 } 864 865 msg = ptr + offset; 866 867 msg_type = msg[1]; 868 handle = msg[2]; 869 870 if (handle == 0) { 871 amdgpu_bo_kunmap(bo); 872 DRM_ERROR("Invalid UVD handle!\n"); 873 return -EINVAL; 874 } 875 876 switch (msg_type) { 877 case 0: 878 /* it's a create msg, calc image size (width * height) */ 879 amdgpu_bo_kunmap(bo); 880 881 /* try to alloc a new handle */ 882 for (i = 0; i < adev->uvd.max_handles; ++i) { 883 if (atomic_read(&adev->uvd.handles[i]) == handle) { 884 DRM_ERROR(")Handle 0x%x already in use!\n", 885 handle); 886 return -EINVAL; 887 } 888 889 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 890 adev->uvd.filp[i] = ctx->parser->filp; 891 return 0; 892 } 893 } 894 895 DRM_ERROR("No more free UVD handles!\n"); 896 return -ENOSPC; 897 898 case 1: 899 /* it's a decode msg, calc buffer sizes */ 900 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 901 amdgpu_bo_kunmap(bo); 902 if (r) 903 return r; 904 905 /* validate the handle */ 906 for (i = 0; i < adev->uvd.max_handles; ++i) { 907 if (atomic_read(&adev->uvd.handles[i]) == handle) { 908 if (adev->uvd.filp[i] != ctx->parser->filp) { 909 DRM_ERROR("UVD handle collision detected!\n"); 910 return -EINVAL; 911 } 912 return 0; 913 } 914 } 915 916 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 917 return -ENOENT; 918 919 case 2: 920 /* it's a destroy msg, free the handle */ 921 for (i = 0; i < adev->uvd.max_handles; ++i) 922 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 923 amdgpu_bo_kunmap(bo); 924 return 0; 925 926 default: 927 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 928 } 929 930 amdgpu_bo_kunmap(bo); 931 return -EINVAL; 932 } 933 934 /** 935 * amdgpu_uvd_cs_pass2 - second parsing round 936 * 937 * @ctx: UVD parser context 938 * 939 * Patch buffer addresses, make sure buffer sizes are correct. 940 */ 941 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 942 { 943 struct amdgpu_bo_va_mapping *mapping; 944 struct amdgpu_bo *bo; 945 uint32_t cmd; 946 uint64_t start, end; 947 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 948 int r; 949 950 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 951 if (r) { 952 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 953 return r; 954 } 955 956 start = amdgpu_bo_gpu_offset(bo); 957 958 end = (mapping->last + 1 - mapping->start); 959 end = end * AMDGPU_GPU_PAGE_SIZE + start; 960 961 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; 962 start += addr; 963 964 amdgpu_ib_set_value(ctx->ib, ctx->data0, lower_32_bits(start)); 965 amdgpu_ib_set_value(ctx->ib, ctx->data1, upper_32_bits(start)); 966 967 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1; 968 if (cmd < 0x4) { 969 if ((end - start) < ctx->buf_sizes[cmd]) { 970 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 971 (unsigned int)(end - start), 972 ctx->buf_sizes[cmd]); 973 return -EINVAL; 974 } 975 976 } else if (cmd == 0x206) { 977 if ((end - start) < ctx->buf_sizes[4]) { 978 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 979 (unsigned int)(end - start), 980 ctx->buf_sizes[4]); 981 return -EINVAL; 982 } 983 } else if ((cmd != 0x100) && (cmd != 0x204)) { 984 DRM_ERROR("invalid UVD command %X!\n", cmd); 985 return -EINVAL; 986 } 987 988 if (!ctx->parser->adev->uvd.address_64_bit) { 989 if ((start >> 28) != ((end - 1) >> 28)) { 990 DRM_ERROR("reloc %llx-%llx crossing 256MB boundary!\n", 991 start, end); 992 return -EINVAL; 993 } 994 995 if ((cmd == 0 || cmd == 0x3) && 996 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) { 997 DRM_ERROR("msg/fb buffer %llx-%llx out of 256MB segment!\n", 998 start, end); 999 return -EINVAL; 1000 } 1001 } 1002 1003 if (cmd == 0) { 1004 ctx->has_msg_cmd = true; 1005 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 1006 if (r) 1007 return r; 1008 } else if (!ctx->has_msg_cmd) { 1009 DRM_ERROR("Message needed before other commands are send!\n"); 1010 return -EINVAL; 1011 } 1012 1013 return 0; 1014 } 1015 1016 /** 1017 * amdgpu_uvd_cs_reg - parse register writes 1018 * 1019 * @ctx: UVD parser context 1020 * @cb: callback function 1021 * 1022 * Parse the register writes, call cb on each complete command. 1023 */ 1024 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 1025 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 1026 { 1027 int i, r; 1028 1029 ctx->idx++; 1030 for (i = 0; i <= ctx->count; ++i) { 1031 unsigned int reg = ctx->reg + i; 1032 1033 if (ctx->idx >= ctx->ib->length_dw) { 1034 DRM_ERROR("Register command after end of CS!\n"); 1035 return -EINVAL; 1036 } 1037 1038 switch (reg) { 1039 case mmUVD_GPCOM_VCPU_DATA0: 1040 ctx->data0 = ctx->idx; 1041 break; 1042 case mmUVD_GPCOM_VCPU_DATA1: 1043 ctx->data1 = ctx->idx; 1044 break; 1045 case mmUVD_GPCOM_VCPU_CMD: 1046 r = cb(ctx); 1047 if (r) 1048 return r; 1049 break; 1050 case mmUVD_ENGINE_CNTL: 1051 case mmUVD_NO_OP: 1052 break; 1053 default: 1054 DRM_ERROR("Invalid reg 0x%X!\n", reg); 1055 return -EINVAL; 1056 } 1057 ctx->idx++; 1058 } 1059 return 0; 1060 } 1061 1062 /** 1063 * amdgpu_uvd_cs_packets - parse UVD packets 1064 * 1065 * @ctx: UVD parser context 1066 * @cb: callback function 1067 * 1068 * Parse the command stream packets. 1069 */ 1070 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 1071 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 1072 { 1073 int r; 1074 1075 for (ctx->idx = 0 ; ctx->idx < ctx->ib->length_dw; ) { 1076 uint32_t cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx); 1077 unsigned int type = CP_PACKET_GET_TYPE(cmd); 1078 1079 switch (type) { 1080 case PACKET_TYPE0: 1081 ctx->reg = CP_PACKET0_GET_REG(cmd); 1082 ctx->count = CP_PACKET_GET_COUNT(cmd); 1083 r = amdgpu_uvd_cs_reg(ctx, cb); 1084 if (r) 1085 return r; 1086 break; 1087 case PACKET_TYPE2: 1088 ++ctx->idx; 1089 break; 1090 default: 1091 DRM_ERROR("Unknown packet type %d !\n", type); 1092 return -EINVAL; 1093 } 1094 } 1095 return 0; 1096 } 1097 1098 /** 1099 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 1100 * 1101 * @parser: Command submission parser context 1102 * @job: the job to parse 1103 * @ib: the IB to patch 1104 * 1105 * Parse the command stream, patch in addresses as necessary. 1106 */ 1107 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, 1108 struct amdgpu_job *job, 1109 struct amdgpu_ib *ib) 1110 { 1111 struct amdgpu_uvd_cs_ctx ctx = {}; 1112 unsigned int buf_sizes[] = { 1113 [0x00000000] = 2048, 1114 [0x00000001] = 0xFFFFFFFF, 1115 [0x00000002] = 0xFFFFFFFF, 1116 [0x00000003] = 2048, 1117 [0x00000004] = 0xFFFFFFFF, 1118 }; 1119 int r; 1120 1121 job->vm = NULL; 1122 1123 if (ib->length_dw % 16) { 1124 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 1125 ib->length_dw); 1126 return -EINVAL; 1127 } 1128 1129 ctx.parser = parser; 1130 ctx.buf_sizes = buf_sizes; 1131 ctx.ib = ib; 1132 1133 /* first round only required on chips without UVD 64 bit address support */ 1134 if (!parser->adev->uvd.address_64_bit) { 1135 /* first round, make sure the buffers are actually in the UVD segment */ 1136 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 1137 if (r) 1138 return r; 1139 } 1140 1141 /* second round, patch buffer addresses into the command stream */ 1142 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 1143 if (r) 1144 return r; 1145 1146 if (!ctx.has_msg_cmd) { 1147 DRM_ERROR("UVD-IBs need a msg command!\n"); 1148 return -EINVAL; 1149 } 1150 1151 return 0; 1152 } 1153 1154 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 1155 bool direct, struct dma_fence **fence) 1156 { 1157 struct amdgpu_device *adev = ring->adev; 1158 struct dma_fence *f = NULL; 1159 uint32_t offset, data[4]; 1160 struct amdgpu_job *job; 1161 struct amdgpu_ib *ib; 1162 uint64_t addr; 1163 int i, r; 1164 1165 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->uvd.entity, 1166 AMDGPU_FENCE_OWNER_UNDEFINED, 1167 64, direct ? AMDGPU_IB_POOL_DIRECT : 1168 AMDGPU_IB_POOL_DELAYED, &job, 1169 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); 1170 if (r) 1171 return r; 1172 1173 if (adev->asic_type >= CHIP_VEGA10) 1174 offset = adev->reg_offset[UVD_HWIP][ring->me][1]; 1175 else 1176 offset = UVD_BASE_SI; 1177 1178 data[0] = PACKET0(offset + UVD_GPCOM_VCPU_DATA0, 0); 1179 data[1] = PACKET0(offset + UVD_GPCOM_VCPU_DATA1, 0); 1180 data[2] = PACKET0(offset + UVD_GPCOM_VCPU_CMD, 0); 1181 data[3] = PACKET0(offset + UVD_NO_OP, 0); 1182 1183 ib = &job->ibs[0]; 1184 addr = amdgpu_bo_gpu_offset(bo); 1185 ib->ptr[0] = data[0]; 1186 ib->ptr[1] = addr; 1187 ib->ptr[2] = data[1]; 1188 ib->ptr[3] = addr >> 32; 1189 ib->ptr[4] = data[2]; 1190 ib->ptr[5] = 0; 1191 for (i = 6; i < 16; i += 2) { 1192 ib->ptr[i] = data[3]; 1193 ib->ptr[i+1] = 0; 1194 } 1195 ib->length_dw = 16; 1196 1197 if (direct) { 1198 r = amdgpu_job_submit_direct(job, ring, &f); 1199 if (r) 1200 goto err_free; 1201 } else { 1202 r = drm_sched_job_add_resv_dependencies(&job->base, 1203 bo->tbo.base.resv, 1204 DMA_RESV_USAGE_KERNEL); 1205 if (r) 1206 goto err_free; 1207 1208 f = amdgpu_job_submit(job); 1209 } 1210 1211 amdgpu_bo_reserve(bo, true); 1212 amdgpu_bo_fence(bo, f, false); 1213 amdgpu_bo_unreserve(bo); 1214 1215 if (fence) 1216 *fence = dma_fence_get(f); 1217 dma_fence_put(f); 1218 1219 return 0; 1220 1221 err_free: 1222 amdgpu_job_free(job); 1223 return r; 1224 } 1225 1226 /* multiple fence commands without any stream commands in between can 1227 * crash the vcpu so just try to emmit a dummy create/destroy msg to 1228 * avoid this 1229 */ 1230 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1231 struct dma_fence **fence) 1232 { 1233 struct amdgpu_device *adev = ring->adev; 1234 struct amdgpu_bo *bo = adev->uvd.ib_bo; 1235 uint32_t *msg; 1236 int i; 1237 1238 msg = amdgpu_bo_kptr(bo); 1239 /* stitch together an UVD create msg */ 1240 msg[0] = cpu_to_le32(0x00000de4); 1241 msg[1] = cpu_to_le32(0x00000000); 1242 msg[2] = cpu_to_le32(handle); 1243 msg[3] = cpu_to_le32(0x00000000); 1244 msg[4] = cpu_to_le32(0x00000000); 1245 msg[5] = cpu_to_le32(0x00000000); 1246 msg[6] = cpu_to_le32(0x00000000); 1247 msg[7] = cpu_to_le32(0x00000780); 1248 msg[8] = cpu_to_le32(0x00000440); 1249 msg[9] = cpu_to_le32(0x00000000); 1250 msg[10] = cpu_to_le32(0x01b37000); 1251 for (i = 11; i < 1024; ++i) 1252 msg[i] = cpu_to_le32(0x0); 1253 1254 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1255 1256 } 1257 1258 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1259 bool direct, struct dma_fence **fence) 1260 { 1261 struct amdgpu_device *adev = ring->adev; 1262 struct amdgpu_bo *bo = NULL; 1263 uint32_t *msg; 1264 int r, i; 1265 1266 if (direct) { 1267 bo = adev->uvd.ib_bo; 1268 } else { 1269 r = amdgpu_uvd_create_msg_bo_helper(adev, 4096, &bo); 1270 if (r) 1271 return r; 1272 } 1273 1274 msg = amdgpu_bo_kptr(bo); 1275 /* stitch together an UVD destroy msg */ 1276 msg[0] = cpu_to_le32(0x00000de4); 1277 msg[1] = cpu_to_le32(0x00000002); 1278 msg[2] = cpu_to_le32(handle); 1279 msg[3] = cpu_to_le32(0x00000000); 1280 for (i = 4; i < 1024; ++i) 1281 msg[i] = cpu_to_le32(0x0); 1282 1283 r = amdgpu_uvd_send_msg(ring, bo, direct, fence); 1284 1285 if (!direct) 1286 amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg); 1287 1288 return r; 1289 } 1290 1291 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1292 { 1293 struct amdgpu_device *adev = 1294 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1295 unsigned int fences = 0, i, j; 1296 1297 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1298 if (adev->uvd.harvest_config & (1 << i)) 1299 continue; 1300 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring); 1301 for (j = 0; j < adev->uvd.num_enc_rings; ++j) 1302 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]); 1303 } 1304 1305 if (fences == 0) { 1306 if (adev->pm.dpm_enabled) { 1307 amdgpu_dpm_enable_uvd(adev, false); 1308 } else { 1309 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1310 /* shutdown the UVD block */ 1311 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1312 AMD_PG_STATE_GATE); 1313 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1314 AMD_CG_STATE_GATE); 1315 } 1316 } else { 1317 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1318 } 1319 } 1320 1321 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 1322 { 1323 struct amdgpu_device *adev = ring->adev; 1324 bool set_clocks; 1325 1326 if (amdgpu_sriov_vf(adev)) 1327 return; 1328 1329 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1330 if (set_clocks) { 1331 if (adev->pm.dpm_enabled) { 1332 amdgpu_dpm_enable_uvd(adev, true); 1333 } else { 1334 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1335 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1336 AMD_CG_STATE_UNGATE); 1337 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1338 AMD_PG_STATE_UNGATE); 1339 } 1340 } 1341 } 1342 1343 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) 1344 { 1345 if (!amdgpu_sriov_vf(ring->adev)) 1346 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1347 } 1348 1349 /** 1350 * amdgpu_uvd_ring_test_ib - test ib execution 1351 * 1352 * @ring: amdgpu_ring pointer 1353 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1354 * 1355 * Test if we can successfully execute an IB 1356 */ 1357 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1358 { 1359 struct dma_fence *fence; 1360 long r; 1361 1362 r = amdgpu_uvd_get_create_msg(ring, 1, &fence); 1363 if (r) 1364 goto error; 1365 1366 r = dma_fence_wait_timeout(fence, false, timeout); 1367 dma_fence_put(fence); 1368 if (r == 0) 1369 r = -ETIMEDOUT; 1370 if (r < 0) 1371 goto error; 1372 1373 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 1374 if (r) 1375 goto error; 1376 1377 r = dma_fence_wait_timeout(fence, false, timeout); 1378 if (r == 0) 1379 r = -ETIMEDOUT; 1380 else if (r > 0) 1381 r = 0; 1382 1383 dma_fence_put(fence); 1384 1385 error: 1386 return r; 1387 } 1388 1389 /** 1390 * amdgpu_uvd_used_handles - returns used UVD handles 1391 * 1392 * @adev: amdgpu_device pointer 1393 * 1394 * Returns the number of UVD handles in use 1395 */ 1396 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) 1397 { 1398 unsigned int i; 1399 uint32_t used_handles = 0; 1400 1401 for (i = 0; i < adev->uvd.max_handles; ++i) { 1402 /* 1403 * Handles can be freed in any order, and not 1404 * necessarily linear. So we need to count 1405 * all non-zero handles. 1406 */ 1407 if (atomic_read(&adev->uvd.handles[i])) 1408 used_handles++; 1409 } 1410 1411 return used_handles; 1412 } 1413