1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 34 #include <drm/drm.h> 35 #include <drm/drm_drv.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_pm.h" 39 #include "amdgpu_uvd.h" 40 #include "amdgpu_cs.h" 41 #include "cikd.h" 42 #include "uvd/uvd_4_2_d.h" 43 44 #include "amdgpu_ras.h" 45 46 /* 1 second timeout */ 47 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) 48 49 /* Firmware versions for VI */ 50 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) 51 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) 52 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) 53 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) 54 55 /* Polaris10/11 firmware version */ 56 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 57 58 /* Firmware Names */ 59 #ifdef CONFIG_DRM_AMDGPU_SI 60 #define FIRMWARE_TAHITI "amdgpu/tahiti_uvd.bin" 61 #define FIRMWARE_VERDE "amdgpu/verde_uvd.bin" 62 #define FIRMWARE_PITCAIRN "amdgpu/pitcairn_uvd.bin" 63 #define FIRMWARE_OLAND "amdgpu/oland_uvd.bin" 64 #endif 65 #ifdef CONFIG_DRM_AMDGPU_CIK 66 #define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin" 67 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin" 68 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin" 69 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin" 70 #define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin" 71 #endif 72 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 73 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 74 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 75 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 76 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 77 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 78 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" 79 #define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin" 80 81 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" 82 #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin" 83 #define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin" 84 85 /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */ 86 #define UVD_GPCOM_VCPU_CMD 0x03c3 87 #define UVD_GPCOM_VCPU_DATA0 0x03c4 88 #define UVD_GPCOM_VCPU_DATA1 0x03c5 89 #define UVD_NO_OP 0x03ff 90 #define UVD_BASE_SI 0x3800 91 92 /* 93 * amdgpu_uvd_cs_ctx - Command submission parser context 94 * 95 * Used for emulating virtual memory support on UVD 4.2. 96 */ 97 struct amdgpu_uvd_cs_ctx { 98 struct amdgpu_cs_parser *parser; 99 unsigned reg, count; 100 unsigned data0, data1; 101 unsigned idx; 102 struct amdgpu_ib *ib; 103 104 /* does the IB has a msg command */ 105 bool has_msg_cmd; 106 107 /* minimum buffer sizes */ 108 unsigned *buf_sizes; 109 }; 110 111 #ifdef CONFIG_DRM_AMDGPU_SI 112 MODULE_FIRMWARE(FIRMWARE_TAHITI); 113 MODULE_FIRMWARE(FIRMWARE_VERDE); 114 MODULE_FIRMWARE(FIRMWARE_PITCAIRN); 115 MODULE_FIRMWARE(FIRMWARE_OLAND); 116 #endif 117 #ifdef CONFIG_DRM_AMDGPU_CIK 118 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 119 MODULE_FIRMWARE(FIRMWARE_KABINI); 120 MODULE_FIRMWARE(FIRMWARE_KAVERI); 121 MODULE_FIRMWARE(FIRMWARE_HAWAII); 122 MODULE_FIRMWARE(FIRMWARE_MULLINS); 123 #endif 124 MODULE_FIRMWARE(FIRMWARE_TONGA); 125 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 126 MODULE_FIRMWARE(FIRMWARE_FIJI); 127 MODULE_FIRMWARE(FIRMWARE_STONEY); 128 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 129 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 130 MODULE_FIRMWARE(FIRMWARE_POLARIS12); 131 MODULE_FIRMWARE(FIRMWARE_VEGAM); 132 133 MODULE_FIRMWARE(FIRMWARE_VEGA10); 134 MODULE_FIRMWARE(FIRMWARE_VEGA12); 135 MODULE_FIRMWARE(FIRMWARE_VEGA20); 136 137 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 138 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo); 139 140 static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev, 141 uint32_t size, 142 struct amdgpu_bo **bo_ptr) 143 { 144 struct ttm_operation_ctx ctx = { true, false }; 145 struct amdgpu_bo *bo = NULL; 146 void *addr; 147 int r; 148 149 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, 150 AMDGPU_GEM_DOMAIN_GTT, 151 &bo, NULL, &addr); 152 if (r) 153 return r; 154 155 if (adev->uvd.address_64_bit) 156 goto succ; 157 158 amdgpu_bo_kunmap(bo); 159 amdgpu_bo_unpin(bo); 160 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 161 amdgpu_uvd_force_into_uvd_segment(bo); 162 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 163 if (r) 164 goto err; 165 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM); 166 if (r) 167 goto err_pin; 168 r = amdgpu_bo_kmap(bo, &addr); 169 if (r) 170 goto err_kmap; 171 succ: 172 amdgpu_bo_unreserve(bo); 173 *bo_ptr = bo; 174 return 0; 175 err_kmap: 176 amdgpu_bo_unpin(bo); 177 err_pin: 178 err: 179 amdgpu_bo_unreserve(bo); 180 amdgpu_bo_unref(&bo); 181 return r; 182 } 183 184 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 185 { 186 unsigned long bo_size; 187 const char *fw_name; 188 const struct common_firmware_header *hdr; 189 unsigned family_id; 190 int i, j, r; 191 192 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 193 194 switch (adev->asic_type) { 195 #ifdef CONFIG_DRM_AMDGPU_SI 196 case CHIP_TAHITI: 197 fw_name = FIRMWARE_TAHITI; 198 break; 199 case CHIP_VERDE: 200 fw_name = FIRMWARE_VERDE; 201 break; 202 case CHIP_PITCAIRN: 203 fw_name = FIRMWARE_PITCAIRN; 204 break; 205 case CHIP_OLAND: 206 fw_name = FIRMWARE_OLAND; 207 break; 208 #endif 209 #ifdef CONFIG_DRM_AMDGPU_CIK 210 case CHIP_BONAIRE: 211 fw_name = FIRMWARE_BONAIRE; 212 break; 213 case CHIP_KABINI: 214 fw_name = FIRMWARE_KABINI; 215 break; 216 case CHIP_KAVERI: 217 fw_name = FIRMWARE_KAVERI; 218 break; 219 case CHIP_HAWAII: 220 fw_name = FIRMWARE_HAWAII; 221 break; 222 case CHIP_MULLINS: 223 fw_name = FIRMWARE_MULLINS; 224 break; 225 #endif 226 case CHIP_TONGA: 227 fw_name = FIRMWARE_TONGA; 228 break; 229 case CHIP_FIJI: 230 fw_name = FIRMWARE_FIJI; 231 break; 232 case CHIP_CARRIZO: 233 fw_name = FIRMWARE_CARRIZO; 234 break; 235 case CHIP_STONEY: 236 fw_name = FIRMWARE_STONEY; 237 break; 238 case CHIP_POLARIS10: 239 fw_name = FIRMWARE_POLARIS10; 240 break; 241 case CHIP_POLARIS11: 242 fw_name = FIRMWARE_POLARIS11; 243 break; 244 case CHIP_POLARIS12: 245 fw_name = FIRMWARE_POLARIS12; 246 break; 247 case CHIP_VEGA10: 248 fw_name = FIRMWARE_VEGA10; 249 break; 250 case CHIP_VEGA12: 251 fw_name = FIRMWARE_VEGA12; 252 break; 253 case CHIP_VEGAM: 254 fw_name = FIRMWARE_VEGAM; 255 break; 256 case CHIP_VEGA20: 257 fw_name = FIRMWARE_VEGA20; 258 break; 259 default: 260 return -EINVAL; 261 } 262 263 r = amdgpu_ucode_request(adev, &adev->uvd.fw, fw_name); 264 if (r) { 265 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 266 fw_name); 267 amdgpu_ucode_release(&adev->uvd.fw); 268 return r; 269 } 270 271 /* Set the default UVD handles that the firmware can handle */ 272 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 273 274 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 275 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 276 277 if (adev->asic_type < CHIP_VEGA20) { 278 unsigned version_major, version_minor; 279 280 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 281 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 282 DRM_INFO("Found UVD firmware Version: %u.%u Family ID: %u\n", 283 version_major, version_minor, family_id); 284 285 /* 286 * Limit the number of UVD handles depending on microcode major 287 * and minor versions. The firmware version which has 40 UVD 288 * instances support is 1.80. So all subsequent versions should 289 * also have the same support. 290 */ 291 if ((version_major > 0x01) || 292 ((version_major == 0x01) && (version_minor >= 0x50))) 293 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 294 295 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 296 (family_id << 8)); 297 298 if ((adev->asic_type == CHIP_POLARIS10 || 299 adev->asic_type == CHIP_POLARIS11) && 300 (adev->uvd.fw_version < FW_1_66_16)) 301 DRM_ERROR("POLARIS10/11 UVD firmware version %u.%u is too old.\n", 302 version_major, version_minor); 303 } else { 304 unsigned int enc_major, enc_minor, dec_minor; 305 306 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 307 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f; 308 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3; 309 DRM_INFO("Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n", 310 enc_major, enc_minor, dec_minor, family_id); 311 312 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 313 314 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version); 315 } 316 317 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 318 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 319 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 320 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 321 322 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 323 if (adev->uvd.harvest_config & (1 << j)) 324 continue; 325 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 326 AMDGPU_GEM_DOMAIN_VRAM | 327 AMDGPU_GEM_DOMAIN_GTT, 328 &adev->uvd.inst[j].vcpu_bo, 329 &adev->uvd.inst[j].gpu_addr, 330 &adev->uvd.inst[j].cpu_addr); 331 if (r) { 332 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 333 return r; 334 } 335 } 336 337 for (i = 0; i < adev->uvd.max_handles; ++i) { 338 atomic_set(&adev->uvd.handles[i], 0); 339 adev->uvd.filp[i] = NULL; 340 } 341 342 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 343 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 344 adev->uvd.address_64_bit = true; 345 346 r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo); 347 if (r) 348 return r; 349 350 switch (adev->asic_type) { 351 case CHIP_TONGA: 352 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; 353 break; 354 case CHIP_CARRIZO: 355 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; 356 break; 357 case CHIP_FIJI: 358 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; 359 break; 360 case CHIP_STONEY: 361 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; 362 break; 363 default: 364 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; 365 } 366 367 return 0; 368 } 369 370 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 371 { 372 void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo); 373 int i, j; 374 375 drm_sched_entity_destroy(&adev->uvd.entity); 376 377 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 378 if (adev->uvd.harvest_config & (1 << j)) 379 continue; 380 kvfree(adev->uvd.inst[j].saved_bo); 381 382 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo, 383 &adev->uvd.inst[j].gpu_addr, 384 (void **)&adev->uvd.inst[j].cpu_addr); 385 386 amdgpu_ring_fini(&adev->uvd.inst[j].ring); 387 388 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) 389 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 390 } 391 amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr); 392 amdgpu_ucode_release(&adev->uvd.fw); 393 394 return 0; 395 } 396 397 /** 398 * amdgpu_uvd_entity_init - init entity 399 * 400 * @adev: amdgpu_device pointer 401 * 402 */ 403 int amdgpu_uvd_entity_init(struct amdgpu_device *adev) 404 { 405 struct amdgpu_ring *ring; 406 struct drm_gpu_scheduler *sched; 407 int r; 408 409 ring = &adev->uvd.inst[0].ring; 410 sched = &ring->sched; 411 r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL, 412 &sched, 1, NULL); 413 if (r) { 414 DRM_ERROR("Failed setting up UVD kernel entity.\n"); 415 return r; 416 } 417 418 return 0; 419 } 420 421 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 422 { 423 unsigned size; 424 void *ptr; 425 int i, j, idx; 426 bool in_ras_intr = amdgpu_ras_intr_triggered(); 427 428 cancel_delayed_work_sync(&adev->uvd.idle_work); 429 430 /* only valid for physical mode */ 431 if (adev->asic_type < CHIP_POLARIS10) { 432 for (i = 0; i < adev->uvd.max_handles; ++i) 433 if (atomic_read(&adev->uvd.handles[i])) 434 break; 435 436 if (i == adev->uvd.max_handles) 437 return 0; 438 } 439 440 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 441 if (adev->uvd.harvest_config & (1 << j)) 442 continue; 443 if (adev->uvd.inst[j].vcpu_bo == NULL) 444 continue; 445 446 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo); 447 ptr = adev->uvd.inst[j].cpu_addr; 448 449 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL); 450 if (!adev->uvd.inst[j].saved_bo) 451 return -ENOMEM; 452 453 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 454 /* re-write 0 since err_event_athub will corrupt VCPU buffer */ 455 if (in_ras_intr) 456 memset(adev->uvd.inst[j].saved_bo, 0, size); 457 else 458 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); 459 460 drm_dev_exit(idx); 461 } 462 } 463 464 if (in_ras_intr) 465 DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n"); 466 467 return 0; 468 } 469 470 int amdgpu_uvd_resume(struct amdgpu_device *adev) 471 { 472 unsigned size; 473 void *ptr; 474 int i, idx; 475 476 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 477 if (adev->uvd.harvest_config & (1 << i)) 478 continue; 479 if (adev->uvd.inst[i].vcpu_bo == NULL) 480 return -EINVAL; 481 482 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo); 483 ptr = adev->uvd.inst[i].cpu_addr; 484 485 if (adev->uvd.inst[i].saved_bo != NULL) { 486 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 487 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size); 488 drm_dev_exit(idx); 489 } 490 kvfree(adev->uvd.inst[i].saved_bo); 491 adev->uvd.inst[i].saved_bo = NULL; 492 } else { 493 const struct common_firmware_header *hdr; 494 unsigned offset; 495 496 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 497 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 498 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 499 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 500 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, 501 le32_to_cpu(hdr->ucode_size_bytes)); 502 drm_dev_exit(idx); 503 } 504 size -= le32_to_cpu(hdr->ucode_size_bytes); 505 ptr += le32_to_cpu(hdr->ucode_size_bytes); 506 } 507 memset_io(ptr, 0, size); 508 /* to restore uvd fence seq */ 509 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring); 510 } 511 } 512 return 0; 513 } 514 515 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 516 { 517 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring; 518 int i, r; 519 520 for (i = 0; i < adev->uvd.max_handles; ++i) { 521 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 522 523 if (handle != 0 && adev->uvd.filp[i] == filp) { 524 struct dma_fence *fence; 525 526 r = amdgpu_uvd_get_destroy_msg(ring, handle, false, 527 &fence); 528 if (r) { 529 DRM_ERROR("Error destroying UVD %d!\n", r); 530 continue; 531 } 532 533 dma_fence_wait(fence, false); 534 dma_fence_put(fence); 535 536 adev->uvd.filp[i] = NULL; 537 atomic_set(&adev->uvd.handles[i], 0); 538 } 539 } 540 } 541 542 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 543 { 544 int i; 545 for (i = 0; i < abo->placement.num_placement; ++i) { 546 abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 547 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 548 } 549 } 550 551 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) 552 { 553 uint32_t lo, hi; 554 uint64_t addr; 555 556 lo = amdgpu_ib_get_value(ctx->ib, ctx->data0); 557 hi = amdgpu_ib_get_value(ctx->ib, ctx->data1); 558 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 559 560 return addr; 561 } 562 563 /** 564 * amdgpu_uvd_cs_pass1 - first parsing round 565 * 566 * @ctx: UVD parser context 567 * 568 * Make sure UVD message and feedback buffers are in VRAM and 569 * nobody is violating an 256MB boundary. 570 */ 571 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 572 { 573 struct ttm_operation_ctx tctx = { false, false }; 574 struct amdgpu_bo_va_mapping *mapping; 575 struct amdgpu_bo *bo; 576 uint32_t cmd; 577 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 578 int r = 0; 579 580 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 581 if (r) { 582 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 583 return r; 584 } 585 586 if (!ctx->parser->adev->uvd.address_64_bit) { 587 /* check if it's a message or feedback command */ 588 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1; 589 if (cmd == 0x0 || cmd == 0x3) { 590 /* yes, force it into VRAM */ 591 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 592 amdgpu_bo_placement_from_domain(bo, domain); 593 } 594 amdgpu_uvd_force_into_uvd_segment(bo); 595 596 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); 597 } 598 599 return r; 600 } 601 602 /** 603 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 604 * 605 * @adev: amdgpu_device pointer 606 * @msg: pointer to message structure 607 * @buf_sizes: placeholder to put the different buffer lengths 608 * 609 * Peek into the decode message and calculate the necessary buffer sizes. 610 */ 611 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 612 unsigned buf_sizes[]) 613 { 614 unsigned stream_type = msg[4]; 615 unsigned width = msg[6]; 616 unsigned height = msg[7]; 617 unsigned dpb_size = msg[9]; 618 unsigned pitch = msg[28]; 619 unsigned level = msg[57]; 620 621 unsigned width_in_mb = width / 16; 622 unsigned height_in_mb = ALIGN(height / 16, 2); 623 unsigned fs_in_mb = width_in_mb * height_in_mb; 624 625 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 626 unsigned min_ctx_size = ~0; 627 628 image_size = width * height; 629 image_size += image_size / 2; 630 image_size = ALIGN(image_size, 1024); 631 632 switch (stream_type) { 633 case 0: /* H264 */ 634 switch(level) { 635 case 30: 636 num_dpb_buffer = 8100 / fs_in_mb; 637 break; 638 case 31: 639 num_dpb_buffer = 18000 / fs_in_mb; 640 break; 641 case 32: 642 num_dpb_buffer = 20480 / fs_in_mb; 643 break; 644 case 41: 645 num_dpb_buffer = 32768 / fs_in_mb; 646 break; 647 case 42: 648 num_dpb_buffer = 34816 / fs_in_mb; 649 break; 650 case 50: 651 num_dpb_buffer = 110400 / fs_in_mb; 652 break; 653 case 51: 654 num_dpb_buffer = 184320 / fs_in_mb; 655 break; 656 default: 657 num_dpb_buffer = 184320 / fs_in_mb; 658 break; 659 } 660 num_dpb_buffer++; 661 if (num_dpb_buffer > 17) 662 num_dpb_buffer = 17; 663 664 /* reference picture buffer */ 665 min_dpb_size = image_size * num_dpb_buffer; 666 667 /* macroblock context buffer */ 668 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 669 670 /* IT surface buffer */ 671 min_dpb_size += width_in_mb * height_in_mb * 32; 672 break; 673 674 case 1: /* VC1 */ 675 676 /* reference picture buffer */ 677 min_dpb_size = image_size * 3; 678 679 /* CONTEXT_BUFFER */ 680 min_dpb_size += width_in_mb * height_in_mb * 128; 681 682 /* IT surface buffer */ 683 min_dpb_size += width_in_mb * 64; 684 685 /* DB surface buffer */ 686 min_dpb_size += width_in_mb * 128; 687 688 /* BP */ 689 tmp = max(width_in_mb, height_in_mb); 690 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 691 break; 692 693 case 3: /* MPEG2 */ 694 695 /* reference picture buffer */ 696 min_dpb_size = image_size * 3; 697 break; 698 699 case 4: /* MPEG4 */ 700 701 /* reference picture buffer */ 702 min_dpb_size = image_size * 3; 703 704 /* CM */ 705 min_dpb_size += width_in_mb * height_in_mb * 64; 706 707 /* IT surface buffer */ 708 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 709 break; 710 711 case 7: /* H264 Perf */ 712 switch(level) { 713 case 30: 714 num_dpb_buffer = 8100 / fs_in_mb; 715 break; 716 case 31: 717 num_dpb_buffer = 18000 / fs_in_mb; 718 break; 719 case 32: 720 num_dpb_buffer = 20480 / fs_in_mb; 721 break; 722 case 41: 723 num_dpb_buffer = 32768 / fs_in_mb; 724 break; 725 case 42: 726 num_dpb_buffer = 34816 / fs_in_mb; 727 break; 728 case 50: 729 num_dpb_buffer = 110400 / fs_in_mb; 730 break; 731 case 51: 732 num_dpb_buffer = 184320 / fs_in_mb; 733 break; 734 default: 735 num_dpb_buffer = 184320 / fs_in_mb; 736 break; 737 } 738 num_dpb_buffer++; 739 if (num_dpb_buffer > 17) 740 num_dpb_buffer = 17; 741 742 /* reference picture buffer */ 743 min_dpb_size = image_size * num_dpb_buffer; 744 745 if (!adev->uvd.use_ctx_buf){ 746 /* macroblock context buffer */ 747 min_dpb_size += 748 width_in_mb * height_in_mb * num_dpb_buffer * 192; 749 750 /* IT surface buffer */ 751 min_dpb_size += width_in_mb * height_in_mb * 32; 752 } else { 753 /* macroblock context buffer */ 754 min_ctx_size = 755 width_in_mb * height_in_mb * num_dpb_buffer * 192; 756 } 757 break; 758 759 case 8: /* MJPEG */ 760 min_dpb_size = 0; 761 break; 762 763 case 16: /* H265 */ 764 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 765 image_size = ALIGN(image_size, 256); 766 767 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 768 min_dpb_size = image_size * num_dpb_buffer; 769 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 770 * 16 * num_dpb_buffer + 52 * 1024; 771 break; 772 773 default: 774 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 775 return -EINVAL; 776 } 777 778 if (width > pitch) { 779 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 780 return -EINVAL; 781 } 782 783 if (dpb_size < min_dpb_size) { 784 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 785 dpb_size, min_dpb_size); 786 return -EINVAL; 787 } 788 789 buf_sizes[0x1] = dpb_size; 790 buf_sizes[0x2] = image_size; 791 buf_sizes[0x4] = min_ctx_size; 792 /* store image width to adjust nb memory pstate */ 793 adev->uvd.decode_image_width = width; 794 return 0; 795 } 796 797 /** 798 * amdgpu_uvd_cs_msg - handle UVD message 799 * 800 * @ctx: UVD parser context 801 * @bo: buffer object containing the message 802 * @offset: offset into the buffer object 803 * 804 * Peek into the UVD message and extract the session id. 805 * Make sure that we don't open up to many sessions. 806 */ 807 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 808 struct amdgpu_bo *bo, unsigned offset) 809 { 810 struct amdgpu_device *adev = ctx->parser->adev; 811 int32_t *msg, msg_type, handle; 812 void *ptr; 813 long r; 814 int i; 815 816 if (offset & 0x3F) { 817 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 818 return -EINVAL; 819 } 820 821 r = amdgpu_bo_kmap(bo, &ptr); 822 if (r) { 823 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r); 824 return r; 825 } 826 827 msg = ptr + offset; 828 829 msg_type = msg[1]; 830 handle = msg[2]; 831 832 if (handle == 0) { 833 amdgpu_bo_kunmap(bo); 834 DRM_ERROR("Invalid UVD handle!\n"); 835 return -EINVAL; 836 } 837 838 switch (msg_type) { 839 case 0: 840 /* it's a create msg, calc image size (width * height) */ 841 amdgpu_bo_kunmap(bo); 842 843 /* try to alloc a new handle */ 844 for (i = 0; i < adev->uvd.max_handles; ++i) { 845 if (atomic_read(&adev->uvd.handles[i]) == handle) { 846 DRM_ERROR(")Handle 0x%x already in use!\n", 847 handle); 848 return -EINVAL; 849 } 850 851 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 852 adev->uvd.filp[i] = ctx->parser->filp; 853 return 0; 854 } 855 } 856 857 DRM_ERROR("No more free UVD handles!\n"); 858 return -ENOSPC; 859 860 case 1: 861 /* it's a decode msg, calc buffer sizes */ 862 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 863 amdgpu_bo_kunmap(bo); 864 if (r) 865 return r; 866 867 /* validate the handle */ 868 for (i = 0; i < adev->uvd.max_handles; ++i) { 869 if (atomic_read(&adev->uvd.handles[i]) == handle) { 870 if (adev->uvd.filp[i] != ctx->parser->filp) { 871 DRM_ERROR("UVD handle collision detected!\n"); 872 return -EINVAL; 873 } 874 return 0; 875 } 876 } 877 878 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 879 return -ENOENT; 880 881 case 2: 882 /* it's a destroy msg, free the handle */ 883 for (i = 0; i < adev->uvd.max_handles; ++i) 884 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 885 amdgpu_bo_kunmap(bo); 886 return 0; 887 888 default: 889 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 890 } 891 892 amdgpu_bo_kunmap(bo); 893 return -EINVAL; 894 } 895 896 /** 897 * amdgpu_uvd_cs_pass2 - second parsing round 898 * 899 * @ctx: UVD parser context 900 * 901 * Patch buffer addresses, make sure buffer sizes are correct. 902 */ 903 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 904 { 905 struct amdgpu_bo_va_mapping *mapping; 906 struct amdgpu_bo *bo; 907 uint32_t cmd; 908 uint64_t start, end; 909 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 910 int r; 911 912 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 913 if (r) { 914 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 915 return r; 916 } 917 918 start = amdgpu_bo_gpu_offset(bo); 919 920 end = (mapping->last + 1 - mapping->start); 921 end = end * AMDGPU_GPU_PAGE_SIZE + start; 922 923 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; 924 start += addr; 925 926 amdgpu_ib_set_value(ctx->ib, ctx->data0, lower_32_bits(start)); 927 amdgpu_ib_set_value(ctx->ib, ctx->data1, upper_32_bits(start)); 928 929 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1; 930 if (cmd < 0x4) { 931 if ((end - start) < ctx->buf_sizes[cmd]) { 932 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 933 (unsigned)(end - start), 934 ctx->buf_sizes[cmd]); 935 return -EINVAL; 936 } 937 938 } else if (cmd == 0x206) { 939 if ((end - start) < ctx->buf_sizes[4]) { 940 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 941 (unsigned)(end - start), 942 ctx->buf_sizes[4]); 943 return -EINVAL; 944 } 945 } else if ((cmd != 0x100) && (cmd != 0x204)) { 946 DRM_ERROR("invalid UVD command %X!\n", cmd); 947 return -EINVAL; 948 } 949 950 if (!ctx->parser->adev->uvd.address_64_bit) { 951 if ((start >> 28) != ((end - 1) >> 28)) { 952 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 953 start, end); 954 return -EINVAL; 955 } 956 957 if ((cmd == 0 || cmd == 0x3) && 958 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) { 959 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 960 start, end); 961 return -EINVAL; 962 } 963 } 964 965 if (cmd == 0) { 966 ctx->has_msg_cmd = true; 967 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 968 if (r) 969 return r; 970 } else if (!ctx->has_msg_cmd) { 971 DRM_ERROR("Message needed before other commands are send!\n"); 972 return -EINVAL; 973 } 974 975 return 0; 976 } 977 978 /** 979 * amdgpu_uvd_cs_reg - parse register writes 980 * 981 * @ctx: UVD parser context 982 * @cb: callback function 983 * 984 * Parse the register writes, call cb on each complete command. 985 */ 986 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 987 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 988 { 989 int i, r; 990 991 ctx->idx++; 992 for (i = 0; i <= ctx->count; ++i) { 993 unsigned reg = ctx->reg + i; 994 995 if (ctx->idx >= ctx->ib->length_dw) { 996 DRM_ERROR("Register command after end of CS!\n"); 997 return -EINVAL; 998 } 999 1000 switch (reg) { 1001 case mmUVD_GPCOM_VCPU_DATA0: 1002 ctx->data0 = ctx->idx; 1003 break; 1004 case mmUVD_GPCOM_VCPU_DATA1: 1005 ctx->data1 = ctx->idx; 1006 break; 1007 case mmUVD_GPCOM_VCPU_CMD: 1008 r = cb(ctx); 1009 if (r) 1010 return r; 1011 break; 1012 case mmUVD_ENGINE_CNTL: 1013 case mmUVD_NO_OP: 1014 break; 1015 default: 1016 DRM_ERROR("Invalid reg 0x%X!\n", reg); 1017 return -EINVAL; 1018 } 1019 ctx->idx++; 1020 } 1021 return 0; 1022 } 1023 1024 /** 1025 * amdgpu_uvd_cs_packets - parse UVD packets 1026 * 1027 * @ctx: UVD parser context 1028 * @cb: callback function 1029 * 1030 * Parse the command stream packets. 1031 */ 1032 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 1033 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 1034 { 1035 int r; 1036 1037 for (ctx->idx = 0 ; ctx->idx < ctx->ib->length_dw; ) { 1038 uint32_t cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx); 1039 unsigned type = CP_PACKET_GET_TYPE(cmd); 1040 switch (type) { 1041 case PACKET_TYPE0: 1042 ctx->reg = CP_PACKET0_GET_REG(cmd); 1043 ctx->count = CP_PACKET_GET_COUNT(cmd); 1044 r = amdgpu_uvd_cs_reg(ctx, cb); 1045 if (r) 1046 return r; 1047 break; 1048 case PACKET_TYPE2: 1049 ++ctx->idx; 1050 break; 1051 default: 1052 DRM_ERROR("Unknown packet type %d !\n", type); 1053 return -EINVAL; 1054 } 1055 } 1056 return 0; 1057 } 1058 1059 /** 1060 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 1061 * 1062 * @parser: Command submission parser context 1063 * @job: the job to parse 1064 * @ib: the IB to patch 1065 * 1066 * Parse the command stream, patch in addresses as necessary. 1067 */ 1068 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, 1069 struct amdgpu_job *job, 1070 struct amdgpu_ib *ib) 1071 { 1072 struct amdgpu_uvd_cs_ctx ctx = {}; 1073 unsigned buf_sizes[] = { 1074 [0x00000000] = 2048, 1075 [0x00000001] = 0xFFFFFFFF, 1076 [0x00000002] = 0xFFFFFFFF, 1077 [0x00000003] = 2048, 1078 [0x00000004] = 0xFFFFFFFF, 1079 }; 1080 int r; 1081 1082 job->vm = NULL; 1083 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 1084 1085 if (ib->length_dw % 16) { 1086 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 1087 ib->length_dw); 1088 return -EINVAL; 1089 } 1090 1091 ctx.parser = parser; 1092 ctx.buf_sizes = buf_sizes; 1093 ctx.ib = ib; 1094 1095 /* first round only required on chips without UVD 64 bit address support */ 1096 if (!parser->adev->uvd.address_64_bit) { 1097 /* first round, make sure the buffers are actually in the UVD segment */ 1098 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 1099 if (r) 1100 return r; 1101 } 1102 1103 /* second round, patch buffer addresses into the command stream */ 1104 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 1105 if (r) 1106 return r; 1107 1108 if (!ctx.has_msg_cmd) { 1109 DRM_ERROR("UVD-IBs need a msg command!\n"); 1110 return -EINVAL; 1111 } 1112 1113 return 0; 1114 } 1115 1116 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 1117 bool direct, struct dma_fence **fence) 1118 { 1119 struct amdgpu_device *adev = ring->adev; 1120 struct dma_fence *f = NULL; 1121 struct amdgpu_job *job; 1122 struct amdgpu_ib *ib; 1123 uint32_t data[4]; 1124 uint64_t addr; 1125 long r; 1126 int i; 1127 unsigned offset_idx = 0; 1128 unsigned offset[3] = { UVD_BASE_SI, 0, 0 }; 1129 1130 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->uvd.entity, 1131 AMDGPU_FENCE_OWNER_UNDEFINED, 1132 64, direct ? AMDGPU_IB_POOL_DIRECT : 1133 AMDGPU_IB_POOL_DELAYED, &job); 1134 if (r) 1135 return r; 1136 1137 if (adev->asic_type >= CHIP_VEGA10) { 1138 offset_idx = 1 + ring->me; 1139 offset[1] = adev->reg_offset[UVD_HWIP][0][1]; 1140 offset[2] = adev->reg_offset[UVD_HWIP][1][1]; 1141 } 1142 1143 data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0); 1144 data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0); 1145 data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0); 1146 data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0); 1147 1148 ib = &job->ibs[0]; 1149 addr = amdgpu_bo_gpu_offset(bo); 1150 ib->ptr[0] = data[0]; 1151 ib->ptr[1] = addr; 1152 ib->ptr[2] = data[1]; 1153 ib->ptr[3] = addr >> 32; 1154 ib->ptr[4] = data[2]; 1155 ib->ptr[5] = 0; 1156 for (i = 6; i < 16; i += 2) { 1157 ib->ptr[i] = data[3]; 1158 ib->ptr[i+1] = 0; 1159 } 1160 ib->length_dw = 16; 1161 1162 if (direct) { 1163 r = dma_resv_wait_timeout(bo->tbo.base.resv, 1164 DMA_RESV_USAGE_KERNEL, false, 1165 msecs_to_jiffies(10)); 1166 if (r == 0) 1167 r = -ETIMEDOUT; 1168 if (r < 0) 1169 goto err_free; 1170 1171 r = amdgpu_job_submit_direct(job, ring, &f); 1172 if (r) 1173 goto err_free; 1174 } else { 1175 r = drm_sched_job_add_resv_dependencies(&job->base, 1176 bo->tbo.base.resv, 1177 DMA_RESV_USAGE_KERNEL); 1178 if (r) 1179 goto err_free; 1180 1181 f = amdgpu_job_submit(job); 1182 } 1183 1184 amdgpu_bo_reserve(bo, true); 1185 amdgpu_bo_fence(bo, f, false); 1186 amdgpu_bo_unreserve(bo); 1187 1188 if (fence) 1189 *fence = dma_fence_get(f); 1190 dma_fence_put(f); 1191 1192 return 0; 1193 1194 err_free: 1195 amdgpu_job_free(job); 1196 return r; 1197 } 1198 1199 /* multiple fence commands without any stream commands in between can 1200 crash the vcpu so just try to emmit a dummy create/destroy msg to 1201 avoid this */ 1202 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1203 struct dma_fence **fence) 1204 { 1205 struct amdgpu_device *adev = ring->adev; 1206 struct amdgpu_bo *bo = adev->uvd.ib_bo; 1207 uint32_t *msg; 1208 int i; 1209 1210 msg = amdgpu_bo_kptr(bo); 1211 /* stitch together an UVD create msg */ 1212 msg[0] = cpu_to_le32(0x00000de4); 1213 msg[1] = cpu_to_le32(0x00000000); 1214 msg[2] = cpu_to_le32(handle); 1215 msg[3] = cpu_to_le32(0x00000000); 1216 msg[4] = cpu_to_le32(0x00000000); 1217 msg[5] = cpu_to_le32(0x00000000); 1218 msg[6] = cpu_to_le32(0x00000000); 1219 msg[7] = cpu_to_le32(0x00000780); 1220 msg[8] = cpu_to_le32(0x00000440); 1221 msg[9] = cpu_to_le32(0x00000000); 1222 msg[10] = cpu_to_le32(0x01b37000); 1223 for (i = 11; i < 1024; ++i) 1224 msg[i] = cpu_to_le32(0x0); 1225 1226 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1227 1228 } 1229 1230 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1231 bool direct, struct dma_fence **fence) 1232 { 1233 struct amdgpu_device *adev = ring->adev; 1234 struct amdgpu_bo *bo = NULL; 1235 uint32_t *msg; 1236 int r, i; 1237 1238 if (direct) { 1239 bo = adev->uvd.ib_bo; 1240 } else { 1241 r = amdgpu_uvd_create_msg_bo_helper(adev, 4096, &bo); 1242 if (r) 1243 return r; 1244 } 1245 1246 msg = amdgpu_bo_kptr(bo); 1247 /* stitch together an UVD destroy msg */ 1248 msg[0] = cpu_to_le32(0x00000de4); 1249 msg[1] = cpu_to_le32(0x00000002); 1250 msg[2] = cpu_to_le32(handle); 1251 msg[3] = cpu_to_le32(0x00000000); 1252 for (i = 4; i < 1024; ++i) 1253 msg[i] = cpu_to_le32(0x0); 1254 1255 r = amdgpu_uvd_send_msg(ring, bo, direct, fence); 1256 1257 if (!direct) 1258 amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg); 1259 1260 return r; 1261 } 1262 1263 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1264 { 1265 struct amdgpu_device *adev = 1266 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1267 unsigned fences = 0, i, j; 1268 1269 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1270 if (adev->uvd.harvest_config & (1 << i)) 1271 continue; 1272 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring); 1273 for (j = 0; j < adev->uvd.num_enc_rings; ++j) { 1274 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]); 1275 } 1276 } 1277 1278 if (fences == 0) { 1279 if (adev->pm.dpm_enabled) { 1280 amdgpu_dpm_enable_uvd(adev, false); 1281 } else { 1282 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1283 /* shutdown the UVD block */ 1284 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1285 AMD_PG_STATE_GATE); 1286 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1287 AMD_CG_STATE_GATE); 1288 } 1289 } else { 1290 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1291 } 1292 } 1293 1294 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 1295 { 1296 struct amdgpu_device *adev = ring->adev; 1297 bool set_clocks; 1298 1299 if (amdgpu_sriov_vf(adev)) 1300 return; 1301 1302 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1303 if (set_clocks) { 1304 if (adev->pm.dpm_enabled) { 1305 amdgpu_dpm_enable_uvd(adev, true); 1306 } else { 1307 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1308 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1309 AMD_CG_STATE_UNGATE); 1310 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1311 AMD_PG_STATE_UNGATE); 1312 } 1313 } 1314 } 1315 1316 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) 1317 { 1318 if (!amdgpu_sriov_vf(ring->adev)) 1319 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1320 } 1321 1322 /** 1323 * amdgpu_uvd_ring_test_ib - test ib execution 1324 * 1325 * @ring: amdgpu_ring pointer 1326 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1327 * 1328 * Test if we can successfully execute an IB 1329 */ 1330 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1331 { 1332 struct dma_fence *fence; 1333 long r; 1334 1335 r = amdgpu_uvd_get_create_msg(ring, 1, &fence); 1336 if (r) 1337 goto error; 1338 1339 r = dma_fence_wait_timeout(fence, false, timeout); 1340 dma_fence_put(fence); 1341 if (r == 0) 1342 r = -ETIMEDOUT; 1343 if (r < 0) 1344 goto error; 1345 1346 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 1347 if (r) 1348 goto error; 1349 1350 r = dma_fence_wait_timeout(fence, false, timeout); 1351 if (r == 0) 1352 r = -ETIMEDOUT; 1353 else if (r > 0) 1354 r = 0; 1355 1356 dma_fence_put(fence); 1357 1358 error: 1359 return r; 1360 } 1361 1362 /** 1363 * amdgpu_uvd_used_handles - returns used UVD handles 1364 * 1365 * @adev: amdgpu_device pointer 1366 * 1367 * Returns the number of UVD handles in use 1368 */ 1369 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) 1370 { 1371 unsigned i; 1372 uint32_t used_handles = 0; 1373 1374 for (i = 0; i < adev->uvd.max_handles; ++i) { 1375 /* 1376 * Handles can be freed in any order, and not 1377 * necessarily linear. So we need to count 1378 * all non-zero handles. 1379 */ 1380 if (atomic_read(&adev->uvd.handles[i])) 1381 used_handles++; 1382 } 1383 1384 return used_handles; 1385 } 1386