1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <drm/drmP.h> 34 #include <drm/drm.h> 35 36 #include "amdgpu.h" 37 #include "amdgpu_pm.h" 38 #include "amdgpu_uvd.h" 39 #include "cikd.h" 40 #include "uvd/uvd_4_2_d.h" 41 42 /* 1 second timeout */ 43 #define UVD_IDLE_TIMEOUT_MS 1000 44 45 /* Firmware Names */ 46 #ifdef CONFIG_DRM_AMDGPU_CIK 47 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" 48 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin" 49 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" 50 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" 51 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" 52 #endif 53 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 54 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 55 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 56 57 /** 58 * amdgpu_uvd_cs_ctx - Command submission parser context 59 * 60 * Used for emulating virtual memory support on UVD 4.2. 61 */ 62 struct amdgpu_uvd_cs_ctx { 63 struct amdgpu_cs_parser *parser; 64 unsigned reg, count; 65 unsigned data0, data1; 66 unsigned idx; 67 unsigned ib_idx; 68 69 /* does the IB has a msg command */ 70 bool has_msg_cmd; 71 72 /* minimum buffer sizes */ 73 unsigned *buf_sizes; 74 }; 75 76 #ifdef CONFIG_DRM_AMDGPU_CIK 77 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 78 MODULE_FIRMWARE(FIRMWARE_KABINI); 79 MODULE_FIRMWARE(FIRMWARE_KAVERI); 80 MODULE_FIRMWARE(FIRMWARE_HAWAII); 81 MODULE_FIRMWARE(FIRMWARE_MULLINS); 82 #endif 83 MODULE_FIRMWARE(FIRMWARE_TONGA); 84 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 85 MODULE_FIRMWARE(FIRMWARE_FIJI); 86 87 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev); 88 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 89 90 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 91 { 92 unsigned long bo_size; 93 const char *fw_name; 94 const struct common_firmware_header *hdr; 95 unsigned version_major, version_minor, family_id; 96 int i, r; 97 98 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 99 100 switch (adev->asic_type) { 101 #ifdef CONFIG_DRM_AMDGPU_CIK 102 case CHIP_BONAIRE: 103 fw_name = FIRMWARE_BONAIRE; 104 break; 105 case CHIP_KABINI: 106 fw_name = FIRMWARE_KABINI; 107 break; 108 case CHIP_KAVERI: 109 fw_name = FIRMWARE_KAVERI; 110 break; 111 case CHIP_HAWAII: 112 fw_name = FIRMWARE_HAWAII; 113 break; 114 case CHIP_MULLINS: 115 fw_name = FIRMWARE_MULLINS; 116 break; 117 #endif 118 case CHIP_TONGA: 119 fw_name = FIRMWARE_TONGA; 120 break; 121 case CHIP_FIJI: 122 fw_name = FIRMWARE_FIJI; 123 break; 124 case CHIP_CARRIZO: 125 fw_name = FIRMWARE_CARRIZO; 126 break; 127 default: 128 return -EINVAL; 129 } 130 131 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); 132 if (r) { 133 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", 134 fw_name); 135 return r; 136 } 137 138 r = amdgpu_ucode_validate(adev->uvd.fw); 139 if (r) { 140 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 141 fw_name); 142 release_firmware(adev->uvd.fw); 143 adev->uvd.fw = NULL; 144 return r; 145 } 146 147 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 148 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 149 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 150 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 151 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", 152 version_major, version_minor, family_id); 153 154 bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) 155 + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE; 156 r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true, 157 AMDGPU_GEM_DOMAIN_VRAM, 158 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 159 NULL, NULL, &adev->uvd.vcpu_bo); 160 if (r) { 161 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 162 return r; 163 } 164 165 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); 166 if (r) { 167 amdgpu_bo_unref(&adev->uvd.vcpu_bo); 168 dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r); 169 return r; 170 } 171 172 r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM, 173 &adev->uvd.gpu_addr); 174 if (r) { 175 amdgpu_bo_unreserve(adev->uvd.vcpu_bo); 176 amdgpu_bo_unref(&adev->uvd.vcpu_bo); 177 dev_err(adev->dev, "(%d) UVD bo pin failed\n", r); 178 return r; 179 } 180 181 r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr); 182 if (r) { 183 dev_err(adev->dev, "(%d) UVD map failed\n", r); 184 return r; 185 } 186 187 amdgpu_bo_unreserve(adev->uvd.vcpu_bo); 188 189 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 190 atomic_set(&adev->uvd.handles[i], 0); 191 adev->uvd.filp[i] = NULL; 192 } 193 194 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 195 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 196 adev->uvd.address_64_bit = true; 197 198 return 0; 199 } 200 201 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 202 { 203 int r; 204 205 if (adev->uvd.vcpu_bo == NULL) 206 return 0; 207 208 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); 209 if (!r) { 210 amdgpu_bo_kunmap(adev->uvd.vcpu_bo); 211 amdgpu_bo_unpin(adev->uvd.vcpu_bo); 212 amdgpu_bo_unreserve(adev->uvd.vcpu_bo); 213 } 214 215 amdgpu_bo_unref(&adev->uvd.vcpu_bo); 216 217 amdgpu_ring_fini(&adev->uvd.ring); 218 219 release_firmware(adev->uvd.fw); 220 221 return 0; 222 } 223 224 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 225 { 226 struct amdgpu_ring *ring = &adev->uvd.ring; 227 int i, r; 228 229 if (adev->uvd.vcpu_bo == NULL) 230 return 0; 231 232 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 233 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 234 if (handle != 0) { 235 struct fence *fence; 236 237 amdgpu_uvd_note_usage(adev); 238 239 r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence); 240 if (r) { 241 DRM_ERROR("Error destroying UVD (%d)!\n", r); 242 continue; 243 } 244 245 fence_wait(fence, false); 246 fence_put(fence); 247 248 adev->uvd.filp[i] = NULL; 249 atomic_set(&adev->uvd.handles[i], 0); 250 } 251 } 252 253 return 0; 254 } 255 256 int amdgpu_uvd_resume(struct amdgpu_device *adev) 257 { 258 unsigned size; 259 void *ptr; 260 const struct common_firmware_header *hdr; 261 unsigned offset; 262 263 if (adev->uvd.vcpu_bo == NULL) 264 return -EINVAL; 265 266 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 267 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 268 memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset, 269 (adev->uvd.fw->size) - offset); 270 271 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 272 size -= le32_to_cpu(hdr->ucode_size_bytes); 273 ptr = adev->uvd.cpu_addr; 274 ptr += le32_to_cpu(hdr->ucode_size_bytes); 275 276 memset(ptr, 0, size); 277 278 return 0; 279 } 280 281 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 282 { 283 struct amdgpu_ring *ring = &adev->uvd.ring; 284 int i, r; 285 286 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 287 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 288 if (handle != 0 && adev->uvd.filp[i] == filp) { 289 struct fence *fence; 290 291 amdgpu_uvd_note_usage(adev); 292 293 r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence); 294 if (r) { 295 DRM_ERROR("Error destroying UVD (%d)!\n", r); 296 continue; 297 } 298 299 fence_wait(fence, false); 300 fence_put(fence); 301 302 adev->uvd.filp[i] = NULL; 303 atomic_set(&adev->uvd.handles[i], 0); 304 } 305 } 306 } 307 308 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo) 309 { 310 int i; 311 for (i = 0; i < rbo->placement.num_placement; ++i) { 312 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; 313 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 314 } 315 } 316 317 /** 318 * amdgpu_uvd_cs_pass1 - first parsing round 319 * 320 * @ctx: UVD parser context 321 * 322 * Make sure UVD message and feedback buffers are in VRAM and 323 * nobody is violating an 256MB boundary. 324 */ 325 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 326 { 327 struct amdgpu_bo_va_mapping *mapping; 328 struct amdgpu_bo *bo; 329 uint32_t cmd, lo, hi; 330 uint64_t addr; 331 int r = 0; 332 333 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 334 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 335 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 336 337 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); 338 if (mapping == NULL) { 339 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 340 return -EINVAL; 341 } 342 343 if (!ctx->parser->adev->uvd.address_64_bit) { 344 /* check if it's a message or feedback command */ 345 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 346 if (cmd == 0x0 || cmd == 0x3) { 347 /* yes, force it into VRAM */ 348 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 349 amdgpu_ttm_placement_from_domain(bo, domain); 350 } 351 amdgpu_uvd_force_into_uvd_segment(bo); 352 353 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 354 } 355 356 return r; 357 } 358 359 /** 360 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 361 * 362 * @msg: pointer to message structure 363 * @buf_sizes: returned buffer sizes 364 * 365 * Peek into the decode message and calculate the necessary buffer sizes. 366 */ 367 static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) 368 { 369 unsigned stream_type = msg[4]; 370 unsigned width = msg[6]; 371 unsigned height = msg[7]; 372 unsigned dpb_size = msg[9]; 373 unsigned pitch = msg[28]; 374 unsigned level = msg[57]; 375 376 unsigned width_in_mb = width / 16; 377 unsigned height_in_mb = ALIGN(height / 16, 2); 378 unsigned fs_in_mb = width_in_mb * height_in_mb; 379 380 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 381 unsigned min_ctx_size = 0; 382 383 image_size = width * height; 384 image_size += image_size / 2; 385 image_size = ALIGN(image_size, 1024); 386 387 switch (stream_type) { 388 case 0: /* H264 */ 389 case 7: /* H264 Perf */ 390 switch(level) { 391 case 30: 392 num_dpb_buffer = 8100 / fs_in_mb; 393 break; 394 case 31: 395 num_dpb_buffer = 18000 / fs_in_mb; 396 break; 397 case 32: 398 num_dpb_buffer = 20480 / fs_in_mb; 399 break; 400 case 41: 401 num_dpb_buffer = 32768 / fs_in_mb; 402 break; 403 case 42: 404 num_dpb_buffer = 34816 / fs_in_mb; 405 break; 406 case 50: 407 num_dpb_buffer = 110400 / fs_in_mb; 408 break; 409 case 51: 410 num_dpb_buffer = 184320 / fs_in_mb; 411 break; 412 default: 413 num_dpb_buffer = 184320 / fs_in_mb; 414 break; 415 } 416 num_dpb_buffer++; 417 if (num_dpb_buffer > 17) 418 num_dpb_buffer = 17; 419 420 /* reference picture buffer */ 421 min_dpb_size = image_size * num_dpb_buffer; 422 423 /* macroblock context buffer */ 424 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 425 426 /* IT surface buffer */ 427 min_dpb_size += width_in_mb * height_in_mb * 32; 428 break; 429 430 case 1: /* VC1 */ 431 432 /* reference picture buffer */ 433 min_dpb_size = image_size * 3; 434 435 /* CONTEXT_BUFFER */ 436 min_dpb_size += width_in_mb * height_in_mb * 128; 437 438 /* IT surface buffer */ 439 min_dpb_size += width_in_mb * 64; 440 441 /* DB surface buffer */ 442 min_dpb_size += width_in_mb * 128; 443 444 /* BP */ 445 tmp = max(width_in_mb, height_in_mb); 446 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 447 break; 448 449 case 3: /* MPEG2 */ 450 451 /* reference picture buffer */ 452 min_dpb_size = image_size * 3; 453 break; 454 455 case 4: /* MPEG4 */ 456 457 /* reference picture buffer */ 458 min_dpb_size = image_size * 3; 459 460 /* CM */ 461 min_dpb_size += width_in_mb * height_in_mb * 64; 462 463 /* IT surface buffer */ 464 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 465 break; 466 467 case 16: /* H265 */ 468 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 469 image_size = ALIGN(image_size, 256); 470 471 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 472 min_dpb_size = image_size * num_dpb_buffer; 473 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 474 * 16 * num_dpb_buffer + 52 * 1024; 475 break; 476 477 default: 478 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 479 return -EINVAL; 480 } 481 482 if (width > pitch) { 483 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 484 return -EINVAL; 485 } 486 487 if (dpb_size < min_dpb_size) { 488 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 489 dpb_size, min_dpb_size); 490 return -EINVAL; 491 } 492 493 buf_sizes[0x1] = dpb_size; 494 buf_sizes[0x2] = image_size; 495 buf_sizes[0x4] = min_ctx_size; 496 return 0; 497 } 498 499 /** 500 * amdgpu_uvd_cs_msg - handle UVD message 501 * 502 * @ctx: UVD parser context 503 * @bo: buffer object containing the message 504 * @offset: offset into the buffer object 505 * 506 * Peek into the UVD message and extract the session id. 507 * Make sure that we don't open up to many sessions. 508 */ 509 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 510 struct amdgpu_bo *bo, unsigned offset) 511 { 512 struct amdgpu_device *adev = ctx->parser->adev; 513 int32_t *msg, msg_type, handle; 514 void *ptr; 515 long r; 516 int i; 517 518 if (offset & 0x3F) { 519 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 520 return -EINVAL; 521 } 522 523 r = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false, 524 MAX_SCHEDULE_TIMEOUT); 525 if (r < 0) { 526 DRM_ERROR("Failed waiting for UVD message (%ld)!\n", r); 527 return r; 528 } 529 530 r = amdgpu_bo_kmap(bo, &ptr); 531 if (r) { 532 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r); 533 return r; 534 } 535 536 msg = ptr + offset; 537 538 msg_type = msg[1]; 539 handle = msg[2]; 540 541 if (handle == 0) { 542 DRM_ERROR("Invalid UVD handle!\n"); 543 return -EINVAL; 544 } 545 546 switch (msg_type) { 547 case 0: 548 /* it's a create msg, calc image size (width * height) */ 549 amdgpu_bo_kunmap(bo); 550 551 /* try to alloc a new handle */ 552 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 553 if (atomic_read(&adev->uvd.handles[i]) == handle) { 554 DRM_ERROR("Handle 0x%x already in use!\n", handle); 555 return -EINVAL; 556 } 557 558 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 559 adev->uvd.filp[i] = ctx->parser->filp; 560 return 0; 561 } 562 } 563 564 DRM_ERROR("No more free UVD handles!\n"); 565 return -EINVAL; 566 567 case 1: 568 /* it's a decode msg, calc buffer sizes */ 569 r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes); 570 amdgpu_bo_kunmap(bo); 571 if (r) 572 return r; 573 574 /* validate the handle */ 575 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 576 if (atomic_read(&adev->uvd.handles[i]) == handle) { 577 if (adev->uvd.filp[i] != ctx->parser->filp) { 578 DRM_ERROR("UVD handle collision detected!\n"); 579 return -EINVAL; 580 } 581 return 0; 582 } 583 } 584 585 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 586 return -ENOENT; 587 588 case 2: 589 /* it's a destroy msg, free the handle */ 590 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) 591 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 592 amdgpu_bo_kunmap(bo); 593 return 0; 594 595 default: 596 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 597 return -EINVAL; 598 } 599 BUG(); 600 return -EINVAL; 601 } 602 603 /** 604 * amdgpu_uvd_cs_pass2 - second parsing round 605 * 606 * @ctx: UVD parser context 607 * 608 * Patch buffer addresses, make sure buffer sizes are correct. 609 */ 610 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 611 { 612 struct amdgpu_bo_va_mapping *mapping; 613 struct amdgpu_bo *bo; 614 struct amdgpu_ib *ib; 615 uint32_t cmd, lo, hi; 616 uint64_t start, end; 617 uint64_t addr; 618 int r; 619 620 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 621 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 622 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 623 624 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); 625 if (mapping == NULL) 626 return -EINVAL; 627 628 start = amdgpu_bo_gpu_offset(bo); 629 630 end = (mapping->it.last + 1 - mapping->it.start); 631 end = end * AMDGPU_GPU_PAGE_SIZE + start; 632 633 addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE; 634 start += addr; 635 636 ib = &ctx->parser->ibs[ctx->ib_idx]; 637 ib->ptr[ctx->data0] = start & 0xFFFFFFFF; 638 ib->ptr[ctx->data1] = start >> 32; 639 640 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 641 if (cmd < 0x4) { 642 if ((end - start) < ctx->buf_sizes[cmd]) { 643 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 644 (unsigned)(end - start), 645 ctx->buf_sizes[cmd]); 646 return -EINVAL; 647 } 648 649 } else if (cmd == 0x206) { 650 if ((end - start) < ctx->buf_sizes[4]) { 651 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 652 (unsigned)(end - start), 653 ctx->buf_sizes[4]); 654 return -EINVAL; 655 } 656 } else if ((cmd != 0x100) && (cmd != 0x204)) { 657 DRM_ERROR("invalid UVD command %X!\n", cmd); 658 return -EINVAL; 659 } 660 661 if (!ctx->parser->adev->uvd.address_64_bit) { 662 if ((start >> 28) != ((end - 1) >> 28)) { 663 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 664 start, end); 665 return -EINVAL; 666 } 667 668 if ((cmd == 0 || cmd == 0x3) && 669 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) { 670 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 671 start, end); 672 return -EINVAL; 673 } 674 } 675 676 if (cmd == 0) { 677 ctx->has_msg_cmd = true; 678 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 679 if (r) 680 return r; 681 } else if (!ctx->has_msg_cmd) { 682 DRM_ERROR("Message needed before other commands are send!\n"); 683 return -EINVAL; 684 } 685 686 return 0; 687 } 688 689 /** 690 * amdgpu_uvd_cs_reg - parse register writes 691 * 692 * @ctx: UVD parser context 693 * @cb: callback function 694 * 695 * Parse the register writes, call cb on each complete command. 696 */ 697 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 698 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 699 { 700 struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx]; 701 int i, r; 702 703 ctx->idx++; 704 for (i = 0; i <= ctx->count; ++i) { 705 unsigned reg = ctx->reg + i; 706 707 if (ctx->idx >= ib->length_dw) { 708 DRM_ERROR("Register command after end of CS!\n"); 709 return -EINVAL; 710 } 711 712 switch (reg) { 713 case mmUVD_GPCOM_VCPU_DATA0: 714 ctx->data0 = ctx->idx; 715 break; 716 case mmUVD_GPCOM_VCPU_DATA1: 717 ctx->data1 = ctx->idx; 718 break; 719 case mmUVD_GPCOM_VCPU_CMD: 720 r = cb(ctx); 721 if (r) 722 return r; 723 break; 724 case mmUVD_ENGINE_CNTL: 725 break; 726 default: 727 DRM_ERROR("Invalid reg 0x%X!\n", reg); 728 return -EINVAL; 729 } 730 ctx->idx++; 731 } 732 return 0; 733 } 734 735 /** 736 * amdgpu_uvd_cs_packets - parse UVD packets 737 * 738 * @ctx: UVD parser context 739 * @cb: callback function 740 * 741 * Parse the command stream packets. 742 */ 743 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 744 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 745 { 746 struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx]; 747 int r; 748 749 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { 750 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); 751 unsigned type = CP_PACKET_GET_TYPE(cmd); 752 switch (type) { 753 case PACKET_TYPE0: 754 ctx->reg = CP_PACKET0_GET_REG(cmd); 755 ctx->count = CP_PACKET_GET_COUNT(cmd); 756 r = amdgpu_uvd_cs_reg(ctx, cb); 757 if (r) 758 return r; 759 break; 760 case PACKET_TYPE2: 761 ++ctx->idx; 762 break; 763 default: 764 DRM_ERROR("Unknown packet type %d !\n", type); 765 return -EINVAL; 766 } 767 } 768 return 0; 769 } 770 771 /** 772 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 773 * 774 * @parser: Command submission parser context 775 * 776 * Parse the command stream, patch in addresses as necessary. 777 */ 778 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) 779 { 780 struct amdgpu_uvd_cs_ctx ctx = {}; 781 unsigned buf_sizes[] = { 782 [0x00000000] = 2048, 783 [0x00000001] = 0xFFFFFFFF, 784 [0x00000002] = 0xFFFFFFFF, 785 [0x00000003] = 2048, 786 [0x00000004] = 0xFFFFFFFF, 787 }; 788 struct amdgpu_ib *ib = &parser->ibs[ib_idx]; 789 int r; 790 791 if (ib->length_dw % 16) { 792 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 793 ib->length_dw); 794 return -EINVAL; 795 } 796 797 ctx.parser = parser; 798 ctx.buf_sizes = buf_sizes; 799 ctx.ib_idx = ib_idx; 800 801 /* first round, make sure the buffers are actually in the UVD segment */ 802 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 803 if (r) 804 return r; 805 806 /* second round, patch buffer addresses into the command stream */ 807 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 808 if (r) 809 return r; 810 811 if (!ctx.has_msg_cmd) { 812 DRM_ERROR("UVD-IBs need a msg command!\n"); 813 return -EINVAL; 814 } 815 816 amdgpu_uvd_note_usage(ctx.parser->adev); 817 818 return 0; 819 } 820 821 static int amdgpu_uvd_free_job( 822 struct amdgpu_job *job) 823 { 824 amdgpu_ib_free(job->adev, job->ibs); 825 kfree(job->ibs); 826 return 0; 827 } 828 829 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, 830 struct amdgpu_bo *bo, 831 struct fence **fence) 832 { 833 struct ttm_validate_buffer tv; 834 struct ww_acquire_ctx ticket; 835 struct list_head head; 836 struct amdgpu_ib *ib = NULL; 837 struct fence *f = NULL; 838 struct amdgpu_device *adev = ring->adev; 839 uint64_t addr; 840 int i, r; 841 842 memset(&tv, 0, sizeof(tv)); 843 tv.bo = &bo->tbo; 844 845 INIT_LIST_HEAD(&head); 846 list_add(&tv.head, &head); 847 848 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL); 849 if (r) 850 return r; 851 852 if (!bo->adev->uvd.address_64_bit) { 853 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 854 amdgpu_uvd_force_into_uvd_segment(bo); 855 } 856 857 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 858 if (r) 859 goto err; 860 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); 861 if (!ib) { 862 r = -ENOMEM; 863 goto err; 864 } 865 r = amdgpu_ib_get(ring, NULL, 64, ib); 866 if (r) 867 goto err1; 868 869 addr = amdgpu_bo_gpu_offset(bo); 870 ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); 871 ib->ptr[1] = addr; 872 ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); 873 ib->ptr[3] = addr >> 32; 874 ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); 875 ib->ptr[5] = 0; 876 for (i = 6; i < 16; ++i) 877 ib->ptr[i] = PACKET2(0); 878 ib->length_dw = 16; 879 880 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, 881 &amdgpu_uvd_free_job, 882 AMDGPU_FENCE_OWNER_UNDEFINED, 883 &f); 884 if (r) 885 goto err2; 886 887 ttm_eu_fence_buffer_objects(&ticket, &head, f); 888 889 if (fence) 890 *fence = fence_get(f); 891 amdgpu_bo_unref(&bo); 892 fence_put(f); 893 if (amdgpu_enable_scheduler) 894 return 0; 895 896 amdgpu_ib_free(ring->adev, ib); 897 kfree(ib); 898 return 0; 899 err2: 900 amdgpu_ib_free(ring->adev, ib); 901 err1: 902 kfree(ib); 903 err: 904 ttm_eu_backoff_reservation(&ticket, &head); 905 return r; 906 } 907 908 /* multiple fence commands without any stream commands in between can 909 crash the vcpu so just try to emmit a dummy create/destroy msg to 910 avoid this */ 911 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 912 struct fence **fence) 913 { 914 struct amdgpu_device *adev = ring->adev; 915 struct amdgpu_bo *bo; 916 uint32_t *msg; 917 int r, i; 918 919 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, 920 AMDGPU_GEM_DOMAIN_VRAM, 921 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 922 NULL, NULL, &bo); 923 if (r) 924 return r; 925 926 r = amdgpu_bo_reserve(bo, false); 927 if (r) { 928 amdgpu_bo_unref(&bo); 929 return r; 930 } 931 932 r = amdgpu_bo_kmap(bo, (void **)&msg); 933 if (r) { 934 amdgpu_bo_unreserve(bo); 935 amdgpu_bo_unref(&bo); 936 return r; 937 } 938 939 /* stitch together an UVD create msg */ 940 msg[0] = cpu_to_le32(0x00000de4); 941 msg[1] = cpu_to_le32(0x00000000); 942 msg[2] = cpu_to_le32(handle); 943 msg[3] = cpu_to_le32(0x00000000); 944 msg[4] = cpu_to_le32(0x00000000); 945 msg[5] = cpu_to_le32(0x00000000); 946 msg[6] = cpu_to_le32(0x00000000); 947 msg[7] = cpu_to_le32(0x00000780); 948 msg[8] = cpu_to_le32(0x00000440); 949 msg[9] = cpu_to_le32(0x00000000); 950 msg[10] = cpu_to_le32(0x01b37000); 951 for (i = 11; i < 1024; ++i) 952 msg[i] = cpu_to_le32(0x0); 953 954 amdgpu_bo_kunmap(bo); 955 amdgpu_bo_unreserve(bo); 956 957 return amdgpu_uvd_send_msg(ring, bo, fence); 958 } 959 960 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 961 struct fence **fence) 962 { 963 struct amdgpu_device *adev = ring->adev; 964 struct amdgpu_bo *bo; 965 uint32_t *msg; 966 int r, i; 967 968 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, 969 AMDGPU_GEM_DOMAIN_VRAM, 970 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 971 NULL, NULL, &bo); 972 if (r) 973 return r; 974 975 r = amdgpu_bo_reserve(bo, false); 976 if (r) { 977 amdgpu_bo_unref(&bo); 978 return r; 979 } 980 981 r = amdgpu_bo_kmap(bo, (void **)&msg); 982 if (r) { 983 amdgpu_bo_unreserve(bo); 984 amdgpu_bo_unref(&bo); 985 return r; 986 } 987 988 /* stitch together an UVD destroy msg */ 989 msg[0] = cpu_to_le32(0x00000de4); 990 msg[1] = cpu_to_le32(0x00000002); 991 msg[2] = cpu_to_le32(handle); 992 msg[3] = cpu_to_le32(0x00000000); 993 for (i = 4; i < 1024; ++i) 994 msg[i] = cpu_to_le32(0x0); 995 996 amdgpu_bo_kunmap(bo); 997 amdgpu_bo_unreserve(bo); 998 999 return amdgpu_uvd_send_msg(ring, bo, fence); 1000 } 1001 1002 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1003 { 1004 struct amdgpu_device *adev = 1005 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1006 unsigned i, fences, handles = 0; 1007 1008 fences = amdgpu_fence_count_emitted(&adev->uvd.ring); 1009 1010 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) 1011 if (atomic_read(&adev->uvd.handles[i])) 1012 ++handles; 1013 1014 if (fences == 0 && handles == 0) { 1015 if (adev->pm.dpm_enabled) { 1016 amdgpu_dpm_enable_uvd(adev, false); 1017 } else { 1018 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1019 } 1020 } else { 1021 schedule_delayed_work(&adev->uvd.idle_work, 1022 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 1023 } 1024 } 1025 1026 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev) 1027 { 1028 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1029 set_clocks &= schedule_delayed_work(&adev->uvd.idle_work, 1030 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 1031 1032 if (set_clocks) { 1033 if (adev->pm.dpm_enabled) { 1034 amdgpu_dpm_enable_uvd(adev, true); 1035 } else { 1036 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1037 } 1038 } 1039 } 1040