1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 34 #include <drm/drm.h> 35 #include <drm/drm_drv.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_pm.h" 39 #include "amdgpu_uvd.h" 40 #include "amdgpu_cs.h" 41 #include "cikd.h" 42 #include "uvd/uvd_4_2_d.h" 43 44 #include "amdgpu_ras.h" 45 46 /* 1 second timeout */ 47 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) 48 49 /* Firmware versions for VI */ 50 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) 51 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) 52 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) 53 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) 54 55 /* Polaris10/11 firmware version */ 56 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 57 58 /* Firmware Names */ 59 #ifdef CONFIG_DRM_AMDGPU_SI 60 #define FIRMWARE_TAHITI "amdgpu/tahiti_uvd.bin" 61 #define FIRMWARE_VERDE "amdgpu/verde_uvd.bin" 62 #define FIRMWARE_PITCAIRN "amdgpu/pitcairn_uvd.bin" 63 #define FIRMWARE_OLAND "amdgpu/oland_uvd.bin" 64 #endif 65 #ifdef CONFIG_DRM_AMDGPU_CIK 66 #define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin" 67 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin" 68 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin" 69 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin" 70 #define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin" 71 #endif 72 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 73 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 74 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 75 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 76 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 77 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 78 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" 79 #define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin" 80 81 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" 82 #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin" 83 #define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin" 84 85 /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */ 86 #define UVD_GPCOM_VCPU_CMD 0x03c3 87 #define UVD_GPCOM_VCPU_DATA0 0x03c4 88 #define UVD_GPCOM_VCPU_DATA1 0x03c5 89 #define UVD_NO_OP 0x03ff 90 #define UVD_BASE_SI 0x3800 91 92 /* 93 * amdgpu_uvd_cs_ctx - Command submission parser context 94 * 95 * Used for emulating virtual memory support on UVD 4.2. 96 */ 97 struct amdgpu_uvd_cs_ctx { 98 struct amdgpu_cs_parser *parser; 99 unsigned int reg, count; 100 unsigned int data0, data1; 101 unsigned int idx; 102 struct amdgpu_ib *ib; 103 104 /* does the IB has a msg command */ 105 bool has_msg_cmd; 106 107 /* minimum buffer sizes */ 108 unsigned int *buf_sizes; 109 }; 110 111 #ifdef CONFIG_DRM_AMDGPU_SI 112 MODULE_FIRMWARE(FIRMWARE_TAHITI); 113 MODULE_FIRMWARE(FIRMWARE_VERDE); 114 MODULE_FIRMWARE(FIRMWARE_PITCAIRN); 115 MODULE_FIRMWARE(FIRMWARE_OLAND); 116 #endif 117 #ifdef CONFIG_DRM_AMDGPU_CIK 118 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 119 MODULE_FIRMWARE(FIRMWARE_KABINI); 120 MODULE_FIRMWARE(FIRMWARE_KAVERI); 121 MODULE_FIRMWARE(FIRMWARE_HAWAII); 122 MODULE_FIRMWARE(FIRMWARE_MULLINS); 123 #endif 124 MODULE_FIRMWARE(FIRMWARE_TONGA); 125 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 126 MODULE_FIRMWARE(FIRMWARE_FIJI); 127 MODULE_FIRMWARE(FIRMWARE_STONEY); 128 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 129 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 130 MODULE_FIRMWARE(FIRMWARE_POLARIS12); 131 MODULE_FIRMWARE(FIRMWARE_VEGAM); 132 133 MODULE_FIRMWARE(FIRMWARE_VEGA10); 134 MODULE_FIRMWARE(FIRMWARE_VEGA12); 135 MODULE_FIRMWARE(FIRMWARE_VEGA20); 136 137 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 138 static void amdgpu_uvd_force_into_vcpu_segment(struct amdgpu_bo *abo); 139 140 static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev, 141 uint32_t size, 142 struct amdgpu_bo **bo_ptr) 143 { 144 struct ttm_operation_ctx ctx = { true, false }; 145 struct amdgpu_bo *bo = NULL; 146 void *addr; 147 int r; 148 149 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, 150 AMDGPU_GEM_DOMAIN_GTT, 151 &bo, NULL, &addr); 152 if (r) 153 return r; 154 155 if (adev->uvd.address_64_bit) 156 goto succ; 157 158 amdgpu_bo_kunmap(bo); 159 amdgpu_bo_unpin(bo); 160 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 161 amdgpu_uvd_force_into_vcpu_segment(bo); 162 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 163 if (r) 164 goto err; 165 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM); 166 if (r) 167 goto err_pin; 168 r = amdgpu_bo_kmap(bo, &addr); 169 if (r) 170 goto err_kmap; 171 succ: 172 amdgpu_bo_unreserve(bo); 173 *bo_ptr = bo; 174 return 0; 175 err_kmap: 176 amdgpu_bo_unpin(bo); 177 err_pin: 178 err: 179 amdgpu_bo_unreserve(bo); 180 amdgpu_bo_unref(&bo); 181 return r; 182 } 183 184 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 185 { 186 unsigned long bo_size; 187 const char *fw_name; 188 const struct common_firmware_header *hdr; 189 unsigned int family_id; 190 int i, j, r; 191 u32 vcpu_bo_domain; 192 193 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 194 195 switch (adev->asic_type) { 196 #ifdef CONFIG_DRM_AMDGPU_SI 197 case CHIP_TAHITI: 198 fw_name = FIRMWARE_TAHITI; 199 break; 200 case CHIP_VERDE: 201 fw_name = FIRMWARE_VERDE; 202 break; 203 case CHIP_PITCAIRN: 204 fw_name = FIRMWARE_PITCAIRN; 205 break; 206 case CHIP_OLAND: 207 fw_name = FIRMWARE_OLAND; 208 break; 209 #endif 210 #ifdef CONFIG_DRM_AMDGPU_CIK 211 case CHIP_BONAIRE: 212 fw_name = FIRMWARE_BONAIRE; 213 break; 214 case CHIP_KABINI: 215 fw_name = FIRMWARE_KABINI; 216 break; 217 case CHIP_KAVERI: 218 fw_name = FIRMWARE_KAVERI; 219 break; 220 case CHIP_HAWAII: 221 fw_name = FIRMWARE_HAWAII; 222 break; 223 case CHIP_MULLINS: 224 fw_name = FIRMWARE_MULLINS; 225 break; 226 #endif 227 case CHIP_TONGA: 228 fw_name = FIRMWARE_TONGA; 229 break; 230 case CHIP_FIJI: 231 fw_name = FIRMWARE_FIJI; 232 break; 233 case CHIP_CARRIZO: 234 fw_name = FIRMWARE_CARRIZO; 235 break; 236 case CHIP_STONEY: 237 fw_name = FIRMWARE_STONEY; 238 break; 239 case CHIP_POLARIS10: 240 fw_name = FIRMWARE_POLARIS10; 241 break; 242 case CHIP_POLARIS11: 243 fw_name = FIRMWARE_POLARIS11; 244 break; 245 case CHIP_POLARIS12: 246 fw_name = FIRMWARE_POLARIS12; 247 break; 248 case CHIP_VEGA10: 249 fw_name = FIRMWARE_VEGA10; 250 break; 251 case CHIP_VEGA12: 252 fw_name = FIRMWARE_VEGA12; 253 break; 254 case CHIP_VEGAM: 255 fw_name = FIRMWARE_VEGAM; 256 break; 257 case CHIP_VEGA20: 258 fw_name = FIRMWARE_VEGA20; 259 break; 260 default: 261 return -EINVAL; 262 } 263 264 r = amdgpu_ucode_request(adev, &adev->uvd.fw, AMDGPU_UCODE_REQUIRED, "%s", fw_name); 265 if (r) { 266 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 267 fw_name); 268 amdgpu_ucode_release(&adev->uvd.fw); 269 return r; 270 } 271 272 /* Set the default UVD handles that the firmware can handle */ 273 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 274 275 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 276 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 277 278 if (adev->asic_type < CHIP_VEGA20) { 279 unsigned int version_major, version_minor; 280 281 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 282 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 283 drm_info(adev_to_drm(adev), "Found UVD firmware Version: %u.%u Family ID: %u\n", 284 version_major, version_minor, family_id); 285 286 /* 287 * Limit the number of UVD handles depending on microcode major 288 * and minor versions. The firmware version which has 40 UVD 289 * instances support is 1.80. So all subsequent versions should 290 * also have the same support. 291 */ 292 if ((version_major > 0x01) || 293 ((version_major == 0x01) && (version_minor >= 0x50))) 294 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 295 296 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 297 (family_id << 8)); 298 299 if ((adev->asic_type == CHIP_POLARIS10 || 300 adev->asic_type == CHIP_POLARIS11) && 301 (adev->uvd.fw_version < FW_1_66_16)) 302 DRM_ERROR("POLARIS10/11 UVD firmware version %u.%u is too old.\n", 303 version_major, version_minor); 304 } else { 305 unsigned int enc_major, enc_minor, dec_minor; 306 307 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 308 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f; 309 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3; 310 drm_info(adev_to_drm(adev), "Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n", 311 enc_major, enc_minor, dec_minor, family_id); 312 313 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 314 315 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version); 316 } 317 318 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 319 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 320 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 321 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 322 323 /* UVD 5.0 and newer HW can use 64 bit addressing. */ 324 adev->uvd.address_64_bit = 325 !amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0); 326 327 vcpu_bo_domain = AMDGPU_GEM_DOMAIN_VRAM; 328 if (adev->uvd.address_64_bit) 329 vcpu_bo_domain |= AMDGPU_GEM_DOMAIN_GTT; 330 331 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 332 if (adev->uvd.harvest_config & (1 << j)) 333 continue; 334 335 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 336 vcpu_bo_domain, 337 &adev->uvd.inst[j].vcpu_bo, 338 &adev->uvd.inst[j].gpu_addr, 339 &adev->uvd.inst[j].cpu_addr); 340 if (r) { 341 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 342 return r; 343 } 344 } 345 346 for (i = 0; i < adev->uvd.max_handles; ++i) { 347 atomic_set(&adev->uvd.handles[i], 0); 348 adev->uvd.filp[i] = NULL; 349 } 350 351 r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo); 352 if (r) 353 return r; 354 355 switch (adev->asic_type) { 356 case CHIP_TONGA: 357 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; 358 break; 359 case CHIP_CARRIZO: 360 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; 361 break; 362 case CHIP_FIJI: 363 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; 364 break; 365 case CHIP_STONEY: 366 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; 367 break; 368 default: 369 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; 370 } 371 372 return 0; 373 } 374 375 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 376 { 377 void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo); 378 int i, j; 379 380 drm_sched_entity_destroy(&adev->uvd.entity); 381 382 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 383 if (adev->uvd.harvest_config & (1 << j)) 384 continue; 385 kvfree(adev->uvd.inst[j].saved_bo); 386 387 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo, 388 &adev->uvd.inst[j].gpu_addr, 389 (void **)&adev->uvd.inst[j].cpu_addr); 390 391 amdgpu_ring_fini(&adev->uvd.inst[j].ring); 392 393 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) 394 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 395 } 396 amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr); 397 amdgpu_ucode_release(&adev->uvd.fw); 398 399 return 0; 400 } 401 402 /** 403 * amdgpu_uvd_entity_init - init entity 404 * 405 * @adev: amdgpu_device pointer 406 * @ring: amdgpu_ring pointer to check 407 * 408 * Initialize the entity used for handle management in the kernel driver. 409 */ 410 int amdgpu_uvd_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring) 411 { 412 if (ring == &adev->uvd.inst[0].ring) { 413 struct drm_gpu_scheduler *sched = &ring->sched; 414 int r; 415 416 r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL, 417 &sched, 1, NULL); 418 if (r) { 419 DRM_ERROR("Failed setting up UVD kernel entity.\n"); 420 return r; 421 } 422 } 423 424 return 0; 425 } 426 427 int amdgpu_uvd_prepare_suspend(struct amdgpu_device *adev) 428 { 429 unsigned int size; 430 void *ptr; 431 int i, j, idx; 432 433 cancel_delayed_work_sync(&adev->uvd.idle_work); 434 435 /* only valid for physical mode */ 436 if (adev->asic_type < CHIP_POLARIS10) { 437 for (i = 0; i < adev->uvd.max_handles; ++i) 438 if (atomic_read(&adev->uvd.handles[i])) 439 break; 440 441 if (i == adev->uvd.max_handles) 442 return 0; 443 } 444 445 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 446 if (adev->uvd.harvest_config & (1 << j)) 447 continue; 448 if (adev->uvd.inst[j].vcpu_bo == NULL) 449 continue; 450 451 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo); 452 ptr = adev->uvd.inst[j].cpu_addr; 453 454 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL); 455 if (!adev->uvd.inst[j].saved_bo) 456 return -ENOMEM; 457 458 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 459 /* re-write 0 since err_event_athub will corrupt VCPU buffer */ 460 if (amdgpu_ras_intr_triggered()) 461 memset(adev->uvd.inst[j].saved_bo, 0, size); 462 else 463 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); 464 465 drm_dev_exit(idx); 466 } 467 } 468 469 return 0; 470 } 471 472 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 473 { 474 if (amdgpu_ras_intr_triggered()) 475 drm_warn(adev_to_drm(adev), 476 "UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n"); 477 478 return 0; 479 } 480 481 int amdgpu_uvd_resume(struct amdgpu_device *adev) 482 { 483 unsigned int size; 484 void *ptr; 485 int i, idx; 486 487 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 488 if (adev->uvd.harvest_config & (1 << i)) 489 continue; 490 if (adev->uvd.inst[i].vcpu_bo == NULL) 491 return -EINVAL; 492 493 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo); 494 ptr = adev->uvd.inst[i].cpu_addr; 495 496 if (adev->uvd.inst[i].saved_bo != NULL) { 497 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 498 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size); 499 drm_dev_exit(idx); 500 } 501 kvfree(adev->uvd.inst[i].saved_bo); 502 adev->uvd.inst[i].saved_bo = NULL; 503 } else { 504 const struct common_firmware_header *hdr; 505 unsigned int offset; 506 507 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 508 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 509 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 510 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 511 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, 512 le32_to_cpu(hdr->ucode_size_bytes)); 513 drm_dev_exit(idx); 514 } 515 size -= le32_to_cpu(hdr->ucode_size_bytes); 516 ptr += le32_to_cpu(hdr->ucode_size_bytes); 517 } 518 memset_io(ptr, 0, size); 519 /* to restore uvd fence seq */ 520 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring, NULL); 521 } 522 } 523 return 0; 524 } 525 526 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 527 { 528 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring; 529 int i, r; 530 531 for (i = 0; i < adev->uvd.max_handles; ++i) { 532 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 533 534 if (handle != 0 && adev->uvd.filp[i] == filp) { 535 struct dma_fence *fence; 536 537 r = amdgpu_uvd_get_destroy_msg(ring, handle, false, 538 &fence); 539 if (r) { 540 DRM_ERROR("Error destroying UVD %d!\n", r); 541 continue; 542 } 543 544 dma_fence_wait(fence, false); 545 dma_fence_put(fence); 546 547 adev->uvd.filp[i] = NULL; 548 atomic_set(&adev->uvd.handles[i], 0); 549 } 550 } 551 } 552 553 static void amdgpu_uvd_force_into_vcpu_segment(struct amdgpu_bo *bo) 554 { 555 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 556 struct amdgpu_bo *vcpu_bo = adev->uvd.inst[0].vcpu_bo; 557 struct amdgpu_res_cursor vcpu_cur; 558 559 amdgpu_res_first(vcpu_bo->tbo.resource, 0, 560 amdgpu_bo_size(vcpu_bo), &vcpu_cur); 561 562 bo->placement.num_placement = 1; 563 bo->placement.placement = &bo->placements[0]; 564 bo->placements[0].fpfn = ALIGN_DOWN(vcpu_cur.start, SZ_256M) >> PAGE_SHIFT; 565 bo->placements[0].lpfn = bo->placements[0].fpfn + (SZ_256M >> PAGE_SHIFT); 566 bo->placements[0].mem_type = vcpu_bo->tbo.resource->mem_type; 567 if (bo->placements[0].mem_type == TTM_PL_VRAM) 568 bo->placements[0].flags |= TTM_PL_FLAG_CONTIGUOUS; 569 } 570 571 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 572 { 573 int i; 574 575 for (i = 0; i < abo->placement.num_placement; ++i) { 576 abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 577 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 578 if (abo->placements[i].mem_type == TTM_PL_VRAM) 579 abo->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS; 580 } 581 } 582 583 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) 584 { 585 uint32_t lo, hi; 586 uint64_t addr; 587 588 lo = amdgpu_ib_get_value(ctx->ib, ctx->data0); 589 hi = amdgpu_ib_get_value(ctx->ib, ctx->data1); 590 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 591 592 return addr; 593 } 594 595 /** 596 * amdgpu_uvd_cs_pass1 - first parsing round 597 * 598 * @ctx: UVD parser context 599 * 600 * Make sure UVD message and feedback buffers are in VRAM and 601 * nobody is violating an 256MB boundary. 602 */ 603 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 604 { 605 struct ttm_operation_ctx tctx = { false, false }; 606 struct amdgpu_bo_va_mapping *mapping; 607 struct amdgpu_bo *bo; 608 uint32_t cmd; 609 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 610 int r = 0; 611 612 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 613 if (r) { 614 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 615 return r; 616 } 617 618 if (!ctx->parser->adev->uvd.address_64_bit) { 619 /* check if it's a message or feedback command */ 620 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1; 621 if (cmd == 0x0 || cmd == 0x3) 622 amdgpu_uvd_force_into_vcpu_segment(bo); 623 else 624 amdgpu_uvd_force_into_uvd_segment(bo); 625 626 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); 627 } 628 629 return r; 630 } 631 632 /** 633 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 634 * 635 * @adev: amdgpu_device pointer 636 * @msg: pointer to message structure 637 * @buf_sizes: placeholder to put the different buffer lengths 638 * 639 * Peek into the decode message and calculate the necessary buffer sizes. 640 */ 641 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 642 unsigned int buf_sizes[]) 643 { 644 unsigned int stream_type = msg[4]; 645 unsigned int width = msg[6]; 646 unsigned int height = msg[7]; 647 unsigned int dpb_size = msg[9]; 648 unsigned int pitch = msg[28]; 649 650 unsigned int width_in_mb = width / 16; 651 unsigned int height_in_mb = ALIGN(height / 16, 2); 652 653 unsigned int image_size, tmp, min_dpb_size, num_dpb_buffer; 654 unsigned int min_ctx_size = ~0; 655 656 /* Reject invalid dimensions */ 657 if (width < 16 || height < 16 || width > 4096 || height > 4096) { 658 dev_WARN_ONCE(adev->dev, 1, 659 "Invalid UVD decoding dimensions (%dx%d)!\n", 660 width, height); 661 return -EINVAL; 662 } 663 664 image_size = width * height; 665 image_size += image_size / 2; 666 image_size = ALIGN(image_size, 1024); 667 668 switch (stream_type) { 669 case 0: /* H264 */ 670 num_dpb_buffer = ((msg[61] >> 16) & 0xff) + 1; 671 if (num_dpb_buffer > 17) 672 return -EINVAL; 673 674 /* reference picture buffer */ 675 min_dpb_size = image_size * num_dpb_buffer; 676 677 /* macroblock context buffer */ 678 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 679 680 /* IT surface buffer */ 681 min_dpb_size += width_in_mb * height_in_mb * 32; 682 break; 683 684 case 1: /* VC1 */ 685 686 /* reference picture buffer */ 687 min_dpb_size = image_size * 3; 688 689 /* CONTEXT_BUFFER */ 690 min_dpb_size += width_in_mb * height_in_mb * 128; 691 692 /* IT surface buffer */ 693 min_dpb_size += width_in_mb * 64; 694 695 /* DB surface buffer */ 696 min_dpb_size += width_in_mb * 128; 697 698 /* BP */ 699 tmp = max(width_in_mb, height_in_mb); 700 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 701 break; 702 703 case 3: /* MPEG2 */ 704 705 /* reference picture buffer */ 706 min_dpb_size = image_size * 3; 707 break; 708 709 case 4: /* MPEG4 */ 710 711 /* reference picture buffer */ 712 min_dpb_size = image_size * 3; 713 714 /* CM */ 715 min_dpb_size += width_in_mb * height_in_mb * 64; 716 717 /* IT surface buffer */ 718 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 719 break; 720 721 case 7: /* H264 Perf */ 722 num_dpb_buffer = ((msg[61] >> 16) & 0xff) + 1; 723 if (num_dpb_buffer > 17) 724 return -EINVAL; 725 726 /* reference picture buffer */ 727 min_dpb_size = image_size * num_dpb_buffer; 728 729 if (!adev->uvd.use_ctx_buf) { 730 /* macroblock context buffer */ 731 min_dpb_size += 732 width_in_mb * height_in_mb * num_dpb_buffer * 192; 733 734 /* IT surface buffer */ 735 min_dpb_size += width_in_mb * height_in_mb * 32; 736 } else { 737 /* macroblock context buffer */ 738 min_ctx_size = 739 width_in_mb * height_in_mb * num_dpb_buffer * 192; 740 } 741 break; 742 743 case 8: /* MJPEG */ 744 min_dpb_size = 0; 745 break; 746 747 case 16: /* H265 */ 748 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 749 image_size = ALIGN(image_size, 256); 750 751 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 752 if (num_dpb_buffer > 17) 753 return -EINVAL; 754 755 min_dpb_size = image_size * num_dpb_buffer; 756 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 757 * 16 * num_dpb_buffer + 52 * 1024; 758 break; 759 760 default: 761 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 762 return -EINVAL; 763 } 764 765 if (width > pitch || pitch > 4096) { 766 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 767 return -EINVAL; 768 } 769 770 if (dpb_size < min_dpb_size) { 771 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 772 dpb_size, min_dpb_size); 773 return -EINVAL; 774 } 775 776 buf_sizes[0x1] = dpb_size; 777 buf_sizes[0x2] = (pitch * height) * 3 / 2; 778 buf_sizes[0x4] = min_ctx_size; 779 /* store image width to adjust nb memory pstate */ 780 adev->uvd.decode_image_width = width; 781 return 0; 782 } 783 784 /** 785 * amdgpu_uvd_cs_msg - handle UVD message 786 * 787 * @ctx: UVD parser context 788 * @bo: buffer object containing the message 789 * @offset: offset into the buffer object 790 * 791 * Peek into the UVD message and extract the session id. 792 * Make sure that we don't open up to many sessions. 793 */ 794 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 795 struct amdgpu_bo *bo, unsigned int offset) 796 { 797 struct amdgpu_device *adev = ctx->parser->adev; 798 int32_t *msg, msg_type, handle; 799 void *ptr; 800 long r; 801 int i; 802 803 if (offset & 0x3F) { 804 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 805 return -EINVAL; 806 } 807 808 r = amdgpu_bo_kmap(bo, &ptr); 809 if (r) { 810 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r); 811 return r; 812 } 813 814 msg = ptr + offset; 815 816 msg_type = msg[1]; 817 handle = msg[2]; 818 819 if (handle == 0) { 820 amdgpu_bo_kunmap(bo); 821 DRM_ERROR("Invalid UVD handle!\n"); 822 return -EINVAL; 823 } 824 825 switch (msg_type) { 826 case 0: 827 /* it's a create msg, calc image size (width * height) */ 828 amdgpu_bo_kunmap(bo); 829 830 /* try to alloc a new handle */ 831 for (i = 0; i < adev->uvd.max_handles; ++i) { 832 if (atomic_read(&adev->uvd.handles[i]) == handle) { 833 DRM_ERROR(")Handle 0x%x already in use!\n", 834 handle); 835 return -EINVAL; 836 } 837 838 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 839 adev->uvd.filp[i] = ctx->parser->filp; 840 return 0; 841 } 842 } 843 844 DRM_ERROR("No more free UVD handles!\n"); 845 return -ENOSPC; 846 847 case 1: 848 /* it's a decode msg, calc buffer sizes */ 849 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 850 amdgpu_bo_kunmap(bo); 851 if (r) 852 return r; 853 854 /* validate the handle */ 855 for (i = 0; i < adev->uvd.max_handles; ++i) { 856 if (atomic_read(&adev->uvd.handles[i]) == handle) { 857 if (adev->uvd.filp[i] != ctx->parser->filp) { 858 DRM_ERROR("UVD handle collision detected!\n"); 859 return -EINVAL; 860 } 861 return 0; 862 } 863 } 864 865 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 866 return -ENOENT; 867 868 case 2: 869 /* it's a destroy msg, free the handle */ 870 for (i = 0; i < adev->uvd.max_handles; ++i) 871 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 872 amdgpu_bo_kunmap(bo); 873 return 0; 874 875 default: 876 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 877 } 878 879 amdgpu_bo_kunmap(bo); 880 return -EINVAL; 881 } 882 883 /** 884 * amdgpu_uvd_cs_pass2 - second parsing round 885 * 886 * @ctx: UVD parser context 887 * 888 * Patch buffer addresses, make sure buffer sizes are correct. 889 */ 890 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 891 { 892 struct amdgpu_bo_va_mapping *mapping; 893 struct amdgpu_bo *bo; 894 uint32_t cmd; 895 uint64_t start, end; 896 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 897 int r; 898 899 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 900 if (r) { 901 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 902 return r; 903 } 904 905 start = amdgpu_bo_gpu_offset(bo); 906 907 end = (mapping->last + 1 - mapping->start); 908 end = end * AMDGPU_GPU_PAGE_SIZE + start; 909 910 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; 911 start += addr; 912 913 amdgpu_ib_set_value(ctx->ib, ctx->data0, lower_32_bits(start)); 914 amdgpu_ib_set_value(ctx->ib, ctx->data1, upper_32_bits(start)); 915 916 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1; 917 if (cmd < 0x4) { 918 if ((end - start) < ctx->buf_sizes[cmd]) { 919 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 920 (unsigned int)(end - start), 921 ctx->buf_sizes[cmd]); 922 return -EINVAL; 923 } 924 } else if (cmd == 0x204 || cmd == 0x206) { 925 unsigned int min_size = ctx->buf_sizes[cmd == 0x204 ? 5 : 4]; 926 927 if ((end - start) < min_size) { 928 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 929 (unsigned int)(end - start), 930 min_size); 931 return -EINVAL; 932 } 933 } else if ((cmd != 0x100)) { 934 DRM_ERROR("invalid UVD command %X!\n", cmd); 935 return -EINVAL; 936 } 937 938 if (!ctx->parser->adev->uvd.address_64_bit) { 939 if ((start >> 28) != ((end - 1) >> 28)) { 940 DRM_ERROR("reloc %llx-%llx crossing 256MB boundary!\n", 941 start, end); 942 return -EINVAL; 943 } 944 945 if ((cmd == 0 || cmd == 0x3) && 946 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) { 947 DRM_ERROR("msg/fb buffer %llx-%llx out of 256MB segment!\n", 948 start, end); 949 return -EINVAL; 950 } 951 } 952 953 if (cmd == 0) { 954 ctx->has_msg_cmd = true; 955 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 956 if (r) 957 return r; 958 } else if (!ctx->has_msg_cmd) { 959 DRM_ERROR("Message needed before other commands are send!\n"); 960 return -EINVAL; 961 } 962 963 return 0; 964 } 965 966 /** 967 * amdgpu_uvd_cs_reg - parse register writes 968 * 969 * @ctx: UVD parser context 970 * @cb: callback function 971 * 972 * Parse the register writes, call cb on each complete command. 973 */ 974 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 975 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 976 { 977 int i, r; 978 979 ctx->idx++; 980 for (i = 0; i <= ctx->count; ++i) { 981 unsigned int reg = ctx->reg + i; 982 983 if (ctx->idx >= ctx->ib->length_dw) { 984 DRM_ERROR("Register command after end of CS!\n"); 985 return -EINVAL; 986 } 987 988 switch (reg) { 989 case mmUVD_GPCOM_VCPU_DATA0: 990 ctx->data0 = ctx->idx; 991 break; 992 case mmUVD_GPCOM_VCPU_DATA1: 993 ctx->data1 = ctx->idx; 994 break; 995 case mmUVD_GPCOM_VCPU_CMD: 996 r = cb(ctx); 997 if (r) 998 return r; 999 break; 1000 case mmUVD_ENGINE_CNTL: 1001 case mmUVD_NO_OP: 1002 break; 1003 default: 1004 DRM_ERROR("Invalid reg 0x%X!\n", reg); 1005 return -EINVAL; 1006 } 1007 ctx->idx++; 1008 } 1009 return 0; 1010 } 1011 1012 /** 1013 * amdgpu_uvd_cs_packets - parse UVD packets 1014 * 1015 * @ctx: UVD parser context 1016 * @cb: callback function 1017 * 1018 * Parse the command stream packets. 1019 */ 1020 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 1021 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 1022 { 1023 int r; 1024 1025 for (ctx->idx = 0 ; ctx->idx < ctx->ib->length_dw; ) { 1026 uint32_t cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx); 1027 unsigned int type = CP_PACKET_GET_TYPE(cmd); 1028 1029 switch (type) { 1030 case PACKET_TYPE0: 1031 ctx->reg = CP_PACKET0_GET_REG(cmd); 1032 ctx->count = CP_PACKET_GET_COUNT(cmd); 1033 r = amdgpu_uvd_cs_reg(ctx, cb); 1034 if (r) 1035 return r; 1036 break; 1037 case PACKET_TYPE2: 1038 ++ctx->idx; 1039 break; 1040 default: 1041 DRM_ERROR("Unknown packet type %d !\n", type); 1042 return -EINVAL; 1043 } 1044 } 1045 return 0; 1046 } 1047 1048 /** 1049 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 1050 * 1051 * @parser: Command submission parser context 1052 * @job: the job to parse 1053 * @ib: the IB to patch 1054 * 1055 * Parse the command stream, patch in addresses as necessary. 1056 */ 1057 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, 1058 struct amdgpu_job *job, 1059 struct amdgpu_ib *ib) 1060 { 1061 struct amdgpu_uvd_cs_ctx ctx = {}; 1062 unsigned int buf_sizes[] = { 1063 [0x00000000] = 3556, 1064 [0x00000001] = 0xFFFFFFFF, 1065 [0x00000002] = 0xFFFFFFFF, 1066 [0x00000003] = 2048, 1067 [0x00000004] = 0xFFFFFFFF, 1068 [0x00000005] = 992, 1069 }; 1070 int r; 1071 1072 job->vm = NULL; 1073 1074 if (ib->length_dw % 16) { 1075 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 1076 ib->length_dw); 1077 return -EINVAL; 1078 } 1079 1080 ctx.parser = parser; 1081 ctx.buf_sizes = buf_sizes; 1082 ctx.ib = ib; 1083 1084 /* first round only required on chips without UVD 64 bit address support */ 1085 if (!parser->adev->uvd.address_64_bit) { 1086 /* first round, make sure the buffers are actually in the UVD segment */ 1087 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 1088 if (r) 1089 return r; 1090 } 1091 1092 /* second round, patch buffer addresses into the command stream */ 1093 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 1094 if (r) 1095 return r; 1096 1097 if (!ctx.has_msg_cmd) { 1098 DRM_ERROR("UVD-IBs need a msg command!\n"); 1099 return -EINVAL; 1100 } 1101 1102 return 0; 1103 } 1104 1105 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 1106 bool direct, struct dma_fence **fence) 1107 { 1108 struct amdgpu_device *adev = ring->adev; 1109 struct dma_fence *f = NULL; 1110 uint32_t offset, data[4]; 1111 struct amdgpu_job *job; 1112 struct amdgpu_ib *ib; 1113 uint64_t addr; 1114 int i, r; 1115 1116 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->uvd.entity, 1117 AMDGPU_FENCE_OWNER_UNDEFINED, 1118 64, direct ? AMDGPU_IB_POOL_DIRECT : 1119 AMDGPU_IB_POOL_DELAYED, &job, 1120 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); 1121 if (r) 1122 return r; 1123 1124 if (adev->asic_type >= CHIP_VEGA10) 1125 offset = adev->reg_offset[UVD_HWIP][ring->me][1]; 1126 else 1127 offset = UVD_BASE_SI; 1128 1129 data[0] = PACKET0(offset + UVD_GPCOM_VCPU_DATA0, 0); 1130 data[1] = PACKET0(offset + UVD_GPCOM_VCPU_DATA1, 0); 1131 data[2] = PACKET0(offset + UVD_GPCOM_VCPU_CMD, 0); 1132 data[3] = PACKET0(offset + UVD_NO_OP, 0); 1133 1134 ib = &job->ibs[0]; 1135 addr = amdgpu_bo_gpu_offset(bo); 1136 ib->ptr[0] = data[0]; 1137 ib->ptr[1] = addr; 1138 ib->ptr[2] = data[1]; 1139 ib->ptr[3] = addr >> 32; 1140 ib->ptr[4] = data[2]; 1141 ib->ptr[5] = 0; 1142 for (i = 6; i < 16; i += 2) { 1143 ib->ptr[i] = data[3]; 1144 ib->ptr[i+1] = 0; 1145 } 1146 ib->length_dw = 16; 1147 1148 if (direct) { 1149 r = amdgpu_job_submit_direct(job, ring, &f); 1150 if (r) 1151 goto err_free; 1152 } else { 1153 r = drm_sched_job_add_resv_dependencies(&job->base, 1154 bo->tbo.base.resv, 1155 DMA_RESV_USAGE_KERNEL); 1156 if (r) 1157 goto err_free; 1158 1159 f = amdgpu_job_submit(job); 1160 } 1161 1162 amdgpu_bo_reserve(bo, true); 1163 amdgpu_bo_fence(bo, f, false); 1164 amdgpu_bo_unreserve(bo); 1165 1166 if (fence) 1167 *fence = dma_fence_get(f); 1168 dma_fence_put(f); 1169 1170 return 0; 1171 1172 err_free: 1173 amdgpu_job_free(job); 1174 return r; 1175 } 1176 1177 /* multiple fence commands without any stream commands in between can 1178 * crash the vcpu so just try to emmit a dummy create/destroy msg to 1179 * avoid this 1180 */ 1181 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1182 struct dma_fence **fence) 1183 { 1184 struct amdgpu_device *adev = ring->adev; 1185 struct amdgpu_bo *bo = adev->uvd.ib_bo; 1186 uint32_t *msg; 1187 int i; 1188 1189 msg = amdgpu_bo_kptr(bo); 1190 /* stitch together an UVD create msg */ 1191 msg[0] = cpu_to_le32(0x00000de4); 1192 msg[1] = cpu_to_le32(0x00000000); 1193 msg[2] = cpu_to_le32(handle); 1194 msg[3] = cpu_to_le32(0x00000000); 1195 msg[4] = cpu_to_le32(0x00000000); 1196 msg[5] = cpu_to_le32(0x00000000); 1197 msg[6] = cpu_to_le32(0x00000000); 1198 msg[7] = cpu_to_le32(0x00000780); 1199 msg[8] = cpu_to_le32(0x00000440); 1200 msg[9] = cpu_to_le32(0x00000000); 1201 msg[10] = cpu_to_le32(0x01b37000); 1202 for (i = 11; i < 1024; ++i) 1203 msg[i] = cpu_to_le32(0x0); 1204 1205 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1206 1207 } 1208 1209 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1210 bool direct, struct dma_fence **fence) 1211 { 1212 struct amdgpu_device *adev = ring->adev; 1213 struct amdgpu_bo *bo = NULL; 1214 uint32_t *msg; 1215 int r, i; 1216 1217 if (direct) { 1218 bo = adev->uvd.ib_bo; 1219 } else { 1220 r = amdgpu_uvd_create_msg_bo_helper(adev, 4096, &bo); 1221 if (r) 1222 return r; 1223 } 1224 1225 msg = amdgpu_bo_kptr(bo); 1226 /* stitch together an UVD destroy msg */ 1227 msg[0] = cpu_to_le32(0x00000de4); 1228 msg[1] = cpu_to_le32(0x00000002); 1229 msg[2] = cpu_to_le32(handle); 1230 msg[3] = cpu_to_le32(0x00000000); 1231 for (i = 4; i < 1024; ++i) 1232 msg[i] = cpu_to_le32(0x0); 1233 1234 r = amdgpu_uvd_send_msg(ring, bo, direct, fence); 1235 1236 if (!direct) 1237 amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg); 1238 1239 return r; 1240 } 1241 1242 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1243 { 1244 struct amdgpu_device *adev = 1245 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1246 unsigned int fences = 0, i, j; 1247 1248 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1249 if (adev->uvd.harvest_config & (1 << i)) 1250 continue; 1251 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring); 1252 for (j = 0; j < adev->uvd.num_enc_rings; ++j) 1253 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]); 1254 } 1255 1256 if (fences == 0) { 1257 if (adev->pm.dpm_enabled) { 1258 amdgpu_dpm_enable_uvd(adev, false); 1259 } else { 1260 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1261 /* shutdown the UVD block */ 1262 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1263 AMD_PG_STATE_GATE); 1264 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1265 AMD_CG_STATE_GATE); 1266 } 1267 } else { 1268 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1269 } 1270 } 1271 1272 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 1273 { 1274 struct amdgpu_device *adev = ring->adev; 1275 bool set_clocks; 1276 1277 if (amdgpu_sriov_vf(adev)) 1278 return; 1279 1280 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1281 if (set_clocks) { 1282 if (adev->pm.dpm_enabled) { 1283 amdgpu_dpm_enable_uvd(adev, true); 1284 } else { 1285 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1286 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1287 AMD_CG_STATE_UNGATE); 1288 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1289 AMD_PG_STATE_UNGATE); 1290 } 1291 } 1292 } 1293 1294 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) 1295 { 1296 if (!amdgpu_sriov_vf(ring->adev)) 1297 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1298 } 1299 1300 /** 1301 * amdgpu_uvd_ring_test_ib - test ib execution 1302 * 1303 * @ring: amdgpu_ring pointer 1304 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1305 * 1306 * Test if we can successfully execute an IB 1307 */ 1308 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1309 { 1310 struct dma_fence *fence; 1311 long r; 1312 1313 r = amdgpu_uvd_get_create_msg(ring, 1, &fence); 1314 if (r) 1315 goto error; 1316 1317 r = dma_fence_wait_timeout(fence, false, timeout); 1318 dma_fence_put(fence); 1319 if (r == 0) 1320 r = -ETIMEDOUT; 1321 if (r < 0) 1322 goto error; 1323 1324 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 1325 if (r) 1326 goto error; 1327 1328 r = dma_fence_wait_timeout(fence, false, timeout); 1329 if (r == 0) 1330 r = -ETIMEDOUT; 1331 else if (r > 0) 1332 r = 0; 1333 1334 dma_fence_put(fence); 1335 1336 error: 1337 return r; 1338 } 1339 1340 /** 1341 * amdgpu_uvd_used_handles - returns used UVD handles 1342 * 1343 * @adev: amdgpu_device pointer 1344 * 1345 * Returns the number of UVD handles in use 1346 */ 1347 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) 1348 { 1349 unsigned int i; 1350 uint32_t used_handles = 0; 1351 1352 for (i = 0; i < adev->uvd.max_handles; ++i) { 1353 /* 1354 * Handles can be freed in any order, and not 1355 * necessarily linear. So we need to count 1356 * all non-zero handles. 1357 */ 1358 if (atomic_read(&adev->uvd.handles[i])) 1359 used_handles++; 1360 } 1361 1362 return used_handles; 1363 } 1364