1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 34 #include <drm/drm.h> 35 #include <drm/drm_drv.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_pm.h" 39 #include "amdgpu_uvd.h" 40 #include "amdgpu_cs.h" 41 #include "cikd.h" 42 #include "uvd/uvd_4_2_d.h" 43 44 #include "amdgpu_ras.h" 45 46 /* 1 second timeout */ 47 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) 48 49 /* Firmware versions for VI */ 50 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) 51 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) 52 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) 53 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) 54 55 /* Polaris10/11 firmware version */ 56 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 57 58 /* Firmware Names */ 59 #ifdef CONFIG_DRM_AMDGPU_SI 60 #define FIRMWARE_TAHITI "amdgpu/tahiti_uvd.bin" 61 #define FIRMWARE_VERDE "amdgpu/verde_uvd.bin" 62 #define FIRMWARE_PITCAIRN "amdgpu/pitcairn_uvd.bin" 63 #define FIRMWARE_OLAND "amdgpu/oland_uvd.bin" 64 #endif 65 #ifdef CONFIG_DRM_AMDGPU_CIK 66 #define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin" 67 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin" 68 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin" 69 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin" 70 #define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin" 71 #endif 72 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 73 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 74 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 75 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 76 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 77 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 78 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" 79 #define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin" 80 81 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" 82 #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin" 83 #define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin" 84 85 /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */ 86 #define UVD_GPCOM_VCPU_CMD 0x03c3 87 #define UVD_GPCOM_VCPU_DATA0 0x03c4 88 #define UVD_GPCOM_VCPU_DATA1 0x03c5 89 #define UVD_NO_OP 0x03ff 90 #define UVD_BASE_SI 0x3800 91 92 /* 93 * amdgpu_uvd_cs_ctx - Command submission parser context 94 * 95 * Used for emulating virtual memory support on UVD 4.2. 96 */ 97 struct amdgpu_uvd_cs_ctx { 98 struct amdgpu_cs_parser *parser; 99 unsigned int reg, count; 100 unsigned int data0, data1; 101 unsigned int idx; 102 struct amdgpu_ib *ib; 103 104 /* does the IB has a msg command */ 105 bool has_msg_cmd; 106 107 /* minimum buffer sizes */ 108 unsigned int *buf_sizes; 109 }; 110 111 #ifdef CONFIG_DRM_AMDGPU_SI 112 MODULE_FIRMWARE(FIRMWARE_TAHITI); 113 MODULE_FIRMWARE(FIRMWARE_VERDE); 114 MODULE_FIRMWARE(FIRMWARE_PITCAIRN); 115 MODULE_FIRMWARE(FIRMWARE_OLAND); 116 #endif 117 #ifdef CONFIG_DRM_AMDGPU_CIK 118 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 119 MODULE_FIRMWARE(FIRMWARE_KABINI); 120 MODULE_FIRMWARE(FIRMWARE_KAVERI); 121 MODULE_FIRMWARE(FIRMWARE_HAWAII); 122 MODULE_FIRMWARE(FIRMWARE_MULLINS); 123 #endif 124 MODULE_FIRMWARE(FIRMWARE_TONGA); 125 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 126 MODULE_FIRMWARE(FIRMWARE_FIJI); 127 MODULE_FIRMWARE(FIRMWARE_STONEY); 128 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 129 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 130 MODULE_FIRMWARE(FIRMWARE_POLARIS12); 131 MODULE_FIRMWARE(FIRMWARE_VEGAM); 132 133 MODULE_FIRMWARE(FIRMWARE_VEGA10); 134 MODULE_FIRMWARE(FIRMWARE_VEGA12); 135 MODULE_FIRMWARE(FIRMWARE_VEGA20); 136 137 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 138 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo); 139 140 static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev, 141 uint32_t size, 142 struct amdgpu_bo **bo_ptr) 143 { 144 struct ttm_operation_ctx ctx = { true, false }; 145 struct amdgpu_bo *bo = NULL; 146 void *addr; 147 int r; 148 149 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, 150 AMDGPU_GEM_DOMAIN_GTT, 151 &bo, NULL, &addr); 152 if (r) 153 return r; 154 155 if (adev->uvd.address_64_bit) 156 goto succ; 157 158 amdgpu_bo_kunmap(bo); 159 amdgpu_bo_unpin(bo); 160 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 161 amdgpu_uvd_force_into_uvd_segment(bo); 162 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 163 if (r) 164 goto err; 165 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM); 166 if (r) 167 goto err_pin; 168 r = amdgpu_bo_kmap(bo, &addr); 169 if (r) 170 goto err_kmap; 171 succ: 172 amdgpu_bo_unreserve(bo); 173 *bo_ptr = bo; 174 return 0; 175 err_kmap: 176 amdgpu_bo_unpin(bo); 177 err_pin: 178 err: 179 amdgpu_bo_unreserve(bo); 180 amdgpu_bo_unref(&bo); 181 return r; 182 } 183 184 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 185 { 186 unsigned long bo_size; 187 const char *fw_name; 188 const struct common_firmware_header *hdr; 189 unsigned int family_id; 190 int i, j, r; 191 192 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 193 194 switch (adev->asic_type) { 195 #ifdef CONFIG_DRM_AMDGPU_SI 196 case CHIP_TAHITI: 197 fw_name = FIRMWARE_TAHITI; 198 break; 199 case CHIP_VERDE: 200 fw_name = FIRMWARE_VERDE; 201 break; 202 case CHIP_PITCAIRN: 203 fw_name = FIRMWARE_PITCAIRN; 204 break; 205 case CHIP_OLAND: 206 fw_name = FIRMWARE_OLAND; 207 break; 208 #endif 209 #ifdef CONFIG_DRM_AMDGPU_CIK 210 case CHIP_BONAIRE: 211 fw_name = FIRMWARE_BONAIRE; 212 break; 213 case CHIP_KABINI: 214 fw_name = FIRMWARE_KABINI; 215 break; 216 case CHIP_KAVERI: 217 fw_name = FIRMWARE_KAVERI; 218 break; 219 case CHIP_HAWAII: 220 fw_name = FIRMWARE_HAWAII; 221 break; 222 case CHIP_MULLINS: 223 fw_name = FIRMWARE_MULLINS; 224 break; 225 #endif 226 case CHIP_TONGA: 227 fw_name = FIRMWARE_TONGA; 228 break; 229 case CHIP_FIJI: 230 fw_name = FIRMWARE_FIJI; 231 break; 232 case CHIP_CARRIZO: 233 fw_name = FIRMWARE_CARRIZO; 234 break; 235 case CHIP_STONEY: 236 fw_name = FIRMWARE_STONEY; 237 break; 238 case CHIP_POLARIS10: 239 fw_name = FIRMWARE_POLARIS10; 240 break; 241 case CHIP_POLARIS11: 242 fw_name = FIRMWARE_POLARIS11; 243 break; 244 case CHIP_POLARIS12: 245 fw_name = FIRMWARE_POLARIS12; 246 break; 247 case CHIP_VEGA10: 248 fw_name = FIRMWARE_VEGA10; 249 break; 250 case CHIP_VEGA12: 251 fw_name = FIRMWARE_VEGA12; 252 break; 253 case CHIP_VEGAM: 254 fw_name = FIRMWARE_VEGAM; 255 break; 256 case CHIP_VEGA20: 257 fw_name = FIRMWARE_VEGA20; 258 break; 259 default: 260 return -EINVAL; 261 } 262 263 r = amdgpu_ucode_request(adev, &adev->uvd.fw, "%s", fw_name); 264 if (r) { 265 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 266 fw_name); 267 amdgpu_ucode_release(&adev->uvd.fw); 268 return r; 269 } 270 271 /* Set the default UVD handles that the firmware can handle */ 272 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 273 274 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 275 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 276 277 if (adev->asic_type < CHIP_VEGA20) { 278 unsigned int version_major, version_minor; 279 280 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 281 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 282 DRM_INFO("Found UVD firmware Version: %u.%u Family ID: %u\n", 283 version_major, version_minor, family_id); 284 285 /* 286 * Limit the number of UVD handles depending on microcode major 287 * and minor versions. The firmware version which has 40 UVD 288 * instances support is 1.80. So all subsequent versions should 289 * also have the same support. 290 */ 291 if ((version_major > 0x01) || 292 ((version_major == 0x01) && (version_minor >= 0x50))) 293 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 294 295 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 296 (family_id << 8)); 297 298 if ((adev->asic_type == CHIP_POLARIS10 || 299 adev->asic_type == CHIP_POLARIS11) && 300 (adev->uvd.fw_version < FW_1_66_16)) 301 DRM_ERROR("POLARIS10/11 UVD firmware version %u.%u is too old.\n", 302 version_major, version_minor); 303 } else { 304 unsigned int enc_major, enc_minor, dec_minor; 305 306 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 307 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f; 308 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3; 309 DRM_INFO("Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n", 310 enc_major, enc_minor, dec_minor, family_id); 311 312 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 313 314 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version); 315 } 316 317 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 318 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 319 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 320 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 321 322 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 323 if (adev->uvd.harvest_config & (1 << j)) 324 continue; 325 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 326 AMDGPU_GEM_DOMAIN_VRAM | 327 AMDGPU_GEM_DOMAIN_GTT, 328 &adev->uvd.inst[j].vcpu_bo, 329 &adev->uvd.inst[j].gpu_addr, 330 &adev->uvd.inst[j].cpu_addr); 331 if (r) { 332 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 333 return r; 334 } 335 } 336 337 for (i = 0; i < adev->uvd.max_handles; ++i) { 338 atomic_set(&adev->uvd.handles[i], 0); 339 adev->uvd.filp[i] = NULL; 340 } 341 342 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 343 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 344 adev->uvd.address_64_bit = true; 345 346 r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo); 347 if (r) 348 return r; 349 350 switch (adev->asic_type) { 351 case CHIP_TONGA: 352 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; 353 break; 354 case CHIP_CARRIZO: 355 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; 356 break; 357 case CHIP_FIJI: 358 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; 359 break; 360 case CHIP_STONEY: 361 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; 362 break; 363 default: 364 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; 365 } 366 367 return 0; 368 } 369 370 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 371 { 372 void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo); 373 int i, j; 374 375 drm_sched_entity_destroy(&adev->uvd.entity); 376 377 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 378 if (adev->uvd.harvest_config & (1 << j)) 379 continue; 380 kvfree(adev->uvd.inst[j].saved_bo); 381 382 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo, 383 &adev->uvd.inst[j].gpu_addr, 384 (void **)&adev->uvd.inst[j].cpu_addr); 385 386 amdgpu_ring_fini(&adev->uvd.inst[j].ring); 387 388 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) 389 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 390 } 391 amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr); 392 amdgpu_ucode_release(&adev->uvd.fw); 393 394 return 0; 395 } 396 397 /** 398 * amdgpu_uvd_entity_init - init entity 399 * 400 * @adev: amdgpu_device pointer 401 * @ring: amdgpu_ring pointer to check 402 * 403 * Initialize the entity used for handle management in the kernel driver. 404 */ 405 int amdgpu_uvd_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring) 406 { 407 if (ring == &adev->uvd.inst[0].ring) { 408 struct drm_gpu_scheduler *sched = &ring->sched; 409 int r; 410 411 r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL, 412 &sched, 1, NULL); 413 if (r) { 414 DRM_ERROR("Failed setting up UVD kernel entity.\n"); 415 return r; 416 } 417 } 418 419 return 0; 420 } 421 422 int amdgpu_uvd_prepare_suspend(struct amdgpu_device *adev) 423 { 424 unsigned int size; 425 void *ptr; 426 int i, j, idx; 427 428 cancel_delayed_work_sync(&adev->uvd.idle_work); 429 430 /* only valid for physical mode */ 431 if (adev->asic_type < CHIP_POLARIS10) { 432 for (i = 0; i < adev->uvd.max_handles; ++i) 433 if (atomic_read(&adev->uvd.handles[i])) 434 break; 435 436 if (i == adev->uvd.max_handles) 437 return 0; 438 } 439 440 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 441 if (adev->uvd.harvest_config & (1 << j)) 442 continue; 443 if (adev->uvd.inst[j].vcpu_bo == NULL) 444 continue; 445 446 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo); 447 ptr = adev->uvd.inst[j].cpu_addr; 448 449 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL); 450 if (!adev->uvd.inst[j].saved_bo) 451 return -ENOMEM; 452 453 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 454 /* re-write 0 since err_event_athub will corrupt VCPU buffer */ 455 if (amdgpu_ras_intr_triggered()) 456 memset(adev->uvd.inst[j].saved_bo, 0, size); 457 else 458 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); 459 460 drm_dev_exit(idx); 461 } 462 } 463 464 return 0; 465 } 466 467 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 468 { 469 if (amdgpu_ras_intr_triggered()) 470 DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n"); 471 472 return 0; 473 } 474 475 int amdgpu_uvd_resume(struct amdgpu_device *adev) 476 { 477 unsigned int size; 478 void *ptr; 479 int i, idx; 480 481 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 482 if (adev->uvd.harvest_config & (1 << i)) 483 continue; 484 if (adev->uvd.inst[i].vcpu_bo == NULL) 485 return -EINVAL; 486 487 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo); 488 ptr = adev->uvd.inst[i].cpu_addr; 489 490 if (adev->uvd.inst[i].saved_bo != NULL) { 491 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 492 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size); 493 drm_dev_exit(idx); 494 } 495 kvfree(adev->uvd.inst[i].saved_bo); 496 adev->uvd.inst[i].saved_bo = NULL; 497 } else { 498 const struct common_firmware_header *hdr; 499 unsigned int offset; 500 501 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 502 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 503 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 504 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 505 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, 506 le32_to_cpu(hdr->ucode_size_bytes)); 507 drm_dev_exit(idx); 508 } 509 size -= le32_to_cpu(hdr->ucode_size_bytes); 510 ptr += le32_to_cpu(hdr->ucode_size_bytes); 511 } 512 memset_io(ptr, 0, size); 513 /* to restore uvd fence seq */ 514 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring); 515 } 516 } 517 return 0; 518 } 519 520 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 521 { 522 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring; 523 int i, r; 524 525 for (i = 0; i < adev->uvd.max_handles; ++i) { 526 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 527 528 if (handle != 0 && adev->uvd.filp[i] == filp) { 529 struct dma_fence *fence; 530 531 r = amdgpu_uvd_get_destroy_msg(ring, handle, false, 532 &fence); 533 if (r) { 534 DRM_ERROR("Error destroying UVD %d!\n", r); 535 continue; 536 } 537 538 dma_fence_wait(fence, false); 539 dma_fence_put(fence); 540 541 adev->uvd.filp[i] = NULL; 542 atomic_set(&adev->uvd.handles[i], 0); 543 } 544 } 545 } 546 547 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 548 { 549 int i; 550 551 for (i = 0; i < abo->placement.num_placement; ++i) { 552 abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 553 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 554 if (abo->placements[i].mem_type == TTM_PL_VRAM) 555 abo->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS; 556 } 557 } 558 559 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) 560 { 561 uint32_t lo, hi; 562 uint64_t addr; 563 564 lo = amdgpu_ib_get_value(ctx->ib, ctx->data0); 565 hi = amdgpu_ib_get_value(ctx->ib, ctx->data1); 566 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 567 568 return addr; 569 } 570 571 /** 572 * amdgpu_uvd_cs_pass1 - first parsing round 573 * 574 * @ctx: UVD parser context 575 * 576 * Make sure UVD message and feedback buffers are in VRAM and 577 * nobody is violating an 256MB boundary. 578 */ 579 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 580 { 581 struct ttm_operation_ctx tctx = { false, false }; 582 struct amdgpu_bo_va_mapping *mapping; 583 struct amdgpu_bo *bo; 584 uint32_t cmd; 585 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 586 int r = 0; 587 588 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 589 if (r) { 590 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 591 return r; 592 } 593 594 if (!ctx->parser->adev->uvd.address_64_bit) { 595 /* check if it's a message or feedback command */ 596 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1; 597 if (cmd == 0x0 || cmd == 0x3) { 598 /* yes, force it into VRAM */ 599 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 600 601 amdgpu_bo_placement_from_domain(bo, domain); 602 } 603 amdgpu_uvd_force_into_uvd_segment(bo); 604 605 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); 606 } 607 608 return r; 609 } 610 611 /** 612 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 613 * 614 * @adev: amdgpu_device pointer 615 * @msg: pointer to message structure 616 * @buf_sizes: placeholder to put the different buffer lengths 617 * 618 * Peek into the decode message and calculate the necessary buffer sizes. 619 */ 620 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 621 unsigned int buf_sizes[]) 622 { 623 unsigned int stream_type = msg[4]; 624 unsigned int width = msg[6]; 625 unsigned int height = msg[7]; 626 unsigned int dpb_size = msg[9]; 627 unsigned int pitch = msg[28]; 628 unsigned int level = msg[57]; 629 630 unsigned int width_in_mb = width / 16; 631 unsigned int height_in_mb = ALIGN(height / 16, 2); 632 unsigned int fs_in_mb = width_in_mb * height_in_mb; 633 634 unsigned int image_size, tmp, min_dpb_size, num_dpb_buffer; 635 unsigned int min_ctx_size = ~0; 636 637 image_size = width * height; 638 image_size += image_size / 2; 639 image_size = ALIGN(image_size, 1024); 640 641 switch (stream_type) { 642 case 0: /* H264 */ 643 switch (level) { 644 case 30: 645 num_dpb_buffer = 8100 / fs_in_mb; 646 break; 647 case 31: 648 num_dpb_buffer = 18000 / fs_in_mb; 649 break; 650 case 32: 651 num_dpb_buffer = 20480 / fs_in_mb; 652 break; 653 case 41: 654 num_dpb_buffer = 32768 / fs_in_mb; 655 break; 656 case 42: 657 num_dpb_buffer = 34816 / fs_in_mb; 658 break; 659 case 50: 660 num_dpb_buffer = 110400 / fs_in_mb; 661 break; 662 case 51: 663 num_dpb_buffer = 184320 / fs_in_mb; 664 break; 665 default: 666 num_dpb_buffer = 184320 / fs_in_mb; 667 break; 668 } 669 num_dpb_buffer++; 670 if (num_dpb_buffer > 17) 671 num_dpb_buffer = 17; 672 673 /* reference picture buffer */ 674 min_dpb_size = image_size * num_dpb_buffer; 675 676 /* macroblock context buffer */ 677 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 678 679 /* IT surface buffer */ 680 min_dpb_size += width_in_mb * height_in_mb * 32; 681 break; 682 683 case 1: /* VC1 */ 684 685 /* reference picture buffer */ 686 min_dpb_size = image_size * 3; 687 688 /* CONTEXT_BUFFER */ 689 min_dpb_size += width_in_mb * height_in_mb * 128; 690 691 /* IT surface buffer */ 692 min_dpb_size += width_in_mb * 64; 693 694 /* DB surface buffer */ 695 min_dpb_size += width_in_mb * 128; 696 697 /* BP */ 698 tmp = max(width_in_mb, height_in_mb); 699 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 700 break; 701 702 case 3: /* MPEG2 */ 703 704 /* reference picture buffer */ 705 min_dpb_size = image_size * 3; 706 break; 707 708 case 4: /* MPEG4 */ 709 710 /* reference picture buffer */ 711 min_dpb_size = image_size * 3; 712 713 /* CM */ 714 min_dpb_size += width_in_mb * height_in_mb * 64; 715 716 /* IT surface buffer */ 717 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 718 break; 719 720 case 7: /* H264 Perf */ 721 switch (level) { 722 case 30: 723 num_dpb_buffer = 8100 / fs_in_mb; 724 break; 725 case 31: 726 num_dpb_buffer = 18000 / fs_in_mb; 727 break; 728 case 32: 729 num_dpb_buffer = 20480 / fs_in_mb; 730 break; 731 case 41: 732 num_dpb_buffer = 32768 / fs_in_mb; 733 break; 734 case 42: 735 num_dpb_buffer = 34816 / fs_in_mb; 736 break; 737 case 50: 738 num_dpb_buffer = 110400 / fs_in_mb; 739 break; 740 case 51: 741 num_dpb_buffer = 184320 / fs_in_mb; 742 break; 743 default: 744 num_dpb_buffer = 184320 / fs_in_mb; 745 break; 746 } 747 num_dpb_buffer++; 748 if (num_dpb_buffer > 17) 749 num_dpb_buffer = 17; 750 751 /* reference picture buffer */ 752 min_dpb_size = image_size * num_dpb_buffer; 753 754 if (!adev->uvd.use_ctx_buf) { 755 /* macroblock context buffer */ 756 min_dpb_size += 757 width_in_mb * height_in_mb * num_dpb_buffer * 192; 758 759 /* IT surface buffer */ 760 min_dpb_size += width_in_mb * height_in_mb * 32; 761 } else { 762 /* macroblock context buffer */ 763 min_ctx_size = 764 width_in_mb * height_in_mb * num_dpb_buffer * 192; 765 } 766 break; 767 768 case 8: /* MJPEG */ 769 min_dpb_size = 0; 770 break; 771 772 case 16: /* H265 */ 773 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 774 image_size = ALIGN(image_size, 256); 775 776 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 777 min_dpb_size = image_size * num_dpb_buffer; 778 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 779 * 16 * num_dpb_buffer + 52 * 1024; 780 break; 781 782 default: 783 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 784 return -EINVAL; 785 } 786 787 if (width > pitch) { 788 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 789 return -EINVAL; 790 } 791 792 if (dpb_size < min_dpb_size) { 793 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 794 dpb_size, min_dpb_size); 795 return -EINVAL; 796 } 797 798 buf_sizes[0x1] = dpb_size; 799 buf_sizes[0x2] = image_size; 800 buf_sizes[0x4] = min_ctx_size; 801 /* store image width to adjust nb memory pstate */ 802 adev->uvd.decode_image_width = width; 803 return 0; 804 } 805 806 /** 807 * amdgpu_uvd_cs_msg - handle UVD message 808 * 809 * @ctx: UVD parser context 810 * @bo: buffer object containing the message 811 * @offset: offset into the buffer object 812 * 813 * Peek into the UVD message and extract the session id. 814 * Make sure that we don't open up to many sessions. 815 */ 816 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 817 struct amdgpu_bo *bo, unsigned int offset) 818 { 819 struct amdgpu_device *adev = ctx->parser->adev; 820 int32_t *msg, msg_type, handle; 821 void *ptr; 822 long r; 823 int i; 824 825 if (offset & 0x3F) { 826 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 827 return -EINVAL; 828 } 829 830 r = amdgpu_bo_kmap(bo, &ptr); 831 if (r) { 832 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r); 833 return r; 834 } 835 836 msg = ptr + offset; 837 838 msg_type = msg[1]; 839 handle = msg[2]; 840 841 if (handle == 0) { 842 amdgpu_bo_kunmap(bo); 843 DRM_ERROR("Invalid UVD handle!\n"); 844 return -EINVAL; 845 } 846 847 switch (msg_type) { 848 case 0: 849 /* it's a create msg, calc image size (width * height) */ 850 amdgpu_bo_kunmap(bo); 851 852 /* try to alloc a new handle */ 853 for (i = 0; i < adev->uvd.max_handles; ++i) { 854 if (atomic_read(&adev->uvd.handles[i]) == handle) { 855 DRM_ERROR(")Handle 0x%x already in use!\n", 856 handle); 857 return -EINVAL; 858 } 859 860 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 861 adev->uvd.filp[i] = ctx->parser->filp; 862 return 0; 863 } 864 } 865 866 DRM_ERROR("No more free UVD handles!\n"); 867 return -ENOSPC; 868 869 case 1: 870 /* it's a decode msg, calc buffer sizes */ 871 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 872 amdgpu_bo_kunmap(bo); 873 if (r) 874 return r; 875 876 /* validate the handle */ 877 for (i = 0; i < adev->uvd.max_handles; ++i) { 878 if (atomic_read(&adev->uvd.handles[i]) == handle) { 879 if (adev->uvd.filp[i] != ctx->parser->filp) { 880 DRM_ERROR("UVD handle collision detected!\n"); 881 return -EINVAL; 882 } 883 return 0; 884 } 885 } 886 887 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 888 return -ENOENT; 889 890 case 2: 891 /* it's a destroy msg, free the handle */ 892 for (i = 0; i < adev->uvd.max_handles; ++i) 893 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 894 amdgpu_bo_kunmap(bo); 895 return 0; 896 897 default: 898 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 899 } 900 901 amdgpu_bo_kunmap(bo); 902 return -EINVAL; 903 } 904 905 /** 906 * amdgpu_uvd_cs_pass2 - second parsing round 907 * 908 * @ctx: UVD parser context 909 * 910 * Patch buffer addresses, make sure buffer sizes are correct. 911 */ 912 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 913 { 914 struct amdgpu_bo_va_mapping *mapping; 915 struct amdgpu_bo *bo; 916 uint32_t cmd; 917 uint64_t start, end; 918 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 919 int r; 920 921 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 922 if (r) { 923 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 924 return r; 925 } 926 927 start = amdgpu_bo_gpu_offset(bo); 928 929 end = (mapping->last + 1 - mapping->start); 930 end = end * AMDGPU_GPU_PAGE_SIZE + start; 931 932 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; 933 start += addr; 934 935 amdgpu_ib_set_value(ctx->ib, ctx->data0, lower_32_bits(start)); 936 amdgpu_ib_set_value(ctx->ib, ctx->data1, upper_32_bits(start)); 937 938 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1; 939 if (cmd < 0x4) { 940 if ((end - start) < ctx->buf_sizes[cmd]) { 941 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 942 (unsigned int)(end - start), 943 ctx->buf_sizes[cmd]); 944 return -EINVAL; 945 } 946 947 } else if (cmd == 0x206) { 948 if ((end - start) < ctx->buf_sizes[4]) { 949 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 950 (unsigned int)(end - start), 951 ctx->buf_sizes[4]); 952 return -EINVAL; 953 } 954 } else if ((cmd != 0x100) && (cmd != 0x204)) { 955 DRM_ERROR("invalid UVD command %X!\n", cmd); 956 return -EINVAL; 957 } 958 959 if (!ctx->parser->adev->uvd.address_64_bit) { 960 if ((start >> 28) != ((end - 1) >> 28)) { 961 DRM_ERROR("reloc %llx-%llx crossing 256MB boundary!\n", 962 start, end); 963 return -EINVAL; 964 } 965 966 if ((cmd == 0 || cmd == 0x3) && 967 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) { 968 DRM_ERROR("msg/fb buffer %llx-%llx out of 256MB segment!\n", 969 start, end); 970 return -EINVAL; 971 } 972 } 973 974 if (cmd == 0) { 975 ctx->has_msg_cmd = true; 976 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 977 if (r) 978 return r; 979 } else if (!ctx->has_msg_cmd) { 980 DRM_ERROR("Message needed before other commands are send!\n"); 981 return -EINVAL; 982 } 983 984 return 0; 985 } 986 987 /** 988 * amdgpu_uvd_cs_reg - parse register writes 989 * 990 * @ctx: UVD parser context 991 * @cb: callback function 992 * 993 * Parse the register writes, call cb on each complete command. 994 */ 995 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 996 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 997 { 998 int i, r; 999 1000 ctx->idx++; 1001 for (i = 0; i <= ctx->count; ++i) { 1002 unsigned int reg = ctx->reg + i; 1003 1004 if (ctx->idx >= ctx->ib->length_dw) { 1005 DRM_ERROR("Register command after end of CS!\n"); 1006 return -EINVAL; 1007 } 1008 1009 switch (reg) { 1010 case mmUVD_GPCOM_VCPU_DATA0: 1011 ctx->data0 = ctx->idx; 1012 break; 1013 case mmUVD_GPCOM_VCPU_DATA1: 1014 ctx->data1 = ctx->idx; 1015 break; 1016 case mmUVD_GPCOM_VCPU_CMD: 1017 r = cb(ctx); 1018 if (r) 1019 return r; 1020 break; 1021 case mmUVD_ENGINE_CNTL: 1022 case mmUVD_NO_OP: 1023 break; 1024 default: 1025 DRM_ERROR("Invalid reg 0x%X!\n", reg); 1026 return -EINVAL; 1027 } 1028 ctx->idx++; 1029 } 1030 return 0; 1031 } 1032 1033 /** 1034 * amdgpu_uvd_cs_packets - parse UVD packets 1035 * 1036 * @ctx: UVD parser context 1037 * @cb: callback function 1038 * 1039 * Parse the command stream packets. 1040 */ 1041 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 1042 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 1043 { 1044 int r; 1045 1046 for (ctx->idx = 0 ; ctx->idx < ctx->ib->length_dw; ) { 1047 uint32_t cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx); 1048 unsigned int type = CP_PACKET_GET_TYPE(cmd); 1049 1050 switch (type) { 1051 case PACKET_TYPE0: 1052 ctx->reg = CP_PACKET0_GET_REG(cmd); 1053 ctx->count = CP_PACKET_GET_COUNT(cmd); 1054 r = amdgpu_uvd_cs_reg(ctx, cb); 1055 if (r) 1056 return r; 1057 break; 1058 case PACKET_TYPE2: 1059 ++ctx->idx; 1060 break; 1061 default: 1062 DRM_ERROR("Unknown packet type %d !\n", type); 1063 return -EINVAL; 1064 } 1065 } 1066 return 0; 1067 } 1068 1069 /** 1070 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 1071 * 1072 * @parser: Command submission parser context 1073 * @job: the job to parse 1074 * @ib: the IB to patch 1075 * 1076 * Parse the command stream, patch in addresses as necessary. 1077 */ 1078 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, 1079 struct amdgpu_job *job, 1080 struct amdgpu_ib *ib) 1081 { 1082 struct amdgpu_uvd_cs_ctx ctx = {}; 1083 unsigned int buf_sizes[] = { 1084 [0x00000000] = 2048, 1085 [0x00000001] = 0xFFFFFFFF, 1086 [0x00000002] = 0xFFFFFFFF, 1087 [0x00000003] = 2048, 1088 [0x00000004] = 0xFFFFFFFF, 1089 }; 1090 int r; 1091 1092 job->vm = NULL; 1093 1094 if (ib->length_dw % 16) { 1095 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 1096 ib->length_dw); 1097 return -EINVAL; 1098 } 1099 1100 ctx.parser = parser; 1101 ctx.buf_sizes = buf_sizes; 1102 ctx.ib = ib; 1103 1104 /* first round only required on chips without UVD 64 bit address support */ 1105 if (!parser->adev->uvd.address_64_bit) { 1106 /* first round, make sure the buffers are actually in the UVD segment */ 1107 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 1108 if (r) 1109 return r; 1110 } 1111 1112 /* second round, patch buffer addresses into the command stream */ 1113 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 1114 if (r) 1115 return r; 1116 1117 if (!ctx.has_msg_cmd) { 1118 DRM_ERROR("UVD-IBs need a msg command!\n"); 1119 return -EINVAL; 1120 } 1121 1122 return 0; 1123 } 1124 1125 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 1126 bool direct, struct dma_fence **fence) 1127 { 1128 struct amdgpu_device *adev = ring->adev; 1129 struct dma_fence *f = NULL; 1130 uint32_t offset, data[4]; 1131 struct amdgpu_job *job; 1132 struct amdgpu_ib *ib; 1133 uint64_t addr; 1134 int i, r; 1135 1136 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->uvd.entity, 1137 AMDGPU_FENCE_OWNER_UNDEFINED, 1138 64, direct ? AMDGPU_IB_POOL_DIRECT : 1139 AMDGPU_IB_POOL_DELAYED, &job); 1140 if (r) 1141 return r; 1142 1143 if (adev->asic_type >= CHIP_VEGA10) 1144 offset = adev->reg_offset[UVD_HWIP][ring->me][1]; 1145 else 1146 offset = UVD_BASE_SI; 1147 1148 data[0] = PACKET0(offset + UVD_GPCOM_VCPU_DATA0, 0); 1149 data[1] = PACKET0(offset + UVD_GPCOM_VCPU_DATA1, 0); 1150 data[2] = PACKET0(offset + UVD_GPCOM_VCPU_CMD, 0); 1151 data[3] = PACKET0(offset + UVD_NO_OP, 0); 1152 1153 ib = &job->ibs[0]; 1154 addr = amdgpu_bo_gpu_offset(bo); 1155 ib->ptr[0] = data[0]; 1156 ib->ptr[1] = addr; 1157 ib->ptr[2] = data[1]; 1158 ib->ptr[3] = addr >> 32; 1159 ib->ptr[4] = data[2]; 1160 ib->ptr[5] = 0; 1161 for (i = 6; i < 16; i += 2) { 1162 ib->ptr[i] = data[3]; 1163 ib->ptr[i+1] = 0; 1164 } 1165 ib->length_dw = 16; 1166 1167 if (direct) { 1168 r = amdgpu_job_submit_direct(job, ring, &f); 1169 if (r) 1170 goto err_free; 1171 } else { 1172 r = drm_sched_job_add_resv_dependencies(&job->base, 1173 bo->tbo.base.resv, 1174 DMA_RESV_USAGE_KERNEL); 1175 if (r) 1176 goto err_free; 1177 1178 f = amdgpu_job_submit(job); 1179 } 1180 1181 amdgpu_bo_reserve(bo, true); 1182 amdgpu_bo_fence(bo, f, false); 1183 amdgpu_bo_unreserve(bo); 1184 1185 if (fence) 1186 *fence = dma_fence_get(f); 1187 dma_fence_put(f); 1188 1189 return 0; 1190 1191 err_free: 1192 amdgpu_job_free(job); 1193 return r; 1194 } 1195 1196 /* multiple fence commands without any stream commands in between can 1197 * crash the vcpu so just try to emmit a dummy create/destroy msg to 1198 * avoid this 1199 */ 1200 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1201 struct dma_fence **fence) 1202 { 1203 struct amdgpu_device *adev = ring->adev; 1204 struct amdgpu_bo *bo = adev->uvd.ib_bo; 1205 uint32_t *msg; 1206 int i; 1207 1208 msg = amdgpu_bo_kptr(bo); 1209 /* stitch together an UVD create msg */ 1210 msg[0] = cpu_to_le32(0x00000de4); 1211 msg[1] = cpu_to_le32(0x00000000); 1212 msg[2] = cpu_to_le32(handle); 1213 msg[3] = cpu_to_le32(0x00000000); 1214 msg[4] = cpu_to_le32(0x00000000); 1215 msg[5] = cpu_to_le32(0x00000000); 1216 msg[6] = cpu_to_le32(0x00000000); 1217 msg[7] = cpu_to_le32(0x00000780); 1218 msg[8] = cpu_to_le32(0x00000440); 1219 msg[9] = cpu_to_le32(0x00000000); 1220 msg[10] = cpu_to_le32(0x01b37000); 1221 for (i = 11; i < 1024; ++i) 1222 msg[i] = cpu_to_le32(0x0); 1223 1224 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1225 1226 } 1227 1228 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1229 bool direct, struct dma_fence **fence) 1230 { 1231 struct amdgpu_device *adev = ring->adev; 1232 struct amdgpu_bo *bo = NULL; 1233 uint32_t *msg; 1234 int r, i; 1235 1236 if (direct) { 1237 bo = adev->uvd.ib_bo; 1238 } else { 1239 r = amdgpu_uvd_create_msg_bo_helper(adev, 4096, &bo); 1240 if (r) 1241 return r; 1242 } 1243 1244 msg = amdgpu_bo_kptr(bo); 1245 /* stitch together an UVD destroy msg */ 1246 msg[0] = cpu_to_le32(0x00000de4); 1247 msg[1] = cpu_to_le32(0x00000002); 1248 msg[2] = cpu_to_le32(handle); 1249 msg[3] = cpu_to_le32(0x00000000); 1250 for (i = 4; i < 1024; ++i) 1251 msg[i] = cpu_to_le32(0x0); 1252 1253 r = amdgpu_uvd_send_msg(ring, bo, direct, fence); 1254 1255 if (!direct) 1256 amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg); 1257 1258 return r; 1259 } 1260 1261 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1262 { 1263 struct amdgpu_device *adev = 1264 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1265 unsigned int fences = 0, i, j; 1266 1267 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1268 if (adev->uvd.harvest_config & (1 << i)) 1269 continue; 1270 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring); 1271 for (j = 0; j < adev->uvd.num_enc_rings; ++j) 1272 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]); 1273 } 1274 1275 if (fences == 0) { 1276 if (adev->pm.dpm_enabled) { 1277 amdgpu_dpm_enable_uvd(adev, false); 1278 } else { 1279 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1280 /* shutdown the UVD block */ 1281 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1282 AMD_PG_STATE_GATE); 1283 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1284 AMD_CG_STATE_GATE); 1285 } 1286 } else { 1287 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1288 } 1289 } 1290 1291 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 1292 { 1293 struct amdgpu_device *adev = ring->adev; 1294 bool set_clocks; 1295 1296 if (amdgpu_sriov_vf(adev)) 1297 return; 1298 1299 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1300 if (set_clocks) { 1301 if (adev->pm.dpm_enabled) { 1302 amdgpu_dpm_enable_uvd(adev, true); 1303 } else { 1304 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1305 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1306 AMD_CG_STATE_UNGATE); 1307 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1308 AMD_PG_STATE_UNGATE); 1309 } 1310 } 1311 } 1312 1313 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) 1314 { 1315 if (!amdgpu_sriov_vf(ring->adev)) 1316 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1317 } 1318 1319 /** 1320 * amdgpu_uvd_ring_test_ib - test ib execution 1321 * 1322 * @ring: amdgpu_ring pointer 1323 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1324 * 1325 * Test if we can successfully execute an IB 1326 */ 1327 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1328 { 1329 struct dma_fence *fence; 1330 long r; 1331 1332 r = amdgpu_uvd_get_create_msg(ring, 1, &fence); 1333 if (r) 1334 goto error; 1335 1336 r = dma_fence_wait_timeout(fence, false, timeout); 1337 dma_fence_put(fence); 1338 if (r == 0) 1339 r = -ETIMEDOUT; 1340 if (r < 0) 1341 goto error; 1342 1343 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 1344 if (r) 1345 goto error; 1346 1347 r = dma_fence_wait_timeout(fence, false, timeout); 1348 if (r == 0) 1349 r = -ETIMEDOUT; 1350 else if (r > 0) 1351 r = 0; 1352 1353 dma_fence_put(fence); 1354 1355 error: 1356 return r; 1357 } 1358 1359 /** 1360 * amdgpu_uvd_used_handles - returns used UVD handles 1361 * 1362 * @adev: amdgpu_device pointer 1363 * 1364 * Returns the number of UVD handles in use 1365 */ 1366 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) 1367 { 1368 unsigned int i; 1369 uint32_t used_handles = 0; 1370 1371 for (i = 0; i < adev->uvd.max_handles; ++i) { 1372 /* 1373 * Handles can be freed in any order, and not 1374 * necessarily linear. So we need to count 1375 * all non-zero handles. 1376 */ 1377 if (atomic_read(&adev->uvd.handles[i])) 1378 used_handles++; 1379 } 1380 1381 return used_handles; 1382 } 1383