1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 34 #include <drm/drm.h> 35 #include <drm/drm_drv.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_pm.h" 39 #include "amdgpu_uvd.h" 40 #include "amdgpu_cs.h" 41 #include "cikd.h" 42 #include "uvd/uvd_4_2_d.h" 43 44 #include "amdgpu_ras.h" 45 46 /* 1 second timeout */ 47 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) 48 49 /* Firmware versions for VI */ 50 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) 51 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) 52 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) 53 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) 54 55 /* Polaris10/11 firmware version */ 56 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 57 58 /* Firmware Names */ 59 #ifdef CONFIG_DRM_AMDGPU_SI 60 #define FIRMWARE_TAHITI "amdgpu/tahiti_uvd.bin" 61 #define FIRMWARE_VERDE "amdgpu/verde_uvd.bin" 62 #define FIRMWARE_PITCAIRN "amdgpu/pitcairn_uvd.bin" 63 #define FIRMWARE_OLAND "amdgpu/oland_uvd.bin" 64 #endif 65 #ifdef CONFIG_DRM_AMDGPU_CIK 66 #define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin" 67 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin" 68 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin" 69 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin" 70 #define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin" 71 #endif 72 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 73 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 74 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 75 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 76 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 77 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 78 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" 79 #define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin" 80 81 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" 82 #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin" 83 #define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin" 84 85 /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */ 86 #define UVD_GPCOM_VCPU_CMD 0x03c3 87 #define UVD_GPCOM_VCPU_DATA0 0x03c4 88 #define UVD_GPCOM_VCPU_DATA1 0x03c5 89 #define UVD_NO_OP 0x03ff 90 #define UVD_BASE_SI 0x3800 91 92 /* 93 * amdgpu_uvd_cs_ctx - Command submission parser context 94 * 95 * Used for emulating virtual memory support on UVD 4.2. 96 */ 97 struct amdgpu_uvd_cs_ctx { 98 struct amdgpu_cs_parser *parser; 99 unsigned int reg, count; 100 unsigned int data0, data1; 101 unsigned int idx; 102 struct amdgpu_ib *ib; 103 104 /* does the IB has a msg command */ 105 bool has_msg_cmd; 106 107 /* minimum buffer sizes */ 108 unsigned int *buf_sizes; 109 }; 110 111 #ifdef CONFIG_DRM_AMDGPU_SI 112 MODULE_FIRMWARE(FIRMWARE_TAHITI); 113 MODULE_FIRMWARE(FIRMWARE_VERDE); 114 MODULE_FIRMWARE(FIRMWARE_PITCAIRN); 115 MODULE_FIRMWARE(FIRMWARE_OLAND); 116 #endif 117 #ifdef CONFIG_DRM_AMDGPU_CIK 118 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 119 MODULE_FIRMWARE(FIRMWARE_KABINI); 120 MODULE_FIRMWARE(FIRMWARE_KAVERI); 121 MODULE_FIRMWARE(FIRMWARE_HAWAII); 122 MODULE_FIRMWARE(FIRMWARE_MULLINS); 123 #endif 124 MODULE_FIRMWARE(FIRMWARE_TONGA); 125 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 126 MODULE_FIRMWARE(FIRMWARE_FIJI); 127 MODULE_FIRMWARE(FIRMWARE_STONEY); 128 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 129 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 130 MODULE_FIRMWARE(FIRMWARE_POLARIS12); 131 MODULE_FIRMWARE(FIRMWARE_VEGAM); 132 133 MODULE_FIRMWARE(FIRMWARE_VEGA10); 134 MODULE_FIRMWARE(FIRMWARE_VEGA12); 135 MODULE_FIRMWARE(FIRMWARE_VEGA20); 136 137 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 138 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo); 139 140 static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev, 141 uint32_t size, 142 struct amdgpu_bo **bo_ptr) 143 { 144 struct ttm_operation_ctx ctx = { true, false }; 145 struct amdgpu_bo *bo = NULL; 146 void *addr; 147 int r; 148 149 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, 150 AMDGPU_GEM_DOMAIN_GTT, 151 &bo, NULL, &addr); 152 if (r) 153 return r; 154 155 if (adev->uvd.address_64_bit) 156 goto succ; 157 158 amdgpu_bo_kunmap(bo); 159 amdgpu_bo_unpin(bo); 160 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 161 amdgpu_uvd_force_into_uvd_segment(bo); 162 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 163 if (r) 164 goto err; 165 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM); 166 if (r) 167 goto err_pin; 168 r = amdgpu_bo_kmap(bo, &addr); 169 if (r) 170 goto err_kmap; 171 succ: 172 amdgpu_bo_unreserve(bo); 173 *bo_ptr = bo; 174 return 0; 175 err_kmap: 176 amdgpu_bo_unpin(bo); 177 err_pin: 178 err: 179 amdgpu_bo_unreserve(bo); 180 amdgpu_bo_unref(&bo); 181 return r; 182 } 183 184 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 185 { 186 unsigned long bo_size; 187 const char *fw_name; 188 const struct common_firmware_header *hdr; 189 unsigned int family_id; 190 int i, j, r; 191 192 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 193 194 switch (adev->asic_type) { 195 #ifdef CONFIG_DRM_AMDGPU_SI 196 case CHIP_TAHITI: 197 fw_name = FIRMWARE_TAHITI; 198 break; 199 case CHIP_VERDE: 200 fw_name = FIRMWARE_VERDE; 201 break; 202 case CHIP_PITCAIRN: 203 fw_name = FIRMWARE_PITCAIRN; 204 break; 205 case CHIP_OLAND: 206 fw_name = FIRMWARE_OLAND; 207 break; 208 #endif 209 #ifdef CONFIG_DRM_AMDGPU_CIK 210 case CHIP_BONAIRE: 211 fw_name = FIRMWARE_BONAIRE; 212 break; 213 case CHIP_KABINI: 214 fw_name = FIRMWARE_KABINI; 215 break; 216 case CHIP_KAVERI: 217 fw_name = FIRMWARE_KAVERI; 218 break; 219 case CHIP_HAWAII: 220 fw_name = FIRMWARE_HAWAII; 221 break; 222 case CHIP_MULLINS: 223 fw_name = FIRMWARE_MULLINS; 224 break; 225 #endif 226 case CHIP_TONGA: 227 fw_name = FIRMWARE_TONGA; 228 break; 229 case CHIP_FIJI: 230 fw_name = FIRMWARE_FIJI; 231 break; 232 case CHIP_CARRIZO: 233 fw_name = FIRMWARE_CARRIZO; 234 break; 235 case CHIP_STONEY: 236 fw_name = FIRMWARE_STONEY; 237 break; 238 case CHIP_POLARIS10: 239 fw_name = FIRMWARE_POLARIS10; 240 break; 241 case CHIP_POLARIS11: 242 fw_name = FIRMWARE_POLARIS11; 243 break; 244 case CHIP_POLARIS12: 245 fw_name = FIRMWARE_POLARIS12; 246 break; 247 case CHIP_VEGA10: 248 fw_name = FIRMWARE_VEGA10; 249 break; 250 case CHIP_VEGA12: 251 fw_name = FIRMWARE_VEGA12; 252 break; 253 case CHIP_VEGAM: 254 fw_name = FIRMWARE_VEGAM; 255 break; 256 case CHIP_VEGA20: 257 fw_name = FIRMWARE_VEGA20; 258 break; 259 default: 260 return -EINVAL; 261 } 262 263 r = amdgpu_ucode_request(adev, &adev->uvd.fw, AMDGPU_UCODE_REQUIRED, "%s", fw_name); 264 if (r) { 265 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 266 fw_name); 267 amdgpu_ucode_release(&adev->uvd.fw); 268 return r; 269 } 270 271 /* Set the default UVD handles that the firmware can handle */ 272 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 273 274 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 275 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 276 277 if (adev->asic_type < CHIP_VEGA20) { 278 unsigned int version_major, version_minor; 279 280 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 281 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 282 drm_info(adev_to_drm(adev), "Found UVD firmware Version: %u.%u Family ID: %u\n", 283 version_major, version_minor, family_id); 284 285 /* 286 * Limit the number of UVD handles depending on microcode major 287 * and minor versions. The firmware version which has 40 UVD 288 * instances support is 1.80. So all subsequent versions should 289 * also have the same support. 290 */ 291 if ((version_major > 0x01) || 292 ((version_major == 0x01) && (version_minor >= 0x50))) 293 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 294 295 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 296 (family_id << 8)); 297 298 if ((adev->asic_type == CHIP_POLARIS10 || 299 adev->asic_type == CHIP_POLARIS11) && 300 (adev->uvd.fw_version < FW_1_66_16)) 301 DRM_ERROR("POLARIS10/11 UVD firmware version %u.%u is too old.\n", 302 version_major, version_minor); 303 } else { 304 unsigned int enc_major, enc_minor, dec_minor; 305 306 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 307 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f; 308 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3; 309 drm_info(adev_to_drm(adev), "Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n", 310 enc_major, enc_minor, dec_minor, family_id); 311 312 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 313 314 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version); 315 } 316 317 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 318 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 319 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 320 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 321 322 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 323 if (adev->uvd.harvest_config & (1 << j)) 324 continue; 325 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 326 AMDGPU_GEM_DOMAIN_VRAM | 327 AMDGPU_GEM_DOMAIN_GTT, 328 &adev->uvd.inst[j].vcpu_bo, 329 &adev->uvd.inst[j].gpu_addr, 330 &adev->uvd.inst[j].cpu_addr); 331 if (r) { 332 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 333 return r; 334 } 335 } 336 337 for (i = 0; i < adev->uvd.max_handles; ++i) { 338 atomic_set(&adev->uvd.handles[i], 0); 339 adev->uvd.filp[i] = NULL; 340 } 341 342 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 343 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 344 adev->uvd.address_64_bit = true; 345 346 r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo); 347 if (r) 348 return r; 349 350 switch (adev->asic_type) { 351 case CHIP_TONGA: 352 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; 353 break; 354 case CHIP_CARRIZO: 355 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; 356 break; 357 case CHIP_FIJI: 358 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; 359 break; 360 case CHIP_STONEY: 361 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; 362 break; 363 default: 364 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; 365 } 366 367 return 0; 368 } 369 370 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 371 { 372 void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo); 373 int i, j; 374 375 drm_sched_entity_destroy(&adev->uvd.entity); 376 377 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 378 if (adev->uvd.harvest_config & (1 << j)) 379 continue; 380 kvfree(adev->uvd.inst[j].saved_bo); 381 382 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo, 383 &adev->uvd.inst[j].gpu_addr, 384 (void **)&adev->uvd.inst[j].cpu_addr); 385 386 amdgpu_ring_fini(&adev->uvd.inst[j].ring); 387 388 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) 389 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 390 } 391 amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr); 392 amdgpu_ucode_release(&adev->uvd.fw); 393 394 return 0; 395 } 396 397 /** 398 * amdgpu_uvd_entity_init - init entity 399 * 400 * @adev: amdgpu_device pointer 401 * @ring: amdgpu_ring pointer to check 402 * 403 * Initialize the entity used for handle management in the kernel driver. 404 */ 405 int amdgpu_uvd_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring) 406 { 407 if (ring == &adev->uvd.inst[0].ring) { 408 struct drm_gpu_scheduler *sched = &ring->sched; 409 int r; 410 411 r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL, 412 &sched, 1, NULL); 413 if (r) { 414 DRM_ERROR("Failed setting up UVD kernel entity.\n"); 415 return r; 416 } 417 } 418 419 return 0; 420 } 421 422 int amdgpu_uvd_prepare_suspend(struct amdgpu_device *adev) 423 { 424 unsigned int size; 425 void *ptr; 426 int i, j, idx; 427 428 cancel_delayed_work_sync(&adev->uvd.idle_work); 429 430 /* only valid for physical mode */ 431 if (adev->asic_type < CHIP_POLARIS10) { 432 for (i = 0; i < adev->uvd.max_handles; ++i) 433 if (atomic_read(&adev->uvd.handles[i])) 434 break; 435 436 if (i == adev->uvd.max_handles) 437 return 0; 438 } 439 440 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 441 if (adev->uvd.harvest_config & (1 << j)) 442 continue; 443 if (adev->uvd.inst[j].vcpu_bo == NULL) 444 continue; 445 446 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo); 447 ptr = adev->uvd.inst[j].cpu_addr; 448 449 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL); 450 if (!adev->uvd.inst[j].saved_bo) 451 return -ENOMEM; 452 453 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 454 /* re-write 0 since err_event_athub will corrupt VCPU buffer */ 455 if (amdgpu_ras_intr_triggered()) 456 memset(adev->uvd.inst[j].saved_bo, 0, size); 457 else 458 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); 459 460 drm_dev_exit(idx); 461 } 462 } 463 464 return 0; 465 } 466 467 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 468 { 469 if (amdgpu_ras_intr_triggered()) 470 drm_warn(adev_to_drm(adev), 471 "UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n"); 472 473 return 0; 474 } 475 476 int amdgpu_uvd_resume(struct amdgpu_device *adev) 477 { 478 unsigned int size; 479 void *ptr; 480 int i, idx; 481 482 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 483 if (adev->uvd.harvest_config & (1 << i)) 484 continue; 485 if (adev->uvd.inst[i].vcpu_bo == NULL) 486 return -EINVAL; 487 488 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo); 489 ptr = adev->uvd.inst[i].cpu_addr; 490 491 if (adev->uvd.inst[i].saved_bo != NULL) { 492 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 493 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size); 494 drm_dev_exit(idx); 495 } 496 kvfree(adev->uvd.inst[i].saved_bo); 497 adev->uvd.inst[i].saved_bo = NULL; 498 } else { 499 const struct common_firmware_header *hdr; 500 unsigned int offset; 501 502 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 503 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 504 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 505 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 506 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, 507 le32_to_cpu(hdr->ucode_size_bytes)); 508 drm_dev_exit(idx); 509 } 510 size -= le32_to_cpu(hdr->ucode_size_bytes); 511 ptr += le32_to_cpu(hdr->ucode_size_bytes); 512 } 513 memset_io(ptr, 0, size); 514 /* to restore uvd fence seq */ 515 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring); 516 } 517 } 518 return 0; 519 } 520 521 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 522 { 523 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring; 524 int i, r; 525 526 for (i = 0; i < adev->uvd.max_handles; ++i) { 527 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 528 529 if (handle != 0 && adev->uvd.filp[i] == filp) { 530 struct dma_fence *fence; 531 532 r = amdgpu_uvd_get_destroy_msg(ring, handle, false, 533 &fence); 534 if (r) { 535 DRM_ERROR("Error destroying UVD %d!\n", r); 536 continue; 537 } 538 539 dma_fence_wait(fence, false); 540 dma_fence_put(fence); 541 542 adev->uvd.filp[i] = NULL; 543 atomic_set(&adev->uvd.handles[i], 0); 544 } 545 } 546 } 547 548 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 549 { 550 int i; 551 552 for (i = 0; i < abo->placement.num_placement; ++i) { 553 abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 554 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 555 if (abo->placements[i].mem_type == TTM_PL_VRAM) 556 abo->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS; 557 } 558 } 559 560 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) 561 { 562 uint32_t lo, hi; 563 uint64_t addr; 564 565 lo = amdgpu_ib_get_value(ctx->ib, ctx->data0); 566 hi = amdgpu_ib_get_value(ctx->ib, ctx->data1); 567 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 568 569 return addr; 570 } 571 572 /** 573 * amdgpu_uvd_cs_pass1 - first parsing round 574 * 575 * @ctx: UVD parser context 576 * 577 * Make sure UVD message and feedback buffers are in VRAM and 578 * nobody is violating an 256MB boundary. 579 */ 580 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 581 { 582 struct ttm_operation_ctx tctx = { false, false }; 583 struct amdgpu_bo_va_mapping *mapping; 584 struct amdgpu_bo *bo; 585 uint32_t cmd; 586 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 587 int r = 0; 588 589 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 590 if (r) { 591 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 592 return r; 593 } 594 595 if (!ctx->parser->adev->uvd.address_64_bit) { 596 /* check if it's a message or feedback command */ 597 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1; 598 if (cmd == 0x0 || cmd == 0x3) { 599 /* yes, force it into VRAM */ 600 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 601 602 amdgpu_bo_placement_from_domain(bo, domain); 603 } 604 amdgpu_uvd_force_into_uvd_segment(bo); 605 606 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); 607 } 608 609 return r; 610 } 611 612 /** 613 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 614 * 615 * @adev: amdgpu_device pointer 616 * @msg: pointer to message structure 617 * @buf_sizes: placeholder to put the different buffer lengths 618 * 619 * Peek into the decode message and calculate the necessary buffer sizes. 620 */ 621 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 622 unsigned int buf_sizes[]) 623 { 624 unsigned int stream_type = msg[4]; 625 unsigned int width = msg[6]; 626 unsigned int height = msg[7]; 627 unsigned int dpb_size = msg[9]; 628 unsigned int pitch = msg[28]; 629 unsigned int level = msg[57]; 630 631 unsigned int width_in_mb = width / 16; 632 unsigned int height_in_mb = ALIGN(height / 16, 2); 633 unsigned int fs_in_mb = width_in_mb * height_in_mb; 634 635 unsigned int image_size, tmp, min_dpb_size, num_dpb_buffer; 636 unsigned int min_ctx_size = ~0; 637 638 image_size = width * height; 639 image_size += image_size / 2; 640 image_size = ALIGN(image_size, 1024); 641 642 switch (stream_type) { 643 case 0: /* H264 */ 644 switch (level) { 645 case 30: 646 num_dpb_buffer = 8100 / fs_in_mb; 647 break; 648 case 31: 649 num_dpb_buffer = 18000 / fs_in_mb; 650 break; 651 case 32: 652 num_dpb_buffer = 20480 / fs_in_mb; 653 break; 654 case 41: 655 num_dpb_buffer = 32768 / fs_in_mb; 656 break; 657 case 42: 658 num_dpb_buffer = 34816 / fs_in_mb; 659 break; 660 case 50: 661 num_dpb_buffer = 110400 / fs_in_mb; 662 break; 663 case 51: 664 num_dpb_buffer = 184320 / fs_in_mb; 665 break; 666 default: 667 num_dpb_buffer = 184320 / fs_in_mb; 668 break; 669 } 670 num_dpb_buffer++; 671 if (num_dpb_buffer > 17) 672 num_dpb_buffer = 17; 673 674 /* reference picture buffer */ 675 min_dpb_size = image_size * num_dpb_buffer; 676 677 /* macroblock context buffer */ 678 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 679 680 /* IT surface buffer */ 681 min_dpb_size += width_in_mb * height_in_mb * 32; 682 break; 683 684 case 1: /* VC1 */ 685 686 /* reference picture buffer */ 687 min_dpb_size = image_size * 3; 688 689 /* CONTEXT_BUFFER */ 690 min_dpb_size += width_in_mb * height_in_mb * 128; 691 692 /* IT surface buffer */ 693 min_dpb_size += width_in_mb * 64; 694 695 /* DB surface buffer */ 696 min_dpb_size += width_in_mb * 128; 697 698 /* BP */ 699 tmp = max(width_in_mb, height_in_mb); 700 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 701 break; 702 703 case 3: /* MPEG2 */ 704 705 /* reference picture buffer */ 706 min_dpb_size = image_size * 3; 707 break; 708 709 case 4: /* MPEG4 */ 710 711 /* reference picture buffer */ 712 min_dpb_size = image_size * 3; 713 714 /* CM */ 715 min_dpb_size += width_in_mb * height_in_mb * 64; 716 717 /* IT surface buffer */ 718 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 719 break; 720 721 case 7: /* H264 Perf */ 722 switch (level) { 723 case 30: 724 num_dpb_buffer = 8100 / fs_in_mb; 725 break; 726 case 31: 727 num_dpb_buffer = 18000 / fs_in_mb; 728 break; 729 case 32: 730 num_dpb_buffer = 20480 / fs_in_mb; 731 break; 732 case 41: 733 num_dpb_buffer = 32768 / fs_in_mb; 734 break; 735 case 42: 736 num_dpb_buffer = 34816 / fs_in_mb; 737 break; 738 case 50: 739 num_dpb_buffer = 110400 / fs_in_mb; 740 break; 741 case 51: 742 num_dpb_buffer = 184320 / fs_in_mb; 743 break; 744 default: 745 num_dpb_buffer = 184320 / fs_in_mb; 746 break; 747 } 748 num_dpb_buffer++; 749 if (num_dpb_buffer > 17) 750 num_dpb_buffer = 17; 751 752 /* reference picture buffer */ 753 min_dpb_size = image_size * num_dpb_buffer; 754 755 if (!adev->uvd.use_ctx_buf) { 756 /* macroblock context buffer */ 757 min_dpb_size += 758 width_in_mb * height_in_mb * num_dpb_buffer * 192; 759 760 /* IT surface buffer */ 761 min_dpb_size += width_in_mb * height_in_mb * 32; 762 } else { 763 /* macroblock context buffer */ 764 min_ctx_size = 765 width_in_mb * height_in_mb * num_dpb_buffer * 192; 766 } 767 break; 768 769 case 8: /* MJPEG */ 770 min_dpb_size = 0; 771 break; 772 773 case 16: /* H265 */ 774 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 775 image_size = ALIGN(image_size, 256); 776 777 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 778 min_dpb_size = image_size * num_dpb_buffer; 779 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 780 * 16 * num_dpb_buffer + 52 * 1024; 781 break; 782 783 default: 784 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 785 return -EINVAL; 786 } 787 788 if (width > pitch) { 789 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 790 return -EINVAL; 791 } 792 793 if (dpb_size < min_dpb_size) { 794 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 795 dpb_size, min_dpb_size); 796 return -EINVAL; 797 } 798 799 buf_sizes[0x1] = dpb_size; 800 buf_sizes[0x2] = image_size; 801 buf_sizes[0x4] = min_ctx_size; 802 /* store image width to adjust nb memory pstate */ 803 adev->uvd.decode_image_width = width; 804 return 0; 805 } 806 807 /** 808 * amdgpu_uvd_cs_msg - handle UVD message 809 * 810 * @ctx: UVD parser context 811 * @bo: buffer object containing the message 812 * @offset: offset into the buffer object 813 * 814 * Peek into the UVD message and extract the session id. 815 * Make sure that we don't open up to many sessions. 816 */ 817 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 818 struct amdgpu_bo *bo, unsigned int offset) 819 { 820 struct amdgpu_device *adev = ctx->parser->adev; 821 int32_t *msg, msg_type, handle; 822 void *ptr; 823 long r; 824 int i; 825 826 if (offset & 0x3F) { 827 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 828 return -EINVAL; 829 } 830 831 r = amdgpu_bo_kmap(bo, &ptr); 832 if (r) { 833 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r); 834 return r; 835 } 836 837 msg = ptr + offset; 838 839 msg_type = msg[1]; 840 handle = msg[2]; 841 842 if (handle == 0) { 843 amdgpu_bo_kunmap(bo); 844 DRM_ERROR("Invalid UVD handle!\n"); 845 return -EINVAL; 846 } 847 848 switch (msg_type) { 849 case 0: 850 /* it's a create msg, calc image size (width * height) */ 851 amdgpu_bo_kunmap(bo); 852 853 /* try to alloc a new handle */ 854 for (i = 0; i < adev->uvd.max_handles; ++i) { 855 if (atomic_read(&adev->uvd.handles[i]) == handle) { 856 DRM_ERROR(")Handle 0x%x already in use!\n", 857 handle); 858 return -EINVAL; 859 } 860 861 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 862 adev->uvd.filp[i] = ctx->parser->filp; 863 return 0; 864 } 865 } 866 867 DRM_ERROR("No more free UVD handles!\n"); 868 return -ENOSPC; 869 870 case 1: 871 /* it's a decode msg, calc buffer sizes */ 872 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 873 amdgpu_bo_kunmap(bo); 874 if (r) 875 return r; 876 877 /* validate the handle */ 878 for (i = 0; i < adev->uvd.max_handles; ++i) { 879 if (atomic_read(&adev->uvd.handles[i]) == handle) { 880 if (adev->uvd.filp[i] != ctx->parser->filp) { 881 DRM_ERROR("UVD handle collision detected!\n"); 882 return -EINVAL; 883 } 884 return 0; 885 } 886 } 887 888 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 889 return -ENOENT; 890 891 case 2: 892 /* it's a destroy msg, free the handle */ 893 for (i = 0; i < adev->uvd.max_handles; ++i) 894 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 895 amdgpu_bo_kunmap(bo); 896 return 0; 897 898 default: 899 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 900 } 901 902 amdgpu_bo_kunmap(bo); 903 return -EINVAL; 904 } 905 906 /** 907 * amdgpu_uvd_cs_pass2 - second parsing round 908 * 909 * @ctx: UVD parser context 910 * 911 * Patch buffer addresses, make sure buffer sizes are correct. 912 */ 913 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 914 { 915 struct amdgpu_bo_va_mapping *mapping; 916 struct amdgpu_bo *bo; 917 uint32_t cmd; 918 uint64_t start, end; 919 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 920 int r; 921 922 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 923 if (r) { 924 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 925 return r; 926 } 927 928 start = amdgpu_bo_gpu_offset(bo); 929 930 end = (mapping->last + 1 - mapping->start); 931 end = end * AMDGPU_GPU_PAGE_SIZE + start; 932 933 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; 934 start += addr; 935 936 amdgpu_ib_set_value(ctx->ib, ctx->data0, lower_32_bits(start)); 937 amdgpu_ib_set_value(ctx->ib, ctx->data1, upper_32_bits(start)); 938 939 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1; 940 if (cmd < 0x4) { 941 if ((end - start) < ctx->buf_sizes[cmd]) { 942 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 943 (unsigned int)(end - start), 944 ctx->buf_sizes[cmd]); 945 return -EINVAL; 946 } 947 948 } else if (cmd == 0x206) { 949 if ((end - start) < ctx->buf_sizes[4]) { 950 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 951 (unsigned int)(end - start), 952 ctx->buf_sizes[4]); 953 return -EINVAL; 954 } 955 } else if ((cmd != 0x100) && (cmd != 0x204)) { 956 DRM_ERROR("invalid UVD command %X!\n", cmd); 957 return -EINVAL; 958 } 959 960 if (!ctx->parser->adev->uvd.address_64_bit) { 961 if ((start >> 28) != ((end - 1) >> 28)) { 962 DRM_ERROR("reloc %llx-%llx crossing 256MB boundary!\n", 963 start, end); 964 return -EINVAL; 965 } 966 967 if ((cmd == 0 || cmd == 0x3) && 968 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) { 969 DRM_ERROR("msg/fb buffer %llx-%llx out of 256MB segment!\n", 970 start, end); 971 return -EINVAL; 972 } 973 } 974 975 if (cmd == 0) { 976 ctx->has_msg_cmd = true; 977 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 978 if (r) 979 return r; 980 } else if (!ctx->has_msg_cmd) { 981 DRM_ERROR("Message needed before other commands are send!\n"); 982 return -EINVAL; 983 } 984 985 return 0; 986 } 987 988 /** 989 * amdgpu_uvd_cs_reg - parse register writes 990 * 991 * @ctx: UVD parser context 992 * @cb: callback function 993 * 994 * Parse the register writes, call cb on each complete command. 995 */ 996 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 997 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 998 { 999 int i, r; 1000 1001 ctx->idx++; 1002 for (i = 0; i <= ctx->count; ++i) { 1003 unsigned int reg = ctx->reg + i; 1004 1005 if (ctx->idx >= ctx->ib->length_dw) { 1006 DRM_ERROR("Register command after end of CS!\n"); 1007 return -EINVAL; 1008 } 1009 1010 switch (reg) { 1011 case mmUVD_GPCOM_VCPU_DATA0: 1012 ctx->data0 = ctx->idx; 1013 break; 1014 case mmUVD_GPCOM_VCPU_DATA1: 1015 ctx->data1 = ctx->idx; 1016 break; 1017 case mmUVD_GPCOM_VCPU_CMD: 1018 r = cb(ctx); 1019 if (r) 1020 return r; 1021 break; 1022 case mmUVD_ENGINE_CNTL: 1023 case mmUVD_NO_OP: 1024 break; 1025 default: 1026 DRM_ERROR("Invalid reg 0x%X!\n", reg); 1027 return -EINVAL; 1028 } 1029 ctx->idx++; 1030 } 1031 return 0; 1032 } 1033 1034 /** 1035 * amdgpu_uvd_cs_packets - parse UVD packets 1036 * 1037 * @ctx: UVD parser context 1038 * @cb: callback function 1039 * 1040 * Parse the command stream packets. 1041 */ 1042 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 1043 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 1044 { 1045 int r; 1046 1047 for (ctx->idx = 0 ; ctx->idx < ctx->ib->length_dw; ) { 1048 uint32_t cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx); 1049 unsigned int type = CP_PACKET_GET_TYPE(cmd); 1050 1051 switch (type) { 1052 case PACKET_TYPE0: 1053 ctx->reg = CP_PACKET0_GET_REG(cmd); 1054 ctx->count = CP_PACKET_GET_COUNT(cmd); 1055 r = amdgpu_uvd_cs_reg(ctx, cb); 1056 if (r) 1057 return r; 1058 break; 1059 case PACKET_TYPE2: 1060 ++ctx->idx; 1061 break; 1062 default: 1063 DRM_ERROR("Unknown packet type %d !\n", type); 1064 return -EINVAL; 1065 } 1066 } 1067 return 0; 1068 } 1069 1070 /** 1071 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 1072 * 1073 * @parser: Command submission parser context 1074 * @job: the job to parse 1075 * @ib: the IB to patch 1076 * 1077 * Parse the command stream, patch in addresses as necessary. 1078 */ 1079 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, 1080 struct amdgpu_job *job, 1081 struct amdgpu_ib *ib) 1082 { 1083 struct amdgpu_uvd_cs_ctx ctx = {}; 1084 unsigned int buf_sizes[] = { 1085 [0x00000000] = 2048, 1086 [0x00000001] = 0xFFFFFFFF, 1087 [0x00000002] = 0xFFFFFFFF, 1088 [0x00000003] = 2048, 1089 [0x00000004] = 0xFFFFFFFF, 1090 }; 1091 int r; 1092 1093 job->vm = NULL; 1094 1095 if (ib->length_dw % 16) { 1096 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 1097 ib->length_dw); 1098 return -EINVAL; 1099 } 1100 1101 ctx.parser = parser; 1102 ctx.buf_sizes = buf_sizes; 1103 ctx.ib = ib; 1104 1105 /* first round only required on chips without UVD 64 bit address support */ 1106 if (!parser->adev->uvd.address_64_bit) { 1107 /* first round, make sure the buffers are actually in the UVD segment */ 1108 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 1109 if (r) 1110 return r; 1111 } 1112 1113 /* second round, patch buffer addresses into the command stream */ 1114 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 1115 if (r) 1116 return r; 1117 1118 if (!ctx.has_msg_cmd) { 1119 DRM_ERROR("UVD-IBs need a msg command!\n"); 1120 return -EINVAL; 1121 } 1122 1123 return 0; 1124 } 1125 1126 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 1127 bool direct, struct dma_fence **fence) 1128 { 1129 struct amdgpu_device *adev = ring->adev; 1130 struct dma_fence *f = NULL; 1131 uint32_t offset, data[4]; 1132 struct amdgpu_job *job; 1133 struct amdgpu_ib *ib; 1134 uint64_t addr; 1135 int i, r; 1136 1137 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->uvd.entity, 1138 AMDGPU_FENCE_OWNER_UNDEFINED, 1139 64, direct ? AMDGPU_IB_POOL_DIRECT : 1140 AMDGPU_IB_POOL_DELAYED, &job, 1141 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); 1142 if (r) 1143 return r; 1144 1145 if (adev->asic_type >= CHIP_VEGA10) 1146 offset = adev->reg_offset[UVD_HWIP][ring->me][1]; 1147 else 1148 offset = UVD_BASE_SI; 1149 1150 data[0] = PACKET0(offset + UVD_GPCOM_VCPU_DATA0, 0); 1151 data[1] = PACKET0(offset + UVD_GPCOM_VCPU_DATA1, 0); 1152 data[2] = PACKET0(offset + UVD_GPCOM_VCPU_CMD, 0); 1153 data[3] = PACKET0(offset + UVD_NO_OP, 0); 1154 1155 ib = &job->ibs[0]; 1156 addr = amdgpu_bo_gpu_offset(bo); 1157 ib->ptr[0] = data[0]; 1158 ib->ptr[1] = addr; 1159 ib->ptr[2] = data[1]; 1160 ib->ptr[3] = addr >> 32; 1161 ib->ptr[4] = data[2]; 1162 ib->ptr[5] = 0; 1163 for (i = 6; i < 16; i += 2) { 1164 ib->ptr[i] = data[3]; 1165 ib->ptr[i+1] = 0; 1166 } 1167 ib->length_dw = 16; 1168 1169 if (direct) { 1170 r = amdgpu_job_submit_direct(job, ring, &f); 1171 if (r) 1172 goto err_free; 1173 } else { 1174 r = drm_sched_job_add_resv_dependencies(&job->base, 1175 bo->tbo.base.resv, 1176 DMA_RESV_USAGE_KERNEL); 1177 if (r) 1178 goto err_free; 1179 1180 f = amdgpu_job_submit(job); 1181 } 1182 1183 amdgpu_bo_reserve(bo, true); 1184 amdgpu_bo_fence(bo, f, false); 1185 amdgpu_bo_unreserve(bo); 1186 1187 if (fence) 1188 *fence = dma_fence_get(f); 1189 dma_fence_put(f); 1190 1191 return 0; 1192 1193 err_free: 1194 amdgpu_job_free(job); 1195 return r; 1196 } 1197 1198 /* multiple fence commands without any stream commands in between can 1199 * crash the vcpu so just try to emmit a dummy create/destroy msg to 1200 * avoid this 1201 */ 1202 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1203 struct dma_fence **fence) 1204 { 1205 struct amdgpu_device *adev = ring->adev; 1206 struct amdgpu_bo *bo = adev->uvd.ib_bo; 1207 uint32_t *msg; 1208 int i; 1209 1210 msg = amdgpu_bo_kptr(bo); 1211 /* stitch together an UVD create msg */ 1212 msg[0] = cpu_to_le32(0x00000de4); 1213 msg[1] = cpu_to_le32(0x00000000); 1214 msg[2] = cpu_to_le32(handle); 1215 msg[3] = cpu_to_le32(0x00000000); 1216 msg[4] = cpu_to_le32(0x00000000); 1217 msg[5] = cpu_to_le32(0x00000000); 1218 msg[6] = cpu_to_le32(0x00000000); 1219 msg[7] = cpu_to_le32(0x00000780); 1220 msg[8] = cpu_to_le32(0x00000440); 1221 msg[9] = cpu_to_le32(0x00000000); 1222 msg[10] = cpu_to_le32(0x01b37000); 1223 for (i = 11; i < 1024; ++i) 1224 msg[i] = cpu_to_le32(0x0); 1225 1226 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1227 1228 } 1229 1230 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1231 bool direct, struct dma_fence **fence) 1232 { 1233 struct amdgpu_device *adev = ring->adev; 1234 struct amdgpu_bo *bo = NULL; 1235 uint32_t *msg; 1236 int r, i; 1237 1238 if (direct) { 1239 bo = adev->uvd.ib_bo; 1240 } else { 1241 r = amdgpu_uvd_create_msg_bo_helper(adev, 4096, &bo); 1242 if (r) 1243 return r; 1244 } 1245 1246 msg = amdgpu_bo_kptr(bo); 1247 /* stitch together an UVD destroy msg */ 1248 msg[0] = cpu_to_le32(0x00000de4); 1249 msg[1] = cpu_to_le32(0x00000002); 1250 msg[2] = cpu_to_le32(handle); 1251 msg[3] = cpu_to_le32(0x00000000); 1252 for (i = 4; i < 1024; ++i) 1253 msg[i] = cpu_to_le32(0x0); 1254 1255 r = amdgpu_uvd_send_msg(ring, bo, direct, fence); 1256 1257 if (!direct) 1258 amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg); 1259 1260 return r; 1261 } 1262 1263 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1264 { 1265 struct amdgpu_device *adev = 1266 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1267 unsigned int fences = 0, i, j; 1268 1269 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1270 if (adev->uvd.harvest_config & (1 << i)) 1271 continue; 1272 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring); 1273 for (j = 0; j < adev->uvd.num_enc_rings; ++j) 1274 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]); 1275 } 1276 1277 if (fences == 0) { 1278 if (adev->pm.dpm_enabled) { 1279 amdgpu_dpm_enable_uvd(adev, false); 1280 } else { 1281 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1282 /* shutdown the UVD block */ 1283 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1284 AMD_PG_STATE_GATE); 1285 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1286 AMD_CG_STATE_GATE); 1287 } 1288 } else { 1289 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1290 } 1291 } 1292 1293 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 1294 { 1295 struct amdgpu_device *adev = ring->adev; 1296 bool set_clocks; 1297 1298 if (amdgpu_sriov_vf(adev)) 1299 return; 1300 1301 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1302 if (set_clocks) { 1303 if (adev->pm.dpm_enabled) { 1304 amdgpu_dpm_enable_uvd(adev, true); 1305 } else { 1306 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1307 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1308 AMD_CG_STATE_UNGATE); 1309 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1310 AMD_PG_STATE_UNGATE); 1311 } 1312 } 1313 } 1314 1315 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) 1316 { 1317 if (!amdgpu_sriov_vf(ring->adev)) 1318 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1319 } 1320 1321 /** 1322 * amdgpu_uvd_ring_test_ib - test ib execution 1323 * 1324 * @ring: amdgpu_ring pointer 1325 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1326 * 1327 * Test if we can successfully execute an IB 1328 */ 1329 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1330 { 1331 struct dma_fence *fence; 1332 long r; 1333 1334 r = amdgpu_uvd_get_create_msg(ring, 1, &fence); 1335 if (r) 1336 goto error; 1337 1338 r = dma_fence_wait_timeout(fence, false, timeout); 1339 dma_fence_put(fence); 1340 if (r == 0) 1341 r = -ETIMEDOUT; 1342 if (r < 0) 1343 goto error; 1344 1345 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 1346 if (r) 1347 goto error; 1348 1349 r = dma_fence_wait_timeout(fence, false, timeout); 1350 if (r == 0) 1351 r = -ETIMEDOUT; 1352 else if (r > 0) 1353 r = 0; 1354 1355 dma_fence_put(fence); 1356 1357 error: 1358 return r; 1359 } 1360 1361 /** 1362 * amdgpu_uvd_used_handles - returns used UVD handles 1363 * 1364 * @adev: amdgpu_device pointer 1365 * 1366 * Returns the number of UVD handles in use 1367 */ 1368 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) 1369 { 1370 unsigned int i; 1371 uint32_t used_handles = 0; 1372 1373 for (i = 0; i < adev->uvd.max_handles; ++i) { 1374 /* 1375 * Handles can be freed in any order, and not 1376 * necessarily linear. So we need to count 1377 * all non-zero handles. 1378 */ 1379 if (atomic_read(&adev->uvd.handles[i])) 1380 used_handles++; 1381 } 1382 1383 return used_handles; 1384 } 1385