1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef AMDGPU_USERQ_H_ 26 #define AMDGPU_USERQ_H_ 27 #include "amdgpu_eviction_fence.h" 28 29 #define AMDGPU_MAX_USERQ_COUNT 512 30 31 #define to_ev_fence(f) container_of(f, struct amdgpu_eviction_fence, base) 32 #define uq_mgr_to_fpriv(u) container_of(u, struct amdgpu_fpriv, userq_mgr) 33 #define work_to_uq_mgr(w, name) container_of(w, struct amdgpu_userq_mgr, name) 34 35 enum amdgpu_userq_state { 36 AMDGPU_USERQ_STATE_UNMAPPED = 0, 37 AMDGPU_USERQ_STATE_MAPPED, 38 AMDGPU_USERQ_STATE_PREEMPTED, 39 AMDGPU_USERQ_STATE_HUNG, 40 AMDGPU_USERQ_STATE_INVALID_VA, 41 }; 42 43 struct amdgpu_mqd_prop; 44 45 struct amdgpu_userq_obj { 46 void *cpu_ptr; 47 uint64_t gpu_addr; 48 struct amdgpu_bo *obj; 49 }; 50 51 struct amdgpu_userq_va_cursor { 52 u64 gpu_addr; 53 struct list_head list; 54 }; 55 56 struct amdgpu_usermode_queue { 57 int queue_type; 58 enum amdgpu_userq_state state; 59 uint64_t doorbell_handle; 60 uint64_t doorbell_index; 61 uint64_t flags; 62 struct amdgpu_mqd_prop *userq_prop; 63 struct amdgpu_userq_mgr *userq_mgr; 64 struct amdgpu_vm *vm; 65 struct amdgpu_userq_obj mqd; 66 struct amdgpu_userq_obj db_obj; 67 struct amdgpu_userq_obj fw_obj; 68 struct amdgpu_userq_obj wptr_obj; 69 70 /** 71 * @fence_drv_lock: Protecting @fence_drv_xa. 72 */ 73 struct mutex fence_drv_lock; 74 75 /** 76 * @fence_drv_xa: 77 * 78 * References to the external fence drivers returned by wait_ioctl. 79 * Dropped on the next signaled dma_fence or queue destruction. 80 */ 81 struct xarray fence_drv_xa; 82 struct amdgpu_userq_fence_driver *fence_drv; 83 struct dma_fence *last_fence; 84 u32 xcp_id; 85 int priority; 86 struct dentry *debugfs_queue; 87 88 /** 89 * @hang_detect_work: 90 * 91 * Delayed work which runs when userq_fences time out. 92 */ 93 struct delayed_work hang_detect_work; 94 struct kref refcount; 95 96 struct list_head userq_va_list; 97 }; 98 99 struct amdgpu_userq_funcs { 100 int (*mqd_create)(struct amdgpu_usermode_queue *queue, 101 struct drm_amdgpu_userq_in *args); 102 int (*mqd_update)(struct amdgpu_usermode_queue *queue, 103 struct drm_amdgpu_userq_in *args); 104 void (*mqd_destroy)(struct amdgpu_usermode_queue *uq); 105 int (*unmap)(struct amdgpu_usermode_queue *queue); 106 int (*map)(struct amdgpu_usermode_queue *queue); 107 int (*preempt)(struct amdgpu_usermode_queue *queue); 108 int (*restore)(struct amdgpu_usermode_queue *queue); 109 int (*detect_and_reset)(struct amdgpu_device *adev, 110 int queue_type); 111 }; 112 113 /* Usermode queues for gfx */ 114 struct amdgpu_userq_mgr { 115 /** 116 * @userq_xa: Per-process user queue map (queue ID → queue) 117 * Key: queue_id (unique ID within the process's userq manager) 118 * Value: struct amdgpu_usermode_queue 119 */ 120 struct xarray userq_xa; 121 struct mutex userq_mutex; 122 struct amdgpu_device *adev; 123 struct delayed_work resume_work; 124 struct drm_file *file; 125 126 /** 127 * @reset_work: 128 * 129 * Reset work which is used when eviction fails. 130 */ 131 struct work_struct reset_work; 132 atomic_t userq_count[AMDGPU_RING_TYPE_MAX]; 133 }; 134 135 struct amdgpu_db_info { 136 uint64_t doorbell_handle; 137 uint32_t queue_type; 138 uint32_t doorbell_offset; 139 struct amdgpu_userq_obj *db_obj; 140 }; 141 142 struct amdgpu_usermode_queue *amdgpu_userq_get(struct amdgpu_userq_mgr *uq_mgr, u32 qid); 143 void amdgpu_userq_put(struct amdgpu_usermode_queue *queue); 144 145 int amdgpu_userq_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 146 147 int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *file_priv, 148 struct amdgpu_device *adev); 149 150 void amdgpu_userq_mgr_cancel_reset_work(struct amdgpu_device *adev); 151 void amdgpu_userq_mgr_cancel_resume(struct amdgpu_userq_mgr *userq_mgr); 152 void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr); 153 154 int amdgpu_userq_create_object(struct amdgpu_userq_mgr *uq_mgr, 155 struct amdgpu_userq_obj *userq_obj, 156 int size); 157 158 void amdgpu_userq_destroy_object(struct amdgpu_userq_mgr *uq_mgr, 159 struct amdgpu_userq_obj *userq_obj); 160 161 void amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr); 162 163 void amdgpu_userq_ensure_ev_fence(struct amdgpu_userq_mgr *userq_mgr, 164 struct amdgpu_eviction_fence_mgr *evf_mgr); 165 166 uint64_t amdgpu_userq_get_doorbell_index(struct amdgpu_userq_mgr *uq_mgr, 167 struct amdgpu_db_info *db_info, 168 struct drm_file *filp); 169 170 u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev); 171 bool amdgpu_userq_enabled(struct drm_device *dev); 172 173 int amdgpu_userq_suspend(struct amdgpu_device *adev); 174 int amdgpu_userq_resume(struct amdgpu_device *adev); 175 176 int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev, 177 u32 idx); 178 int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev, 179 u32 idx); 180 void amdgpu_userq_reset_work(struct work_struct *work); 181 void amdgpu_userq_pre_reset(struct amdgpu_device *adev); 182 int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost); 183 void amdgpu_userq_start_hang_detect_work(struct amdgpu_usermode_queue *queue); 184 void amdgpu_userq_process_fence_irq(struct amdgpu_device *adev, u32 doorbell); 185 186 int amdgpu_userq_input_va_validate(struct amdgpu_device *adev, 187 struct amdgpu_usermode_queue *queue, 188 u64 addr, u64 expected_size); 189 void amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev, 190 struct amdgpu_bo_va_mapping *mapping, 191 uint64_t saddr); 192 #endif 193