1 /* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef __AMDGPU_UMC_H__ 22 #define __AMDGPU_UMC_H__ 23 #include "amdgpu_ras.h" 24 #include "amdgpu_mca.h" 25 /* 26 * (addr / 256) * 4096, the higher 26 bits in ErrorAddr 27 * is the index of 4KB block 28 */ 29 #define ADDR_OF_4KB_BLOCK(addr) (((addr) & ~0xffULL) << 4) 30 /* 31 * (addr / 256) * 8192, the higher 26 bits in ErrorAddr 32 * is the index of 8KB block 33 */ 34 #define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5) 35 /* 36 * (addr / 256) * 32768, the higher 26 bits in ErrorAddr 37 * is the index of 8KB block 38 */ 39 #define ADDR_OF_32KB_BLOCK(addr) (((addr) & ~0xffULL) << 7) 40 /* channel index is the index of 256B block */ 41 #define ADDR_OF_256B_BLOCK(channel_index) ((channel_index) << 8) 42 /* offset in 256B block */ 43 #define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL) 44 45 #define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++) 46 #define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++) 47 #define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst)) 48 49 #define LOOP_UMC_NODE_INST(node_inst) \ 50 for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num) 51 52 #define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \ 53 LOOP_UMC_NODE_INST((node_inst)) LOOP_UMC_INST_AND_CH((umc_inst), (ch_inst)) 54 55 /* Page retirement tag */ 56 #define UMC_ECC_NEW_DETECTED_TAG 0x1 57 58 typedef int (*umc_func)(struct amdgpu_device *adev, uint32_t node_inst, 59 uint32_t umc_inst, uint32_t ch_inst, void *data); 60 61 struct amdgpu_umc_ras { 62 struct amdgpu_ras_block_object ras_block; 63 void (*err_cnt_init)(struct amdgpu_device *adev); 64 bool (*query_ras_poison_mode)(struct amdgpu_device *adev); 65 void (*ecc_info_query_ras_error_count)(struct amdgpu_device *adev, 66 void *ras_error_status); 67 void (*ecc_info_query_ras_error_address)(struct amdgpu_device *adev, 68 void *ras_error_status); 69 bool (*check_ecc_err_status)(struct amdgpu_device *adev, 70 enum amdgpu_mca_error_type type, void *ras_error_status); 71 int (*update_ecc_status)(struct amdgpu_device *adev, 72 uint64_t status, uint64_t ipid, uint64_t addr); 73 }; 74 75 struct amdgpu_umc_funcs { 76 void (*init_registers)(struct amdgpu_device *adev); 77 }; 78 79 struct amdgpu_umc { 80 /* max error count in one ras query call */ 81 uint32_t max_ras_err_cnt_per_query; 82 /* number of umc channel instance with memory map register access */ 83 uint32_t channel_inst_num; 84 /* number of umc instance with memory map register access */ 85 uint32_t umc_inst_num; 86 87 /* Total number of umc node instance including harvest one */ 88 uint32_t node_inst_num; 89 90 /* UMC regiser per channel offset */ 91 uint32_t channel_offs; 92 /* how many pages are retired in one UE */ 93 uint32_t retire_unit; 94 /* channel index table of interleaved memory */ 95 const uint32_t *channel_idx_tbl; 96 struct ras_common_if *ras_if; 97 98 const struct amdgpu_umc_funcs *funcs; 99 struct amdgpu_umc_ras *ras; 100 101 /* active mask for umc node instance */ 102 unsigned long active_mask; 103 }; 104 105 int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev); 106 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); 107 int amdgpu_umc_poison_handler(struct amdgpu_device *adev, 108 enum amdgpu_ras_block block, uint32_t reset); 109 int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev, 110 enum amdgpu_ras_block block, uint16_t pasid, 111 pasid_notify pasid_fn, void *data, uint32_t reset); 112 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, 113 struct amdgpu_irq_src *source, 114 struct amdgpu_iv_entry *entry); 115 int amdgpu_umc_fill_error_record(struct ras_err_data *err_data, 116 uint64_t err_addr, 117 uint64_t retired_page, 118 uint32_t channel_index, 119 uint32_t umc_inst); 120 121 int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, 122 void *ras_error_status, 123 struct amdgpu_iv_entry *entry); 124 int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev, 125 uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst); 126 127 int amdgpu_umc_loop_channels(struct amdgpu_device *adev, 128 umc_func func, void *data); 129 130 int amdgpu_umc_bad_page_polling_timeout(struct amdgpu_device *adev, 131 uint32_t reset, uint32_t timeout_ms); 132 133 int amdgpu_umc_update_ecc_status(struct amdgpu_device *adev, 134 uint64_t status, uint64_t ipid, uint64_t addr); 135 int amdgpu_umc_build_pages_hash(struct amdgpu_device *adev, 136 uint64_t *pfns, int len, uint64_t *val); 137 int amdgpu_umc_logs_ecc_err(struct amdgpu_device *adev, 138 struct radix_tree_root *ecc_tree, struct ras_ecc_err *ecc_err); 139 140 void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev, 141 void *ras_error_status); 142 #endif 143