1 /* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef __AMDGPU_UMC_H__ 22 #define __AMDGPU_UMC_H__ 23 #include "amdgpu_ras.h" 24 #include "amdgpu_mca.h" 25 /* 26 * (addr / 256) * 4096, the higher 26 bits in ErrorAddr 27 * is the index of 4KB block 28 */ 29 #define ADDR_OF_4KB_BLOCK(addr) (((addr) & ~0xffULL) << 4) 30 /* 31 * (addr / 256) * 8192, the higher 26 bits in ErrorAddr 32 * is the index of 8KB block 33 */ 34 #define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5) 35 /* 36 * (addr / 256) * 32768, the higher 26 bits in ErrorAddr 37 * is the index of 8KB block 38 */ 39 #define ADDR_OF_32KB_BLOCK(addr) (((addr) & ~0xffULL) << 7) 40 /* channel index is the index of 256B block */ 41 #define ADDR_OF_256B_BLOCK(channel_index) ((channel_index) << 8) 42 /* offset in 256B block */ 43 #define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL) 44 45 #define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++) 46 #define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++) 47 #define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst)) 48 49 #define LOOP_UMC_NODE_INST(node_inst) \ 50 for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num) 51 52 #define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \ 53 LOOP_UMC_NODE_INST((node_inst)) LOOP_UMC_INST_AND_CH((umc_inst), (ch_inst)) 54 55 /* Page retirement tag */ 56 #define UMC_ECC_NEW_DETECTED_TAG 0x1 57 /* 58 * a flag to indicate v2 of channel index stored in eeprom 59 * 60 * v1 (legacy way): store channel index within a umc instance in eeprom 61 * range in UMC v12: 0 ~ 7 62 * v2: store global channel index in eeprom 63 * range in UMC v12: 0 ~ 127 64 * 65 * NOTE: it's better to store it in eeprom_table_record.mem_channel, 66 * but there is only 8 bits in mem_channel, and the channel number may 67 * increase in the future, we decide to save it in 68 * eeprom_table_record.retired_page. retired_page is useless in v2, 69 * we depend on eeprom_table_record.address instead of retired_page in v2. 70 * Only 48 bits are saved on eeprom, use bit 47 here. 71 */ 72 #define UMC_CHANNEL_IDX_V2 BIT_ULL(47) 73 74 /* 75 * save nps value to eeprom_table_record.retired_page[47:40], 76 * the channel index flag above will be retired. 77 */ 78 #define UMC_NPS_SHIFT 40 79 #define UMC_NPS_MASK 0xffULL 80 81 /* three column bits and one row bit in MCA address flip 82 * in bad page retirement 83 */ 84 #define RETIRE_FLIP_BITS_NUM 4 85 86 struct amdgpu_umc_flip_bits { 87 uint32_t flip_bits_in_pa[RETIRE_FLIP_BITS_NUM]; 88 uint32_t flip_row_bit; 89 uint32_t r13_in_pa; 90 uint32_t bit_num; 91 }; 92 93 typedef int (*umc_func)(struct amdgpu_device *adev, uint32_t node_inst, 94 uint32_t umc_inst, uint32_t ch_inst, void *data); 95 96 struct amdgpu_umc_ras { 97 struct amdgpu_ras_block_object ras_block; 98 void (*err_cnt_init)(struct amdgpu_device *adev); 99 bool (*query_ras_poison_mode)(struct amdgpu_device *adev); 100 void (*ecc_info_query_ras_error_count)(struct amdgpu_device *adev, 101 void *ras_error_status); 102 void (*ecc_info_query_ras_error_address)(struct amdgpu_device *adev, 103 void *ras_error_status); 104 bool (*check_ecc_err_status)(struct amdgpu_device *adev, 105 enum amdgpu_mca_error_type type, void *ras_error_status); 106 void (*get_retire_flip_bits)(struct amdgpu_device *adev); 107 }; 108 109 struct amdgpu_umc_funcs { 110 void (*init_registers)(struct amdgpu_device *adev); 111 }; 112 113 struct amdgpu_umc { 114 /* max error count in one ras query call */ 115 uint32_t max_ras_err_cnt_per_query; 116 /* number of umc channel instance with memory map register access */ 117 uint32_t channel_inst_num; 118 /* number of umc instance with memory map register access */ 119 uint32_t umc_inst_num; 120 121 /* Total number of umc node instance including harvest one */ 122 uint32_t node_inst_num; 123 124 /* UMC regiser per channel offset */ 125 uint32_t channel_offs; 126 /* how many pages are retired in one UE */ 127 uint32_t retire_unit; 128 /* channel index table of interleaved memory */ 129 const uint32_t *channel_idx_tbl; 130 struct ras_common_if *ras_if; 131 132 const struct amdgpu_umc_funcs *funcs; 133 struct amdgpu_umc_ras *ras; 134 135 /* active mask for umc node instance */ 136 unsigned long active_mask; 137 138 struct amdgpu_umc_flip_bits flip_bits; 139 140 unsigned long err_addr_cnt; 141 }; 142 143 int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev); 144 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); 145 int amdgpu_umc_poison_handler(struct amdgpu_device *adev, 146 enum amdgpu_ras_block block, uint32_t reset); 147 int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev, 148 enum amdgpu_ras_block block, uint16_t pasid, 149 pasid_notify pasid_fn, void *data, uint32_t reset); 150 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, 151 struct amdgpu_irq_src *source, 152 struct amdgpu_iv_entry *entry); 153 int amdgpu_umc_uniras_process_ecc_irq(struct amdgpu_device *adev, 154 struct amdgpu_irq_src *source, 155 struct amdgpu_iv_entry *entry); 156 int amdgpu_umc_fill_error_record(struct ras_err_data *err_data, 157 uint64_t err_addr, 158 uint64_t retired_page, 159 uint32_t channel_index, 160 uint32_t umc_inst); 161 162 int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, 163 void *ras_error_status, 164 struct amdgpu_iv_entry *entry); 165 int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev, 166 uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst); 167 168 int amdgpu_umc_loop_channels(struct amdgpu_device *adev, 169 umc_func func, void *data); 170 171 void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev, 172 void *ras_error_status); 173 #endif 174