1 /* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef __AMDGPU_UMC_H__ 22 #define __AMDGPU_UMC_H__ 23 #include "amdgpu_ras.h" 24 /* 25 * (addr / 256) * 4096, the higher 26 bits in ErrorAddr 26 * is the index of 4KB block 27 */ 28 #define ADDR_OF_4KB_BLOCK(addr) (((addr) & ~0xffULL) << 4) 29 /* 30 * (addr / 256) * 8192, the higher 26 bits in ErrorAddr 31 * is the index of 8KB block 32 */ 33 #define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5) 34 /* 35 * (addr / 256) * 32768, the higher 26 bits in ErrorAddr 36 * is the index of 8KB block 37 */ 38 #define ADDR_OF_32KB_BLOCK(addr) (((addr) & ~0xffULL) << 7) 39 /* channel index is the index of 256B block */ 40 #define ADDR_OF_256B_BLOCK(channel_index) ((channel_index) << 8) 41 /* offset in 256B block */ 42 #define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL) 43 44 #define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++) 45 #define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++) 46 #define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst)) 47 48 #define LOOP_UMC_NODE_INST(node_inst) \ 49 for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num) 50 51 #define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \ 52 LOOP_UMC_NODE_INST((node_inst)) LOOP_UMC_INST_AND_CH((umc_inst), (ch_inst)) 53 54 /* Page retirement tag */ 55 #define UMC_ECC_NEW_DETECTED_TAG 0x1 56 /* 57 * a flag to indicate v2 of channel index stored in eeprom 58 * 59 * v1 (legacy way): store channel index within a umc instance in eeprom 60 * range in UMC v12: 0 ~ 7 61 * v2: store global channel index in eeprom 62 * range in UMC v12: 0 ~ 127 63 * 64 * NOTE: it's better to store it in eeprom_table_record.mem_channel, 65 * but there is only 8 bits in mem_channel, and the channel number may 66 * increase in the future, we decide to save it in 67 * eeprom_table_record.retired_page. retired_page is useless in v2, 68 * we depend on eeprom_table_record.address instead of retired_page in v2. 69 * Only 48 bits are saved on eeprom, use bit 47 here. 70 */ 71 #define UMC_CHANNEL_IDX_V2 BIT_ULL(47) 72 73 /* 74 * save nps value to eeprom_table_record.retired_page[47:40], 75 * the channel index flag above will be retired. 76 */ 77 #define UMC_NPS_SHIFT 40 78 #define UMC_NPS_MASK 0xffULL 79 80 typedef int (*umc_func)(struct amdgpu_device *adev, uint32_t node_inst, 81 uint32_t umc_inst, uint32_t ch_inst, void *data); 82 83 struct amdgpu_umc_ras { 84 struct amdgpu_ras_block_object ras_block; 85 void (*err_cnt_init)(struct amdgpu_device *adev); 86 bool (*query_ras_poison_mode)(struct amdgpu_device *adev); 87 void (*ecc_info_query_ras_error_count)(struct amdgpu_device *adev, 88 void *ras_error_status); 89 void (*ecc_info_query_ras_error_address)(struct amdgpu_device *adev, 90 void *ras_error_status); 91 }; 92 93 struct amdgpu_umc_funcs { 94 void (*init_registers)(struct amdgpu_device *adev); 95 }; 96 97 struct amdgpu_umc { 98 /* max error count in one ras query call */ 99 uint32_t max_ras_err_cnt_per_query; 100 /* number of umc channel instance with memory map register access */ 101 uint32_t channel_inst_num; 102 /* number of umc instance with memory map register access */ 103 uint32_t umc_inst_num; 104 105 /* Total number of umc node instance including harvest one */ 106 uint32_t node_inst_num; 107 108 /* UMC regiser per channel offset */ 109 uint32_t channel_offs; 110 /* how many pages are retired in one UE */ 111 uint32_t retire_unit; 112 /* channel index table of interleaved memory */ 113 const uint32_t *channel_idx_tbl; 114 struct ras_common_if *ras_if; 115 116 const struct amdgpu_umc_funcs *funcs; 117 struct amdgpu_umc_ras *ras; 118 119 /* active mask for umc node instance */ 120 unsigned long active_mask; 121 122 unsigned long err_addr_cnt; 123 }; 124 125 int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev); 126 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); 127 int amdgpu_umc_poison_handler(struct amdgpu_device *adev, 128 enum amdgpu_ras_block block, uint32_t reset); 129 int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev, 130 enum amdgpu_ras_block block, uint16_t pasid, 131 pasid_notify pasid_fn, void *data, uint32_t reset); 132 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, 133 struct amdgpu_irq_src *source, 134 struct amdgpu_iv_entry *entry); 135 int amdgpu_umc_uniras_process_ecc_irq(struct amdgpu_device *adev, 136 struct amdgpu_irq_src *source, 137 struct amdgpu_iv_entry *entry); 138 int amdgpu_umc_fill_error_record(struct ras_err_data *err_data, 139 uint64_t err_addr, 140 uint64_t retired_page, 141 uint32_t channel_index, 142 uint32_t umc_inst); 143 144 int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, 145 void *ras_error_status, 146 struct amdgpu_iv_entry *entry); 147 int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev, 148 uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst); 149 150 int amdgpu_umc_loop_channels(struct amdgpu_device *adev, 151 umc_func func, void *data); 152 153 void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev, 154 void *ras_error_status); 155 #endif 156