1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/sort.h> 25 #include "amdgpu.h" 26 #include "umc_v6_7.h" 27 #include "amdgpu_ras_mgr.h" 28 #define MAX_UMC_POISON_POLLING_TIME_SYNC 20 //ms 29 30 #define MAX_UMC_HASH_STRING_SIZE 256 31 32 static int amdgpu_umc_convert_error_address(struct amdgpu_device *adev, 33 struct ras_err_data *err_data, uint64_t err_addr, 34 uint32_t ch_inst, uint32_t umc_inst) 35 { 36 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 37 case IP_VERSION(6, 7, 0): 38 umc_v6_7_convert_error_address(adev, 39 err_data, err_addr, ch_inst, umc_inst); 40 break; 41 default: 42 dev_warn(adev->dev, 43 "UMC address to Physical address translation is not supported\n"); 44 return AMDGPU_RAS_FAIL; 45 } 46 47 return AMDGPU_RAS_SUCCESS; 48 } 49 50 int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev, 51 uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst) 52 { 53 struct ras_err_data err_data; 54 int ret; 55 56 ret = amdgpu_ras_error_data_init(&err_data); 57 if (ret) 58 return ret; 59 60 err_data.err_addr = 61 kzalloc_objs(struct eeprom_table_record, 62 adev->umc.max_ras_err_cnt_per_query); 63 if (!err_data.err_addr) { 64 dev_warn(adev->dev, 65 "Failed to alloc memory for umc error record in MCA notifier!\n"); 66 ret = AMDGPU_RAS_FAIL; 67 goto out_fini_err_data; 68 } 69 70 err_data.err_addr_len = adev->umc.max_ras_err_cnt_per_query; 71 72 /* 73 * Translate UMC channel address to Physical address 74 */ 75 ret = amdgpu_umc_convert_error_address(adev, &err_data, err_addr, 76 ch_inst, umc_inst); 77 if (ret) 78 goto out_free_err_addr; 79 80 if (amdgpu_bad_page_threshold != 0) { 81 amdgpu_ras_add_bad_pages(adev, err_data.err_addr, 82 err_data.err_addr_cnt, false); 83 amdgpu_ras_save_bad_pages(adev, NULL); 84 } 85 86 out_free_err_addr: 87 kfree(err_data.err_addr); 88 89 out_fini_err_data: 90 amdgpu_ras_error_data_fini(&err_data); 91 92 return ret; 93 } 94 95 void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev, 96 void *ras_error_status) 97 { 98 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 99 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 100 unsigned int error_query_mode; 101 int ret = 0; 102 unsigned long err_count; 103 104 amdgpu_ras_get_error_query_mode(adev, &error_query_mode); 105 106 err_data->err_addr = 107 kzalloc_objs(struct eeprom_table_record, 108 adev->umc.max_ras_err_cnt_per_query); 109 110 /* still call query_ras_error_address to clear error status 111 * even NOMEM error is encountered 112 */ 113 if (!err_data->err_addr) 114 dev_warn(adev->dev, 115 "Failed to alloc memory for umc error address record!\n"); 116 else 117 err_data->err_addr_len = adev->umc.max_ras_err_cnt_per_query; 118 119 mutex_lock(&con->page_retirement_lock); 120 ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(con->umc_ecc)); 121 if (ret == -EOPNOTSUPP && 122 error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) { 123 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && 124 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) 125 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, 126 ras_error_status); 127 128 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && 129 adev->umc.ras->ras_block.hw_ops->query_ras_error_address && 130 adev->umc.max_ras_err_cnt_per_query) { 131 err_data->err_addr = 132 kzalloc_objs(struct eeprom_table_record, 133 adev->umc.max_ras_err_cnt_per_query); 134 135 /* still call query_ras_error_address to clear error status 136 * even NOMEM error is encountered 137 */ 138 if (!err_data->err_addr) 139 dev_warn(adev->dev, 140 "Failed to alloc memory for umc error address record!\n"); 141 else 142 err_data->err_addr_len = 143 adev->umc.max_ras_err_cnt_per_query; 144 145 /* umc query_ras_error_address is also responsible for clearing 146 * error status 147 */ 148 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, 149 ras_error_status); 150 } 151 } else if (error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY || 152 (!ret && error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY)) { 153 if (adev->umc.ras && 154 adev->umc.ras->ecc_info_query_ras_error_count) 155 adev->umc.ras->ecc_info_query_ras_error_count(adev, 156 ras_error_status); 157 158 if (adev->umc.ras && 159 adev->umc.ras->ecc_info_query_ras_error_address && 160 adev->umc.max_ras_err_cnt_per_query) { 161 err_data->err_addr = 162 kcalloc(adev->umc.max_ras_err_cnt_per_query, 163 sizeof(struct eeprom_table_record), GFP_KERNEL); 164 165 /* still call query_ras_error_address to clear error status 166 * even NOMEM error is encountered 167 */ 168 if (!err_data->err_addr) 169 dev_warn(adev->dev, 170 "Failed to alloc memory for umc error address record!\n"); 171 else 172 err_data->err_addr_len = 173 adev->umc.max_ras_err_cnt_per_query; 174 175 /* umc query_ras_error_address is also responsible for clearing 176 * error status 177 */ 178 adev->umc.ras->ecc_info_query_ras_error_address(adev, 179 ras_error_status); 180 } 181 } 182 183 /* only uncorrectable error needs gpu reset */ 184 if (err_data->ue_count || err_data->de_count) { 185 err_count = err_data->ue_count + err_data->de_count; 186 if ((amdgpu_bad_page_threshold != 0) && 187 err_data->err_addr_cnt) { 188 amdgpu_ras_add_bad_pages(adev, err_data->err_addr, 189 err_data->err_addr_cnt, amdgpu_ras_smu_eeprom_supported(adev)); 190 amdgpu_ras_save_bad_pages(adev, &err_count); 191 192 amdgpu_dpm_send_hbm_bad_pages_num(adev, 193 con->eeprom_control.ras_num_bad_pages); 194 195 if (con->update_channel_flag == true) { 196 amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap); 197 con->update_channel_flag = false; 198 } 199 } 200 } 201 202 kfree(err_data->err_addr); 203 err_data->err_addr = NULL; 204 205 mutex_unlock(&con->page_retirement_lock); 206 } 207 208 static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev, 209 void *ras_error_status, 210 struct amdgpu_iv_entry *entry, 211 uint32_t reset) 212 { 213 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 214 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 215 216 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 217 amdgpu_umc_handle_bad_pages(adev, ras_error_status); 218 219 if ((err_data->ue_count || err_data->de_count) && 220 (reset || amdgpu_ras_is_rma(adev))) { 221 con->gpu_reset_flags |= reset; 222 amdgpu_ras_reset_gpu(adev); 223 } 224 225 return AMDGPU_RAS_SUCCESS; 226 } 227 228 int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev, 229 enum amdgpu_ras_block block, uint16_t pasid, 230 pasid_notify pasid_fn, void *data, uint32_t reset) 231 { 232 int ret = AMDGPU_RAS_SUCCESS; 233 234 if (adev->gmc.xgmi.connected_to_cpu || 235 adev->gmc.is_app_apu) { 236 if (reset) { 237 /* MCA poison handler is only responsible for GPU reset, 238 * let MCA notifier do page retirement. 239 */ 240 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 241 amdgpu_ras_reset_gpu(adev); 242 } 243 return ret; 244 } 245 246 if (!amdgpu_sriov_vf(adev)) { 247 if (amdgpu_ip_version(adev, UMC_HWIP, 0) < IP_VERSION(12, 0, 0)) { 248 struct ras_err_data err_data; 249 struct ras_common_if head = { 250 .block = AMDGPU_RAS_BLOCK__UMC, 251 }; 252 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head); 253 254 ret = amdgpu_ras_error_data_init(&err_data); 255 if (ret) 256 return ret; 257 258 ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset); 259 260 if (ret == AMDGPU_RAS_SUCCESS && obj) { 261 obj->err_data.ue_count += err_data.ue_count; 262 obj->err_data.ce_count += err_data.ce_count; 263 obj->err_data.de_count += err_data.de_count; 264 } 265 266 amdgpu_ras_error_data_fini(&err_data); 267 } else { 268 struct ras_ih_info ih_info = {0}; 269 270 ih_info.block = block; 271 ih_info.pasid = pasid; 272 ih_info.reset = reset; 273 ih_info.pasid_fn = pasid_fn; 274 ih_info.data = data; 275 amdgpu_ras_mgr_handle_consumer_interrupt(adev, &ih_info); 276 } 277 } else { 278 if (adev->virt.ops && adev->virt.ops->ras_poison_handler) 279 adev->virt.ops->ras_poison_handler(adev, block); 280 else 281 dev_warn(adev->dev, 282 "No ras_poison_handler interface in SRIOV!\n"); 283 } 284 285 return ret; 286 } 287 288 int amdgpu_umc_poison_handler(struct amdgpu_device *adev, 289 enum amdgpu_ras_block block, uint32_t reset) 290 { 291 return amdgpu_umc_pasid_poison_handler(adev, 292 block, 0, NULL, NULL, reset); 293 } 294 295 int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, 296 void *ras_error_status, 297 struct amdgpu_iv_entry *entry) 298 { 299 return amdgpu_umc_do_page_retirement(adev, ras_error_status, entry, 300 AMDGPU_RAS_GPU_RESET_MODE1_RESET); 301 } 302 303 int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev) 304 { 305 int err; 306 struct amdgpu_umc_ras *ras; 307 308 if (!adev->umc.ras) 309 return 0; 310 311 ras = adev->umc.ras; 312 313 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 314 if (err) { 315 dev_err(adev->dev, "Failed to register umc ras block!\n"); 316 return err; 317 } 318 319 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); 320 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; 321 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 322 adev->umc.ras_if = &ras->ras_block.ras_comm; 323 324 if (!ras->ras_block.ras_late_init) 325 ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; 326 327 if (!ras->ras_block.ras_cb) 328 ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb; 329 330 return 0; 331 } 332 333 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 334 { 335 int r; 336 337 r = amdgpu_ras_block_late_init(adev, ras_block); 338 if (r) 339 return r; 340 341 if (amdgpu_sriov_vf(adev)) 342 return r; 343 344 if (amdgpu_ras_is_supported(adev, ras_block->block)) { 345 r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); 346 if (r) 347 goto late_fini; 348 } 349 350 /* ras init of specific umc version */ 351 if (adev->umc.ras && 352 adev->umc.ras->err_cnt_init) 353 adev->umc.ras->err_cnt_init(adev); 354 355 return 0; 356 357 late_fini: 358 amdgpu_ras_block_late_fini(adev, ras_block); 359 return r; 360 } 361 362 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, 363 struct amdgpu_irq_src *source, 364 struct amdgpu_iv_entry *entry) 365 { 366 struct ras_common_if *ras_if = adev->umc.ras_if; 367 struct ras_dispatch_if ih_data = { 368 .entry = entry, 369 }; 370 371 if (!ras_if) 372 return 0; 373 374 ih_data.head = *ras_if; 375 376 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 377 return 0; 378 } 379 380 int amdgpu_umc_uniras_process_ecc_irq(struct amdgpu_device *adev, 381 struct amdgpu_irq_src *source, 382 struct amdgpu_iv_entry *entry) 383 { 384 struct ras_ih_info ih_info = {0}; 385 386 ih_info.block = RAS_BLOCK_ID__UMC; 387 amdgpu_ras_mgr_dispatch_interrupt(adev, &ih_info); 388 return 0; 389 } 390 391 int amdgpu_umc_fill_error_record(struct ras_err_data *err_data, 392 uint64_t err_addr, 393 uint64_t retired_page, 394 uint32_t channel_index, 395 uint32_t umc_inst) 396 { 397 struct eeprom_table_record *err_rec; 398 399 if (!err_data || 400 !err_data->err_addr || 401 (err_data->err_addr_cnt >= err_data->err_addr_len)) 402 return -EINVAL; 403 404 err_rec = &err_data->err_addr[err_data->err_addr_cnt]; 405 406 err_rec->address = err_addr; 407 /* page frame address is saved */ 408 err_rec->retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT; 409 err_rec->ts = (uint64_t)ktime_get_real_seconds(); 410 err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE; 411 err_rec->cu = 0; 412 err_rec->mem_channel = channel_index; 413 err_rec->mcumc_id = umc_inst; 414 415 err_data->err_addr_cnt++; 416 417 return 0; 418 } 419 420 static int amdgpu_umc_loop_all_aid(struct amdgpu_device *adev, umc_func func, 421 void *data) 422 { 423 uint32_t umc_node_inst; 424 uint32_t node_inst; 425 uint32_t umc_inst; 426 uint32_t ch_inst; 427 int ret; 428 429 /* 430 * This loop is done based on the following - 431 * umc.active mask = mask of active umc instances across all nodes 432 * umc.umc_inst_num = maximum number of umc instancess per node 433 * umc.node_inst_num = maximum number of node instances 434 * Channel instances are not assumed to be harvested. 435 */ 436 dev_dbg(adev->dev, "active umcs :%lx umc_inst per node: %d", 437 adev->umc.active_mask, adev->umc.umc_inst_num); 438 for_each_set_bit(umc_node_inst, &(adev->umc.active_mask), 439 adev->umc.node_inst_num * adev->umc.umc_inst_num) { 440 node_inst = umc_node_inst / adev->umc.umc_inst_num; 441 umc_inst = umc_node_inst % adev->umc.umc_inst_num; 442 LOOP_UMC_CH_INST(ch_inst) { 443 dev_dbg(adev->dev, 444 "node_inst :%d umc_inst: %d ch_inst: %d", 445 node_inst, umc_inst, ch_inst); 446 ret = func(adev, node_inst, umc_inst, ch_inst, data); 447 if (ret) { 448 dev_err(adev->dev, 449 "Node %d umc %d ch %d func returns %d\n", 450 node_inst, umc_inst, ch_inst, ret); 451 return ret; 452 } 453 } 454 } 455 456 return 0; 457 } 458 459 int amdgpu_umc_loop_channels(struct amdgpu_device *adev, 460 umc_func func, void *data) 461 { 462 uint32_t node_inst = 0; 463 uint32_t umc_inst = 0; 464 uint32_t ch_inst = 0; 465 int ret = 0; 466 467 if (adev->aid_mask) 468 return amdgpu_umc_loop_all_aid(adev, func, data); 469 470 if (adev->umc.node_inst_num) { 471 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) { 472 ret = func(adev, node_inst, umc_inst, ch_inst, data); 473 if (ret) { 474 dev_err(adev->dev, "Node %d umc %d ch %d func returns %d\n", 475 node_inst, umc_inst, ch_inst, ret); 476 return ret; 477 } 478 } 479 } else { 480 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { 481 ret = func(adev, 0, umc_inst, ch_inst, data); 482 if (ret) { 483 dev_err(adev->dev, "Umc %d ch %d func returns %d\n", 484 umc_inst, ch_inst, ret); 485 return ret; 486 } 487 } 488 } 489 490 return 0; 491 } 492