1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/sort.h> 25 #include "amdgpu.h" 26 #include "umc_v6_7.h" 27 #define MAX_UMC_POISON_POLLING_TIME_SYNC 20 //ms 28 29 #define MAX_UMC_HASH_STRING_SIZE 256 30 31 static int amdgpu_umc_convert_error_address(struct amdgpu_device *adev, 32 struct ras_err_data *err_data, uint64_t err_addr, 33 uint32_t ch_inst, uint32_t umc_inst) 34 { 35 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 36 case IP_VERSION(6, 7, 0): 37 umc_v6_7_convert_error_address(adev, 38 err_data, err_addr, ch_inst, umc_inst); 39 break; 40 default: 41 dev_warn(adev->dev, 42 "UMC address to Physical address translation is not supported\n"); 43 return AMDGPU_RAS_FAIL; 44 } 45 46 return AMDGPU_RAS_SUCCESS; 47 } 48 49 int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev, 50 uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst) 51 { 52 struct ras_err_data err_data; 53 int ret; 54 55 ret = amdgpu_ras_error_data_init(&err_data); 56 if (ret) 57 return ret; 58 59 err_data.err_addr = 60 kcalloc(adev->umc.max_ras_err_cnt_per_query, 61 sizeof(struct eeprom_table_record), GFP_KERNEL); 62 if (!err_data.err_addr) { 63 dev_warn(adev->dev, 64 "Failed to alloc memory for umc error record in MCA notifier!\n"); 65 ret = AMDGPU_RAS_FAIL; 66 goto out_fini_err_data; 67 } 68 69 err_data.err_addr_len = adev->umc.max_ras_err_cnt_per_query; 70 71 /* 72 * Translate UMC channel address to Physical address 73 */ 74 ret = amdgpu_umc_convert_error_address(adev, &err_data, err_addr, 75 ch_inst, umc_inst); 76 if (ret) 77 goto out_free_err_addr; 78 79 if (amdgpu_bad_page_threshold != 0) { 80 amdgpu_ras_add_bad_pages(adev, err_data.err_addr, 81 err_data.err_addr_cnt); 82 amdgpu_ras_save_bad_pages(adev, NULL); 83 } 84 85 out_free_err_addr: 86 kfree(err_data.err_addr); 87 88 out_fini_err_data: 89 amdgpu_ras_error_data_fini(&err_data); 90 91 return ret; 92 } 93 94 void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev, 95 void *ras_error_status) 96 { 97 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 98 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 99 unsigned int error_query_mode; 100 int ret = 0; 101 unsigned long err_count; 102 103 amdgpu_ras_get_error_query_mode(adev, &error_query_mode); 104 105 mutex_lock(&con->page_retirement_lock); 106 ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(con->umc_ecc)); 107 if (ret == -EOPNOTSUPP && 108 error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) { 109 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && 110 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) 111 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status); 112 113 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && 114 adev->umc.ras->ras_block.hw_ops->query_ras_error_address && 115 adev->umc.max_ras_err_cnt_per_query) { 116 err_data->err_addr = 117 kcalloc(adev->umc.max_ras_err_cnt_per_query, 118 sizeof(struct eeprom_table_record), GFP_KERNEL); 119 120 /* still call query_ras_error_address to clear error status 121 * even NOMEM error is encountered 122 */ 123 if(!err_data->err_addr) 124 dev_warn(adev->dev, "Failed to alloc memory for " 125 "umc error address record!\n"); 126 else 127 err_data->err_addr_len = adev->umc.max_ras_err_cnt_per_query; 128 129 /* umc query_ras_error_address is also responsible for clearing 130 * error status 131 */ 132 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, ras_error_status); 133 } 134 } else if (error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY || 135 (!ret && error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY)) { 136 if (adev->umc.ras && 137 adev->umc.ras->ecc_info_query_ras_error_count) 138 adev->umc.ras->ecc_info_query_ras_error_count(adev, ras_error_status); 139 140 if (adev->umc.ras && 141 adev->umc.ras->ecc_info_query_ras_error_address && 142 adev->umc.max_ras_err_cnt_per_query) { 143 err_data->err_addr = 144 kcalloc(adev->umc.max_ras_err_cnt_per_query, 145 sizeof(struct eeprom_table_record), GFP_KERNEL); 146 147 /* still call query_ras_error_address to clear error status 148 * even NOMEM error is encountered 149 */ 150 if(!err_data->err_addr) 151 dev_warn(adev->dev, "Failed to alloc memory for " 152 "umc error address record!\n"); 153 else 154 err_data->err_addr_len = adev->umc.max_ras_err_cnt_per_query; 155 156 /* umc query_ras_error_address is also responsible for clearing 157 * error status 158 */ 159 adev->umc.ras->ecc_info_query_ras_error_address(adev, ras_error_status); 160 } 161 } 162 163 /* only uncorrectable error needs gpu reset */ 164 if (err_data->ue_count || err_data->de_count) { 165 err_count = err_data->ue_count + err_data->de_count; 166 if ((amdgpu_bad_page_threshold != 0) && 167 err_data->err_addr_cnt) { 168 amdgpu_ras_add_bad_pages(adev, err_data->err_addr, 169 err_data->err_addr_cnt); 170 amdgpu_ras_save_bad_pages(adev, &err_count); 171 172 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs); 173 174 if (con->update_channel_flag == true) { 175 amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap); 176 con->update_channel_flag = false; 177 } 178 } 179 } 180 181 kfree(err_data->err_addr); 182 err_data->err_addr = NULL; 183 184 mutex_unlock(&con->page_retirement_lock); 185 } 186 187 static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev, 188 void *ras_error_status, 189 struct amdgpu_iv_entry *entry, 190 uint32_t reset) 191 { 192 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 193 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 194 195 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 196 amdgpu_umc_handle_bad_pages(adev, ras_error_status); 197 198 if ((err_data->ue_count || err_data->de_count) && 199 (reset || (con && con->is_rma))) { 200 con->gpu_reset_flags |= reset; 201 amdgpu_ras_reset_gpu(adev); 202 } 203 204 return AMDGPU_RAS_SUCCESS; 205 } 206 207 int amdgpu_umc_bad_page_polling_timeout(struct amdgpu_device *adev, 208 uint32_t reset, uint32_t timeout_ms) 209 { 210 struct ras_err_data err_data; 211 struct ras_common_if head = { 212 .block = AMDGPU_RAS_BLOCK__UMC, 213 }; 214 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head); 215 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 216 uint32_t timeout = timeout_ms; 217 218 memset(&err_data, 0, sizeof(err_data)); 219 amdgpu_ras_error_data_init(&err_data); 220 221 do { 222 223 amdgpu_umc_handle_bad_pages(adev, &err_data); 224 225 if (timeout && !err_data.de_count) { 226 msleep(1); 227 timeout--; 228 } 229 230 } while (timeout && !err_data.de_count); 231 232 if (!timeout) 233 dev_warn(adev->dev, "Can't find bad pages\n"); 234 235 if (err_data.de_count) 236 dev_info(adev->dev, "%ld new deferred hardware errors detected\n", err_data.de_count); 237 238 if (obj) { 239 obj->err_data.ue_count += err_data.ue_count; 240 obj->err_data.ce_count += err_data.ce_count; 241 obj->err_data.de_count += err_data.de_count; 242 } 243 244 amdgpu_ras_error_data_fini(&err_data); 245 246 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 247 248 if (reset || (err_data.err_addr_cnt && con && con->is_rma)) { 249 con->gpu_reset_flags |= reset; 250 amdgpu_ras_reset_gpu(adev); 251 } 252 253 return 0; 254 } 255 256 int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev, 257 enum amdgpu_ras_block block, uint16_t pasid, 258 pasid_notify pasid_fn, void *data, uint32_t reset) 259 { 260 int ret = AMDGPU_RAS_SUCCESS; 261 262 if (adev->gmc.xgmi.connected_to_cpu || 263 adev->gmc.is_app_apu) { 264 if (reset) { 265 /* MCA poison handler is only responsible for GPU reset, 266 * let MCA notifier do page retirement. 267 */ 268 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 269 amdgpu_ras_reset_gpu(adev); 270 } 271 return ret; 272 } 273 274 if (!amdgpu_sriov_vf(adev)) { 275 if (amdgpu_ip_version(adev, UMC_HWIP, 0) < IP_VERSION(12, 0, 0)) { 276 struct ras_err_data err_data; 277 struct ras_common_if head = { 278 .block = AMDGPU_RAS_BLOCK__UMC, 279 }; 280 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head); 281 282 ret = amdgpu_ras_error_data_init(&err_data); 283 if (ret) 284 return ret; 285 286 ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset); 287 288 if (ret == AMDGPU_RAS_SUCCESS && obj) { 289 obj->err_data.ue_count += err_data.ue_count; 290 obj->err_data.ce_count += err_data.ce_count; 291 obj->err_data.de_count += err_data.de_count; 292 } 293 294 amdgpu_ras_error_data_fini(&err_data); 295 } else { 296 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 297 int ret; 298 299 ret = amdgpu_ras_put_poison_req(adev, 300 block, pasid, pasid_fn, data, reset); 301 if (!ret) { 302 atomic_inc(&con->page_retirement_req_cnt); 303 wake_up(&con->page_retirement_wq); 304 } 305 } 306 } else { 307 if (adev->virt.ops && adev->virt.ops->ras_poison_handler) 308 adev->virt.ops->ras_poison_handler(adev, block); 309 else 310 dev_warn(adev->dev, 311 "No ras_poison_handler interface in SRIOV!\n"); 312 } 313 314 return ret; 315 } 316 317 int amdgpu_umc_poison_handler(struct amdgpu_device *adev, 318 enum amdgpu_ras_block block, uint32_t reset) 319 { 320 return amdgpu_umc_pasid_poison_handler(adev, 321 block, 0, NULL, NULL, reset); 322 } 323 324 int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, 325 void *ras_error_status, 326 struct amdgpu_iv_entry *entry) 327 { 328 return amdgpu_umc_do_page_retirement(adev, ras_error_status, entry, 329 AMDGPU_RAS_GPU_RESET_MODE1_RESET); 330 } 331 332 int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev) 333 { 334 int err; 335 struct amdgpu_umc_ras *ras; 336 337 if (!adev->umc.ras) 338 return 0; 339 340 ras = adev->umc.ras; 341 342 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 343 if (err) { 344 dev_err(adev->dev, "Failed to register umc ras block!\n"); 345 return err; 346 } 347 348 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); 349 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; 350 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 351 adev->umc.ras_if = &ras->ras_block.ras_comm; 352 353 if (!ras->ras_block.ras_late_init) 354 ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; 355 356 if (!ras->ras_block.ras_cb) 357 ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb; 358 359 return 0; 360 } 361 362 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 363 { 364 int r; 365 366 r = amdgpu_ras_block_late_init(adev, ras_block); 367 if (r) 368 return r; 369 370 if (amdgpu_ras_is_supported(adev, ras_block->block)) { 371 r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); 372 if (r) 373 goto late_fini; 374 } 375 376 /* ras init of specific umc version */ 377 if (adev->umc.ras && 378 adev->umc.ras->err_cnt_init) 379 adev->umc.ras->err_cnt_init(adev); 380 381 return 0; 382 383 late_fini: 384 amdgpu_ras_block_late_fini(adev, ras_block); 385 return r; 386 } 387 388 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, 389 struct amdgpu_irq_src *source, 390 struct amdgpu_iv_entry *entry) 391 { 392 struct ras_common_if *ras_if = adev->umc.ras_if; 393 struct ras_dispatch_if ih_data = { 394 .entry = entry, 395 }; 396 397 if (!ras_if) 398 return 0; 399 400 ih_data.head = *ras_if; 401 402 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 403 return 0; 404 } 405 406 int amdgpu_umc_fill_error_record(struct ras_err_data *err_data, 407 uint64_t err_addr, 408 uint64_t retired_page, 409 uint32_t channel_index, 410 uint32_t umc_inst) 411 { 412 struct eeprom_table_record *err_rec; 413 414 if (!err_data || 415 !err_data->err_addr || 416 (err_data->err_addr_cnt >= err_data->err_addr_len)) 417 return -EINVAL; 418 419 err_rec = &err_data->err_addr[err_data->err_addr_cnt]; 420 421 err_rec->address = err_addr; 422 /* page frame address is saved */ 423 err_rec->retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT; 424 err_rec->ts = (uint64_t)ktime_get_real_seconds(); 425 err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE; 426 err_rec->cu = 0; 427 err_rec->mem_channel = channel_index; 428 err_rec->mcumc_id = umc_inst; 429 430 err_data->err_addr_cnt++; 431 432 return 0; 433 } 434 435 int amdgpu_umc_loop_channels(struct amdgpu_device *adev, 436 umc_func func, void *data) 437 { 438 uint32_t node_inst = 0; 439 uint32_t umc_inst = 0; 440 uint32_t ch_inst = 0; 441 int ret = 0; 442 443 if (adev->umc.node_inst_num) { 444 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) { 445 ret = func(adev, node_inst, umc_inst, ch_inst, data); 446 if (ret) { 447 dev_err(adev->dev, "Node %d umc %d ch %d func returns %d\n", 448 node_inst, umc_inst, ch_inst, ret); 449 return ret; 450 } 451 } 452 } else { 453 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { 454 ret = func(adev, 0, umc_inst, ch_inst, data); 455 if (ret) { 456 dev_err(adev->dev, "Umc %d ch %d func returns %d\n", 457 umc_inst, ch_inst, ret); 458 return ret; 459 } 460 } 461 } 462 463 return 0; 464 } 465 466 int amdgpu_umc_update_ecc_status(struct amdgpu_device *adev, 467 uint64_t status, uint64_t ipid, uint64_t addr) 468 { 469 if (adev->umc.ras->update_ecc_status) 470 return adev->umc.ras->update_ecc_status(adev, 471 status, ipid, addr); 472 return 0; 473 } 474 475 static int amdgpu_umc_uint64_cmp(const void *a, const void *b) 476 { 477 uint64_t *addr_a = (uint64_t *)a; 478 uint64_t *addr_b = (uint64_t *)b; 479 480 if (*addr_a > *addr_b) 481 return 1; 482 else if (*addr_a < *addr_b) 483 return -1; 484 else 485 return 0; 486 } 487 488 /* Use string hash to avoid logging the same bad pages repeatedly */ 489 int amdgpu_umc_build_pages_hash(struct amdgpu_device *adev, 490 uint64_t *pfns, int len, uint64_t *val) 491 { 492 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 493 char buf[MAX_UMC_HASH_STRING_SIZE] = {0}; 494 int offset = 0, i = 0; 495 uint64_t hash_val; 496 497 if (!pfns || !len) 498 return -EINVAL; 499 500 sort(pfns, len, sizeof(uint64_t), amdgpu_umc_uint64_cmp, NULL); 501 502 for (i = 0; i < len; i++) 503 offset += snprintf(&buf[offset], sizeof(buf) - offset, "%llx", pfns[i]); 504 505 hash_val = siphash(buf, offset, &con->umc_ecc_log.ecc_key); 506 507 *val = hash_val; 508 509 return 0; 510 } 511 512 int amdgpu_umc_logs_ecc_err(struct amdgpu_device *adev, 513 struct radix_tree_root *ecc_tree, struct ras_ecc_err *ecc_err) 514 { 515 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 516 struct ras_ecc_log_info *ecc_log; 517 int ret; 518 519 ecc_log = &con->umc_ecc_log; 520 521 mutex_lock(&ecc_log->lock); 522 ret = radix_tree_insert(ecc_tree, ecc_err->hash_index, ecc_err); 523 if (!ret) { 524 struct ras_err_pages *err_pages = &ecc_err->err_pages; 525 int i; 526 527 /* Reserve memory */ 528 for (i = 0; i < err_pages->count; i++) 529 amdgpu_ras_reserve_page(adev, err_pages->pfn[i]); 530 531 radix_tree_tag_set(ecc_tree, 532 ecc_err->hash_index, UMC_ECC_NEW_DETECTED_TAG); 533 } 534 mutex_unlock(&ecc_log->lock); 535 536 return ret; 537 } 538