1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/sort.h> 25 #include "amdgpu.h" 26 #include "umc_v6_7.h" 27 #define MAX_UMC_POISON_POLLING_TIME_SYNC 20 //ms 28 29 #define MAX_UMC_HASH_STRING_SIZE 256 30 31 static int amdgpu_umc_convert_error_address(struct amdgpu_device *adev, 32 struct ras_err_data *err_data, uint64_t err_addr, 33 uint32_t ch_inst, uint32_t umc_inst) 34 { 35 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 36 case IP_VERSION(6, 7, 0): 37 umc_v6_7_convert_error_address(adev, 38 err_data, err_addr, ch_inst, umc_inst); 39 break; 40 default: 41 dev_warn(adev->dev, 42 "UMC address to Physical address translation is not supported\n"); 43 return AMDGPU_RAS_FAIL; 44 } 45 46 return AMDGPU_RAS_SUCCESS; 47 } 48 49 int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev, 50 uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst) 51 { 52 struct ras_err_data err_data; 53 int ret; 54 55 ret = amdgpu_ras_error_data_init(&err_data); 56 if (ret) 57 return ret; 58 59 err_data.err_addr = 60 kcalloc(adev->umc.max_ras_err_cnt_per_query, 61 sizeof(struct eeprom_table_record), GFP_KERNEL); 62 if (!err_data.err_addr) { 63 dev_warn(adev->dev, 64 "Failed to alloc memory for umc error record in MCA notifier!\n"); 65 ret = AMDGPU_RAS_FAIL; 66 goto out_fini_err_data; 67 } 68 69 err_data.err_addr_len = adev->umc.max_ras_err_cnt_per_query; 70 71 /* 72 * Translate UMC channel address to Physical address 73 */ 74 ret = amdgpu_umc_convert_error_address(adev, &err_data, err_addr, 75 ch_inst, umc_inst); 76 if (ret) 77 goto out_free_err_addr; 78 79 if (amdgpu_bad_page_threshold != 0) { 80 amdgpu_ras_add_bad_pages(adev, err_data.err_addr, 81 err_data.err_addr_cnt); 82 amdgpu_ras_save_bad_pages(adev, NULL); 83 } 84 85 out_free_err_addr: 86 kfree(err_data.err_addr); 87 88 out_fini_err_data: 89 amdgpu_ras_error_data_fini(&err_data); 90 91 return ret; 92 } 93 94 void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev, 95 void *ras_error_status) 96 { 97 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 98 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 99 unsigned int error_query_mode; 100 int ret = 0; 101 unsigned long err_count; 102 103 amdgpu_ras_get_error_query_mode(adev, &error_query_mode); 104 105 mutex_lock(&con->page_retirement_lock); 106 ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(con->umc_ecc)); 107 if (ret == -EOPNOTSUPP && 108 error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) { 109 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && 110 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) 111 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status); 112 113 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && 114 adev->umc.ras->ras_block.hw_ops->query_ras_error_address && 115 adev->umc.max_ras_err_cnt_per_query) { 116 err_data->err_addr = 117 kcalloc(adev->umc.max_ras_err_cnt_per_query, 118 sizeof(struct eeprom_table_record), GFP_KERNEL); 119 120 /* still call query_ras_error_address to clear error status 121 * even NOMEM error is encountered 122 */ 123 if(!err_data->err_addr) 124 dev_warn(adev->dev, "Failed to alloc memory for " 125 "umc error address record!\n"); 126 else 127 err_data->err_addr_len = adev->umc.max_ras_err_cnt_per_query; 128 129 /* umc query_ras_error_address is also responsible for clearing 130 * error status 131 */ 132 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, ras_error_status); 133 } 134 } else if (error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY || 135 (!ret && error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY)) { 136 if (adev->umc.ras && 137 adev->umc.ras->ecc_info_query_ras_error_count) 138 adev->umc.ras->ecc_info_query_ras_error_count(adev, ras_error_status); 139 140 if (adev->umc.ras && 141 adev->umc.ras->ecc_info_query_ras_error_address && 142 adev->umc.max_ras_err_cnt_per_query) { 143 err_data->err_addr = 144 kcalloc(adev->umc.max_ras_err_cnt_per_query, 145 sizeof(struct eeprom_table_record), GFP_KERNEL); 146 147 /* still call query_ras_error_address to clear error status 148 * even NOMEM error is encountered 149 */ 150 if(!err_data->err_addr) 151 dev_warn(adev->dev, "Failed to alloc memory for " 152 "umc error address record!\n"); 153 else 154 err_data->err_addr_len = adev->umc.max_ras_err_cnt_per_query; 155 156 /* umc query_ras_error_address is also responsible for clearing 157 * error status 158 */ 159 adev->umc.ras->ecc_info_query_ras_error_address(adev, ras_error_status); 160 } 161 } 162 163 /* only uncorrectable error needs gpu reset */ 164 if (err_data->ue_count || err_data->de_count) { 165 err_count = err_data->ue_count + err_data->de_count; 166 if ((amdgpu_bad_page_threshold != 0) && 167 err_data->err_addr_cnt) { 168 amdgpu_ras_add_bad_pages(adev, err_data->err_addr, 169 err_data->err_addr_cnt); 170 amdgpu_ras_save_bad_pages(adev, &err_count); 171 172 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs); 173 174 if (con->update_channel_flag == true) { 175 amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap); 176 con->update_channel_flag = false; 177 } 178 } 179 } 180 181 kfree(err_data->err_addr); 182 183 mutex_unlock(&con->page_retirement_lock); 184 } 185 186 static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev, 187 void *ras_error_status, 188 struct amdgpu_iv_entry *entry, 189 uint32_t reset) 190 { 191 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 192 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 193 194 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 195 amdgpu_umc_handle_bad_pages(adev, ras_error_status); 196 197 if (err_data->ue_count && reset) { 198 con->gpu_reset_flags |= reset; 199 amdgpu_ras_reset_gpu(adev); 200 } 201 202 return AMDGPU_RAS_SUCCESS; 203 } 204 205 int amdgpu_umc_bad_page_polling_timeout(struct amdgpu_device *adev, 206 uint32_t reset, uint32_t timeout_ms) 207 { 208 struct ras_err_data err_data; 209 struct ras_common_if head = { 210 .block = AMDGPU_RAS_BLOCK__UMC, 211 }; 212 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head); 213 uint32_t timeout = timeout_ms; 214 215 memset(&err_data, 0, sizeof(err_data)); 216 amdgpu_ras_error_data_init(&err_data); 217 218 do { 219 220 amdgpu_umc_handle_bad_pages(adev, &err_data); 221 222 if (timeout && !err_data.de_count) { 223 msleep(1); 224 timeout--; 225 } 226 227 } while (timeout && !err_data.de_count); 228 229 if (!timeout) 230 dev_warn(adev->dev, "Can't find bad pages\n"); 231 232 if (err_data.de_count) 233 dev_info(adev->dev, "%ld new deferred hardware errors detected\n", err_data.de_count); 234 235 if (obj) { 236 obj->err_data.ue_count += err_data.ue_count; 237 obj->err_data.ce_count += err_data.ce_count; 238 obj->err_data.de_count += err_data.de_count; 239 } 240 241 amdgpu_ras_error_data_fini(&err_data); 242 243 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 244 245 if (reset) { 246 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 247 248 con->gpu_reset_flags |= reset; 249 amdgpu_ras_reset_gpu(adev); 250 } 251 252 return 0; 253 } 254 255 int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev, 256 enum amdgpu_ras_block block, uint16_t pasid, 257 pasid_notify pasid_fn, void *data, uint32_t reset) 258 { 259 int ret = AMDGPU_RAS_SUCCESS; 260 261 if (adev->gmc.xgmi.connected_to_cpu || 262 adev->gmc.is_app_apu) { 263 if (reset) { 264 /* MCA poison handler is only responsible for GPU reset, 265 * let MCA notifier do page retirement. 266 */ 267 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 268 amdgpu_ras_reset_gpu(adev); 269 } 270 return ret; 271 } 272 273 if (!amdgpu_sriov_vf(adev)) { 274 if (amdgpu_ip_version(adev, UMC_HWIP, 0) < IP_VERSION(12, 0, 0)) { 275 struct ras_err_data err_data; 276 struct ras_common_if head = { 277 .block = AMDGPU_RAS_BLOCK__UMC, 278 }; 279 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head); 280 281 ret = amdgpu_ras_error_data_init(&err_data); 282 if (ret) 283 return ret; 284 285 ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset); 286 287 if (ret == AMDGPU_RAS_SUCCESS && obj) { 288 obj->err_data.ue_count += err_data.ue_count; 289 obj->err_data.ce_count += err_data.ce_count; 290 obj->err_data.de_count += err_data.de_count; 291 } 292 293 amdgpu_ras_error_data_fini(&err_data); 294 } else { 295 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 296 297 amdgpu_ras_put_poison_req(adev, 298 block, pasid, pasid_fn, data, reset); 299 300 atomic_inc(&con->page_retirement_req_cnt); 301 302 wake_up(&con->page_retirement_wq); 303 } 304 } else { 305 if (adev->virt.ops && adev->virt.ops->ras_poison_handler) 306 adev->virt.ops->ras_poison_handler(adev, block); 307 else 308 dev_warn(adev->dev, 309 "No ras_poison_handler interface in SRIOV!\n"); 310 } 311 312 return ret; 313 } 314 315 int amdgpu_umc_poison_handler(struct amdgpu_device *adev, 316 enum amdgpu_ras_block block, uint32_t reset) 317 { 318 return amdgpu_umc_pasid_poison_handler(adev, 319 block, 0, NULL, NULL, reset); 320 } 321 322 int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, 323 void *ras_error_status, 324 struct amdgpu_iv_entry *entry) 325 { 326 return amdgpu_umc_do_page_retirement(adev, ras_error_status, entry, 327 AMDGPU_RAS_GPU_RESET_MODE1_RESET); 328 } 329 330 int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev) 331 { 332 int err; 333 struct amdgpu_umc_ras *ras; 334 335 if (!adev->umc.ras) 336 return 0; 337 338 ras = adev->umc.ras; 339 340 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 341 if (err) { 342 dev_err(adev->dev, "Failed to register umc ras block!\n"); 343 return err; 344 } 345 346 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); 347 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; 348 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 349 adev->umc.ras_if = &ras->ras_block.ras_comm; 350 351 if (!ras->ras_block.ras_late_init) 352 ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; 353 354 if (!ras->ras_block.ras_cb) 355 ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb; 356 357 return 0; 358 } 359 360 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 361 { 362 int r; 363 364 r = amdgpu_ras_block_late_init(adev, ras_block); 365 if (r) 366 return r; 367 368 if (amdgpu_ras_is_supported(adev, ras_block->block)) { 369 r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); 370 if (r) 371 goto late_fini; 372 } 373 374 /* ras init of specific umc version */ 375 if (adev->umc.ras && 376 adev->umc.ras->err_cnt_init) 377 adev->umc.ras->err_cnt_init(adev); 378 379 return 0; 380 381 late_fini: 382 amdgpu_ras_block_late_fini(adev, ras_block); 383 return r; 384 } 385 386 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, 387 struct amdgpu_irq_src *source, 388 struct amdgpu_iv_entry *entry) 389 { 390 struct ras_common_if *ras_if = adev->umc.ras_if; 391 struct ras_dispatch_if ih_data = { 392 .entry = entry, 393 }; 394 395 if (!ras_if) 396 return 0; 397 398 ih_data.head = *ras_if; 399 400 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 401 return 0; 402 } 403 404 int amdgpu_umc_fill_error_record(struct ras_err_data *err_data, 405 uint64_t err_addr, 406 uint64_t retired_page, 407 uint32_t channel_index, 408 uint32_t umc_inst) 409 { 410 struct eeprom_table_record *err_rec; 411 412 if (!err_data || 413 !err_data->err_addr || 414 (err_data->err_addr_cnt >= err_data->err_addr_len)) 415 return -EINVAL; 416 417 err_rec = &err_data->err_addr[err_data->err_addr_cnt]; 418 419 err_rec->address = err_addr; 420 /* page frame address is saved */ 421 err_rec->retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT; 422 err_rec->ts = (uint64_t)ktime_get_real_seconds(); 423 err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE; 424 err_rec->cu = 0; 425 err_rec->mem_channel = channel_index; 426 err_rec->mcumc_id = umc_inst; 427 428 err_data->err_addr_cnt++; 429 430 return 0; 431 } 432 433 int amdgpu_umc_loop_channels(struct amdgpu_device *adev, 434 umc_func func, void *data) 435 { 436 uint32_t node_inst = 0; 437 uint32_t umc_inst = 0; 438 uint32_t ch_inst = 0; 439 int ret = 0; 440 441 if (adev->umc.node_inst_num) { 442 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) { 443 ret = func(adev, node_inst, umc_inst, ch_inst, data); 444 if (ret) { 445 dev_err(adev->dev, "Node %d umc %d ch %d func returns %d\n", 446 node_inst, umc_inst, ch_inst, ret); 447 return ret; 448 } 449 } 450 } else { 451 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { 452 ret = func(adev, 0, umc_inst, ch_inst, data); 453 if (ret) { 454 dev_err(adev->dev, "Umc %d ch %d func returns %d\n", 455 umc_inst, ch_inst, ret); 456 return ret; 457 } 458 } 459 } 460 461 return 0; 462 } 463 464 int amdgpu_umc_update_ecc_status(struct amdgpu_device *adev, 465 uint64_t status, uint64_t ipid, uint64_t addr) 466 { 467 if (adev->umc.ras->update_ecc_status) 468 return adev->umc.ras->update_ecc_status(adev, 469 status, ipid, addr); 470 return 0; 471 } 472 473 static int amdgpu_umc_uint64_cmp(const void *a, const void *b) 474 { 475 uint64_t *addr_a = (uint64_t *)a; 476 uint64_t *addr_b = (uint64_t *)b; 477 478 if (*addr_a > *addr_b) 479 return 1; 480 else if (*addr_a < *addr_b) 481 return -1; 482 else 483 return 0; 484 } 485 486 /* Use string hash to avoid logging the same bad pages repeatedly */ 487 int amdgpu_umc_build_pages_hash(struct amdgpu_device *adev, 488 uint64_t *pfns, int len, uint64_t *val) 489 { 490 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 491 char buf[MAX_UMC_HASH_STRING_SIZE] = {0}; 492 int offset = 0, i = 0; 493 uint64_t hash_val; 494 495 if (!pfns || !len) 496 return -EINVAL; 497 498 sort(pfns, len, sizeof(uint64_t), amdgpu_umc_uint64_cmp, NULL); 499 500 for (i = 0; i < len; i++) 501 offset += snprintf(&buf[offset], sizeof(buf) - offset, "%llx", pfns[i]); 502 503 hash_val = siphash(buf, offset, &con->umc_ecc_log.ecc_key); 504 505 *val = hash_val; 506 507 return 0; 508 } 509 510 int amdgpu_umc_logs_ecc_err(struct amdgpu_device *adev, 511 struct radix_tree_root *ecc_tree, struct ras_ecc_err *ecc_err) 512 { 513 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 514 struct ras_ecc_log_info *ecc_log; 515 int ret; 516 517 ecc_log = &con->umc_ecc_log; 518 519 mutex_lock(&ecc_log->lock); 520 ret = radix_tree_insert(ecc_tree, ecc_err->hash_index, ecc_err); 521 if (!ret) { 522 struct ras_err_pages *err_pages = &ecc_err->err_pages; 523 int i; 524 525 /* Reserve memory */ 526 for (i = 0; i < err_pages->count; i++) 527 amdgpu_ras_reserve_page(adev, err_pages->pfn[i]); 528 529 radix_tree_tag_set(ecc_tree, 530 ecc_err->hash_index, UMC_ECC_NEW_DETECTED_TAG); 531 } 532 mutex_unlock(&ecc_log->lock); 533 534 return ret; 535 } 536